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[Qemu-commits] [qemu/qemu] d20bd4: target/s390x: Map existing FAC_* name

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] d20bd4: target/s390x: Map existing FAC_* names to S390_FEA...
Date: Fri, 23 Jun 2017 10:54:32 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: d20bd43c4ce2dcdf7d6fa24eb8a29bcef29fb652
      
https://github.com/qemu/qemu/commit/d20bd43c4ce2dcdf7d6fa24eb8a29bcef29fb652
  Author: Richard Henderson <address@hidden>
  Date:   2017-06-23 (Fri, 23 Jun 2017)

  Changed paths:
    M target/s390x/translate.c

  Log Message:
  -----------
  target/s390x: Map existing FAC_* names to S390_FEAT_* names

The FAC_ names were placeholders prior to the introduction
of the current facility modeling.

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: c8bd95377babc3bd60f86cb3e5b24e74097cf6a9
      
https://github.com/qemu/qemu/commit/c8bd95377babc3bd60f86cb3e5b24e74097cf6a9
  Author: David Hildenbrand <address@hidden>
  Date:   2017-06-23 (Fri, 23 Jun 2017)

  Changed paths:
    M target/s390x/cpu.h
    M target/s390x/translate.c

  Log Message:
  -----------
  target/s390x: change PSW_SHIFT_KEY

Such shifts are usually used to easily extract the PSW KEY from the PSW
mask, so let's avoid the confusing offset of 4.

Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 3e7e5e0bc10d32d7cc41d0a39113473a3abfc657
      
https://github.com/qemu/qemu/commit/3e7e5e0bc10d32d7cc41d0a39113473a3abfc657
  Author: David Hildenbrand <address@hidden>
  Date:   2017-06-23 (Fri, 23 Jun 2017)

  Changed paths:
    M target/s390x/cpu.h
    M target/s390x/cpu_models.c
    M target/s390x/helper.h
    M target/s390x/insn-data.def
    M target/s390x/mem_helper.c
    M target/s390x/translate.c

  Log Message:
  -----------
  target/s390x: implement mvcos instruction

This adds support for the MOVE WITH OPTIONAL SPECIFICATIONS (MVCOS)
instruction. Allow to enable it for the qemu cpu model using

qemu-system-s390x ... -cpu qemu,mvcos=on ...

This allows to boot linux kernel that uses it for uacccess.

We are missing (as for most other part) low address protection checks,
PSW key / storage key checks and support for AR-mode.

We fake an ADDRESSING exception when called from problem state (which
seems to rely on PSW key checks to be in place) and if AR-mode is used.
user mode will always see a PRIVILEDGED exception.

This patch is based on an original patch by Miroslav Benes (thanks!).

Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: e1a5d922b44946e0453189faff41464f95163c10
      
https://github.com/qemu/qemu/commit/e1a5d922b44946e0453189faff41464f95163c10
  Author: Richard Henderson <address@hidden>
  Date:   2017-06-23 (Fri, 23 Jun 2017)

  Changed paths:
    M target/s390x/cpu_models.c

  Log Message:
  -----------
  target/s390x: Mark FPSEH facility as available

This facility bit includes DFP-rounding, FPR-GR-transfer,
FPS-sign-handling, and IEEE-exception-simulation.  We do
support all of these.

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 45aa9aa3b7730b38403553355b36a29f8905916a
      
https://github.com/qemu/qemu/commit/45aa9aa3b7730b38403553355b36a29f8905916a
  Author: Richard Henderson <address@hidden>
  Date:   2017-06-23 (Fri, 23 Jun 2017)

  Changed paths:
    M target/s390x/insn-data.def
    M target/s390x/insn-format.def
    M target/s390x/translate.c

  Log Message:
  -----------
  target/s390x: Implement load-on-condition-2 insns

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: c2a5c1d718eabfde04ebabf2434168b0716107cb
      
https://github.com/qemu/qemu/commit/c2a5c1d718eabfde04ebabf2434168b0716107cb
  Author: Richard Henderson <address@hidden>
  Date:   2017-06-23 (Fri, 23 Jun 2017)

  Changed paths:
    M target/s390x/insn-data.def
    M target/s390x/translate.c

  Log Message:
  -----------
  target/s390x: Implement load-and-zero-rightmost-byte insns

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 37b8638d4347aaa72d359dc35e529937ec250bf4
      
https://github.com/qemu/qemu/commit/37b8638d4347aaa72d359dc35e529937ec250bf4
  Author: Richard Henderson <address@hidden>
  Date:   2017-06-23 (Fri, 23 Jun 2017)

  Changed paths:
    M target/s390x/cpu_models.c

  Log Message:
  -----------
  target/s390x: Mark STFLE_53 facility as available

This facility bit includes load-on-condition-2 and
load-and-zero-rightmost-byte.

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 6a68acd5b7bbf191a74d47ab38e27e5864d326d3
      
https://github.com/qemu/qemu/commit/6a68acd5b7bbf191a74d47ab38e27e5864d326d3
  Author: Richard Henderson <address@hidden>
  Date:   2017-06-23 (Fri, 23 Jun 2017)

  Changed paths:
    M target/s390x/insn-data.def
    M target/s390x/translate.c

  Log Message:
  -----------
  target/s390x: Implement execution-hint insns

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 632c61a9b891affe3fe1037b16231c4a45b87d58
      
https://github.com/qemu/qemu/commit/632c61a9b891affe3fe1037b16231c4a45b87d58
  Author: Richard Henderson <address@hidden>
  Date:   2017-06-23 (Fri, 23 Jun 2017)

  Changed paths:
    M target/s390x/insn-data.def
    M target/s390x/translate.c

  Log Message:
  -----------
  target/s390x: Implement processor-assist insn

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: afa26f3bae18992cc9598a2cb1a9a09d2e813f76
      
https://github.com/qemu/qemu/commit/afa26f3bae18992cc9598a2cb1a9a09d2e813f76
  Author: Richard Henderson <address@hidden>
  Date:   2017-06-23 (Fri, 23 Jun 2017)

  Changed paths:
    M target/s390x/cpu_models.c

  Log Message:
  -----------
  target/s390x: Mark STFLE_49 facility as available

This facility bit includes execution-hint, load-and-trap,
miscellaneous-instruction-extensions and processor-assist.

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 3c39c800bf8fb22222372f9ae84423f966f6da98
      
https://github.com/qemu/qemu/commit/3c39c800bf8fb22222372f9ae84423f966f6da98
  Author: Richard Henderson <address@hidden>
  Date:   2017-06-23 (Fri, 23 Jun 2017)

  Changed paths:
    M target/s390x/mem_helper.c
    M target/s390x/translate.c

  Log Message:
  -----------
  target/s390x: Finish implementing ETF2-ENH

Missed the proper alignment in TRTO/TRTT, and ignoring the M3
field for all TRXX insns without ETF2-ENH.

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 159fed45db25c0c82f3833509502c8242a65c097
      
https://github.com/qemu/qemu/commit/159fed45db25c0c82f3833509502c8242a65c097
  Author: Richard Henderson <address@hidden>
  Date:   2017-06-23 (Fri, 23 Jun 2017)

  Changed paths:
    M target/s390x/cpu.h
    M target/s390x/translate.c

  Log Message:
  -----------
  target/s390x: Clean up TB flag bits

Most of the PSW bits that were being copied into TB->flags
are not relevant to translation.  Removing those that are
unnecessary reduces the amount of translation required.

Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: faf1c63d34861734895521277153c6c0e72b395c
      
https://github.com/qemu/qemu/commit/faf1c63d34861734895521277153c6c0e72b395c
  Author: David Hildenbrand <address@hidden>
  Date:   2017-06-23 (Fri, 23 Jun 2017)

  Changed paths:
    M target/s390x/cpu_models.c
    M target/s390x/mem_helper.c
    M target/s390x/translate.c

  Log Message:
  -----------
  target/s390x: Indicate and check for local tlb clearing

Let's allow to enable it for the qemu cpu model and correctly emulate
it.

Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 97b95aae3bc47eccb06c522a5945a8566b64cc86
      
https://github.com/qemu/qemu/commit/97b95aae3bc47eccb06c522a5945a8566b64cc86
  Author: David Hildenbrand <address@hidden>
  Date:   2017-06-23 (Fri, 23 Jun 2017)

  Changed paths:
    M target/s390x/mem_helper.c

  Log Message:
  -----------
  target/s390x: Improve heuristic for ipte

If only the page index is set, most likely we don't have a valid
virtual address. Let's do a full tlb flush for that case.

Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: be7f28de5d7f635647d7991ace96c54d9f724be4
      
https://github.com/qemu/qemu/commit/be7f28de5d7f635647d7991ace96c54d9f724be4
  Author: David Hildenbrand <address@hidden>
  Date:   2017-06-23 (Fri, 23 Jun 2017)

  Changed paths:
    M target/s390x/cpu_models.c
    M target/s390x/helper.h
    M target/s390x/insn-data.def
    M target/s390x/mem_helper.c
    M target/s390x/translate.c

  Log Message:
  -----------
  target/s390x: Implement idte instruction

Let's keep it very simple for now and flush the complete tlb,
we currently can't find the right entries in our tlb, we would have
to store the used tables for each element.

As we now fully implement the DAT-enhancement facility, we can allow to
enable it for the qemu CPU model.

Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 931892e8a691a8a4151cc5fe1e13c14294bb28fb
      
https://github.com/qemu/qemu/commit/931892e8a691a8a4151cc5fe1e13c14294bb28fb
  Author: Peter Maydell <address@hidden>
  Date:   2017-06-23 (Fri, 23 Jun 2017)

  Changed paths:
    M target/s390x/cpu.h
    M target/s390x/cpu_models.c
    M target/s390x/helper.h
    M target/s390x/insn-data.def
    M target/s390x/insn-format.def
    M target/s390x/mem_helper.c
    M target/s390x/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-s390-20170623' into 
staging

Queued target/s390x patches

# gpg: Signature made Fri 23 Jun 2017 17:18:24 BST
# gpg:                using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <address@hidden>"
# gpg:                 aka "Richard Henderson <address@hidden>"
# gpg:                 aka "Richard Henderson <address@hidden>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC  16A4 AD12 70CC 4DD0 279B

* remotes/rth/tags/pull-s390-20170623:
  target/s390x: Implement idte instruction
  target/s390x: Improve heuristic for ipte
  target/s390x: Indicate and check for local tlb clearing
  target/s390x: Clean up TB flag bits
  target/s390x: Finish implementing ETF2-ENH
  target/s390x: Mark STFLE_49 facility as available
  target/s390x: Implement processor-assist insn
  target/s390x: Implement execution-hint insns
  target/s390x: Mark STFLE_53 facility as available
  target/s390x: Implement load-and-zero-rightmost-byte insns
  target/s390x: Implement load-on-condition-2 insns
  target/s390x: Mark FPSEH facility as available
  target/s390x: implement mvcos instruction
  target/s390x: change PSW_SHIFT_KEY
  target/s390x: Map existing FAC_* names to S390_FEAT_* names

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/14a7fe1a2673...931892e8a691
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