[Qemu-commits] [qemu/qemu] 993063: libvixl: Correct build failures on NetBSD

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 993063fbb531d11f7ede59e5264308eafa6ee4ff
      
https://github.com/qemu/qemu/commit/993063fbb531d11f7ede59e5264308eafa6ee4ff
  Author: Kamil Rytarowski <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M disas/libvixl/Makefile.objs

  Log Message:
  -----------
  libvixl: Correct build failures on NetBSD

Ensure that C99 macros are defined regardless of the inclusion order of
headers in vixl. This is required at least on NetBSD.

The vixl/globals.h headers defines __STDC_CONSTANT_MACROS and must be
included before other system headers.

This file defines unconditionally the following macros, without altering
the original sources:
 - __STDC_CONSTANT_MACROS
 - __STDC_LIMIT_MACROS
 - __STDC_FORMAT_MACROS

Signed-off-by: Kamil Rytarowski <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a18e93125de1ce8caf1d6c00cc7f6f0c96f7854f
      
https://github.com/qemu/qemu/commit/a18e93125de1ce8caf1d6c00cc7f6f0c96f7854f
  Author: Andrew Jones <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M hw/core/loader.c

  Log Message:
  -----------
  load_uboot_image: don't assume a full header read

Don't allow load_uboot_image() to proceed when less bytes than
header-size was read.

Signed-off-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f5dc1b7767144dd44bdda99669e2b5bb8709a62b
      
https://github.com/qemu/qemu/commit/f5dc1b7767144dd44bdda99669e2b5bb8709a62b
  Author: Peter Maydell <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M hw/intc/arm_gicv3_cpuif.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1

We were setting the VBPR1 field of VMCR_EL2 to icv_min_vbpr()
on reset, but this is not correct. The field should reset to
the minimum value of ICV_BPR0_EL1 plus one.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 8193d4617cfdaec6e95c2087d9a13197dc261ef0
      
https://github.com/qemu/qemu/commit/8193d4617cfdaec6e95c2087d9a13197dc261ef0
  Author: Peter Maydell <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M hw/intc/arm_gicv3_cpuif.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum

icc_bpr_write() was not enforcing that writing a value below the
minimum for the BPR should behave as if the BPR was set to the
minimum value. This doesn't make a difference for the secure
BPRs (since we define the minimum for the QEMU implementation
as zero) but did mean we were allowing the NS BPR1 to be set to
0 when 1 should be the lowest value.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: a89ff39ee9016613356677941d8f70be40e06cc3
      
https://github.com/qemu/qemu/commit/a89ff39ee9016613356677941d8f70be40e06cc3
  Author: Peter Maydell <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M hw/intc/arm_gicv3_cpuif.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1

When we calculate the mask to use to get the group priority from
an interrupt priority, the way that NS BPR1 is handled differs
from how BPR0 and S BPR1 work -- a BPR1 value of 1 means
the group priority is in bits [7:1], whereas for BPR0 and S BPR1
this is indicated by a 0 BPR value.

Subtract 1 from the BPR value before creating the mask if
we're using the NS BPR value, for both hardware and virtual
interrupts, as the GICv3 pseudocode does, and fix the comments
accordingly.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 2b3ffa929249b15a75d8bde3e8e57a744f52aff0
      
https://github.com/qemu/qemu/commit/2b3ffa929249b15a75d8bde3e8e57a744f52aff0
  Author: Wei Huang <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: clear PMUVER field of AA64DFR0 when vPMU=off

The PMUv3 driver of linux kernel (in arch/arm64/kernel/perf_event.c)
relies on the PMUVER field of id_aa64dfr0_el1 to decide if PMU support
is present or not. This patch clears the PMUVER field under TCG mode
when vPMU=off. Without it, PMUv3 will init insider guest VMs even
with vPMU=off. This patch also removes a redundant line inside the
if-statement.

Signed-off-by: Wei Huang <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e517d95b63427fae9f03958dbc005c36b4ebf2cf
      
https://github.com/qemu/qemu/commit/e517d95b63427fae9f03958dbc005c36b4ebf2cf
  Author: Peter Maydell <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M target/arm/op_helper.c

  Log Message:
  -----------
  arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access()

When identifying the DFSR format for an alignment fault, use
the mmu index that we are passed, rather than calling cpu_mmu_index()
to get the mmu index for the current CPU state. This doesn't actually
make any difference since the only cases where the current MMU index
differs from the index used for the load are the "unprivileged
load/store" instructions, and in that case the mmu index may
differ but the translation regime is the same (apart from the
"use from Hyp mode" case which is UNPREDICTABLE).
However it's the more logical thing to do.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 8bd5c82030b2cb09d3eef6b444f1620911cc9fc5
      
https://github.com/qemu/qemu/commit/8bd5c82030b2cb09d3eef6b444f1620911cc9fc5
  Author: Peter Maydell <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/op_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  arm: Add support for M profile CPUs having different MMU index semantics

The M profile CPU's MPU has an awkward corner case which we
would like to implement with a different MMU index.

We can avoid having to bump the number of MMU modes ARM
uses, because some of our existing MMU indexes are only
used by non-M-profile CPUs, so we can borrow one.
To avoid that getting too confusing, clean up the code
to try to keep the two meanings of the index separate.

Instead of ARMMMUIdx enum values being identical to core QEMU
MMU index values, they are now the core index values with some
high bits set. Any particular CPU always uses the same high
bits (so eventually A profile cores and M profile cores will
use different bits). New functions arm_to_core_mmu_idx()
and core_to_arm_mmu_idx() convert between the two.

In general core index values are stored in 'int' types, and
ARM values are stored in ARMMMUIdx types.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: e7b921c2d9efc249f99b9feb0e7dca82c96aa5c4
      
https://github.com/qemu/qemu/commit/e7b921c2d9efc249f99b9feb0e7dca82c96aa5c4
  Author: Peter Maydell <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/translate.c

  Log Message:
  -----------
  arm: Use different ARMMMUIdx values for M profile

Make M profile use completely separate ARMMMUIdx values from
those that A profile CPUs use. This is a prelude to adding
support for the MPU and for v8M, which together will require
6 MMU indexes which don't map cleanly onto the A profile
uses:
 non secure User
 non secure Privileged
 non secure Privileged, execution priority < 0
 secure User
 secure Privileged
 secure Privileged, execution priority < 0

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 452a095526a0537f16c271516a2200877a272ea8
      
https://github.com/qemu/qemu/commit/452a095526a0537f16c271516a2200877a272ea8
  Author: Peter Maydell <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/machine.c

  Log Message:
  -----------
  arm: Clean up handling of no-MPU PMSA CPUs

ARM CPUs come in two flavours:
 * proper MMU ("VMSA")
 * only an MPU ("PMSA")
For PMSA, the MPU may be implemented, or not (in which case there
is default "always acts the same" behaviour, but it isn't guest
programmable).

QEMU is a bit confused about how we indicate this: we have an
ARM_FEATURE_MPU, but it's not clear whether this indicates
"PMSA, not VMSA" or "PMSA and MPU present" , and sometimes we
use it for one purpose and sometimes the other.

Currently trying to implement a PMSA-without-MPU core won't
work correctly because we turn off the ARM_FEATURE_MPU bit
and then a lot of things which should still exist get
turned off too.

As the first step in cleaning this up, rename the feature
bit to ARM_FEATURE_PMSA, which indicates a PMSA CPU (with
or without MPU).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: f50cd31413d8bc9d1eef8edd1f878324543bf65d
      
https://github.com/qemu/qemu/commit/f50cd31413d8bc9d1eef8edd1f878324543bf65d
  Author: Peter Maydell <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  arm: Don't clear ARM_FEATURE_PMSA for no-mpu configs

Fix the handling of QOM properties for PMSA CPUs with no MPU:

Allow no-MPU to be specified by either:
 * has-mpu = false
 * pmsav7_dregion = 0
and make setting one imply the other. Don't clear the PMSA
feature bit in this situation.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 06312febfb2d35367006ef23608ddd6a131214d4
      
https://github.com/qemu/qemu/commit/06312febfb2d35367006ef23608ddd6a131214d4
  Author: Peter Maydell <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  arm: Don't let no-MPU PMSA cores write to SCTLR.M

If the CPU is a PMSA config with no MPU implemented, then the
SCTLR.M bit should be RAZ/WI, so that the guest can never
turn on the non-existent MPU.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: e9235c6983b261e04e897e8ff900b2b7a391e644
      
https://github.com/qemu/qemu/commit/e9235c6983b261e04e897e8ff900b2b7a391e644
  Author: Peter Maydell <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  arm: Remove unnecessary check on cpu->pmsav7_dregion

Now that we enforce both:
 * pmsav7_dregion == 0 implies has_mpu == false
 * PMSA with has_mpu == false means SCTLR.M cannot be set
we can remove a check on pmsav7_dregion from get_phys_addr_pmsav7(),
because we can only reach this code path if the MPU is enabled
(and so region_translation_disabled() returned false).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: c9f9f1246d630960bce45881e9c0d27b55be71e2
      
https://github.com/qemu/qemu/commit/c9f9f1246d630960bce45881e9c0d27b55be71e2
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  armv7m: Improve "-d mmu" tracing for PMSAv7 MPU

Improve the "-d mmu" tracing for the PMSAv7 MPU translation
process as an aid in debugging guest MPU configurations:
 * fix a missing newline for a guest-error log
 * report the region number with guest-error or unimp
   logs of bad region register values
 * add a log message for the overall result of the lookup
 * print "0x" prefix for hex values

Signed-off-by: Michael Davidsaver <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
[PMM: a little tidyup, report region number in all messages
 rather than just one]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3a00d560bcfca7ad04327062c1986a016c104b1f
      
https://github.com/qemu/qemu/commit/3a00d560bcfca7ad04327062c1986a016c104b1f
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  armv7m: Implement M profile default memory map

Add support for the M profile default memory map which is used
if the MPU is not present or disabled.

The main differences in behaviour from implementing this
correctly are that we set the PAGE_EXEC attribute on
the right regions of memory, such that device regions
are not executable.

Signed-off-by: Michael Davidsaver <address@hidden>
Message-id: address@hidden
[PMM: rephrased comment and commit message; don't mark
 the flash memory region as not-writable; list all
 the cases in the default map explicitly rather than
 using a 'default' case for the non-executable regions]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 790a11503cfb5e1dcd031ea2212bbebae4ca3cec
      
https://github.com/qemu/qemu/commit/790a11503cfb5e1dcd031ea2212bbebae4ca3cec
  Author: Peter Maydell <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  arm: All M profile cores are PMSA

All M profile CPUs are PMSA, so set the feature bit.
(We haven't actually implemented the M profile MPU register
interface yet, but setting this feature bit gives us closer
to correct behaviour for the MPU-disabled case.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 5dd0641d234e355597be62e5279d8a519c831625
      
https://github.com/qemu/qemu/commit/5dd0641d234e355597be62e5279d8a519c831625
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  armv7m: Classify faults as MemManage or BusFault

General logic is that operations stopped by the MPU are MemManage,
and those which go through the MPU and are caught by the unassigned
handle are BusFault. Distinguish these by looking at the
exception.fsr values, and set the CFSR bits and (if appropriate)
fill in the BFAR or MMFAR with the exception address.

Signed-off-by: Michael Davidsaver <address@hidden>
Message-id: address@hidden
[PMM: i-side faults do not set BFAR/MMFAR, only d-side;
 added some CPU_LOG_INT logging]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 29c483a506070e8f554c77d22686f405e30b9114
      
https://github.com/qemu/qemu/commit/29c483a506070e8f554c77d22686f405e30b9114
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/machine.c

  Log Message:
  -----------
  arm: add MPU support to M profile CPUs

The M series MPU is almost the same as the already implemented R
profile MPU (v7 PMSA).  So all we need to implement here is the MPU
register interface in the system register space.

This implementation has the same restriction as the R profile MPU
that it doesn't permit regions to be sized down smaller than 1K.

We also do not yet implement support for MPU_CTRL.HFNMIENA; this
bit should if zero disable use of the MPU when running HardFault,
NMI or with FAULTMASK set to 1 (ie at an execution priority of
less than zero) -- if the MPU is enabled we don't treat these
cases any differently.

Signed-off-by: Michael Davidsaver <address@hidden>
Message-id: address@hidden
[PMM: Keep all the bits in mpu_ctrl field, rather than
 using SCTLR bits for them; drop broken HFNMIENA support;
 various cleanup]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3bef7012560a7f0ea27b265105de5090ba117514
      
https://github.com/qemu/qemu/commit/3bef7012560a7f0ea27b265105de5090ba117514
  Author: Peter Maydell <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/translate.c

  Log Message:
  -----------
  arm: Implement HFNMIENA support for M profile MPU

Implement HFNMIENA support for the M profile MPU. This bit controls
whether the MPU is treated as enabled when executing at execution
priorities of less than zero (in NMI, HardFault or with the FAULTMASK
bit set).

Doing this requires us to use a different MMU index for "running
at execution priority < 0", because we will have different
access permissions for that case versus the normal case.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: ddabca757a4eb29f342f7f1d01634ccdbe0e3844
      
https://github.com/qemu/qemu/commit/ddabca757a4eb29f342f7f1d01634ccdbe0e3844
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M hw/i2c/aspeed_i2c.c

  Log Message:
  -----------
  aspeed/i2c: improve command handling

Multiple I2C commands can be fired simultaneously and the controller
execute the commands following these priorities:

  (1) Master Start Command
  (2) Master Transmit Command
  (3) Slave Transmit Command or Master Receive Command
  (4) Master Stop Command

The current code is incorrect with respect to the above sequence and
needs to be reworked to handle each individual command.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d0efdc1686405c3873703a8617daba54d3fbb75f
      
https://github.com/qemu/qemu/commit/d0efdc1686405c3873703a8617daba54d3fbb75f
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M hw/i2c/aspeed_i2c.c

  Log Message:
  -----------
  aspeed/i2c: handle LAST command under the RX command

Today, the LAST command is handled with the STOP command but this is
incorrect. Also nack the I2C bus when a LAST is issued.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4960f084cfb4d42bb8995dd23ccad168c3e4ad3a
      
https://github.com/qemu/qemu/commit/4960f084cfb4d42bb8995dd23ccad168c3e4ad3a
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M hw/i2c/aspeed_i2c.c

  Log Message:
  -----------
  aspeed/i2c: introduce a state machine

The Aspeed I2C controller maintains a state machine in the command
register, which is mostly used for debug.

Let's start adding a few states to handle abnormal STOP
commands. Today, the model uses the busy status of the bus as a
condition to do so but it is not precise enough.

Also remove the ABNORMAL bit for failing TX commands. This is
incorrect with respect to the specs.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2cf6cb500c78ee2256023d510b4a54013b861444
      
https://github.com/qemu/qemu/commit/2cf6cb500c78ee2256023d510b4a54013b861444
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: add some I2C devices to the Aspeed machines

Let's add an RTC to the palmetto BMC and a LM75 temperature sensor to
the AST2500 EVB to start with.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>


  Commit: 94a66456f15983f40874eff23a215ba8c74d2bdf
      
https://github.com/qemu/qemu/commit/94a66456f15983f40874eff23a215ba8c74d2bdf
  Author: Andrew Jones <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M hw/arm/virt-acpi-build.c

  Log Message:
  -----------
  hw/arm/virt-acpi-build: build SLIT when needed

Cc: Shannon Zhao <address@hidden>
Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c7637c04be257968e6df30de961a6a23a0ac3dd8
      
https://github.com/qemu/qemu/commit/c7637c04be257968e6df30de961a6a23a0ac3dd8
  Author: Andrew Jones <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: fdt: generate distance-map when needed

This is based on patch Shannon Zhao originally posted.

Cc: Shannon Zhao <address@hidden>
Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7693cd7cb6229ca034faa88497ddb3a5f27cfb41
      
https://github.com/qemu/qemu/commit/7693cd7cb6229ca034faa88497ddb3a5f27cfb41
  Author: Peter Maydell <address@hidden>
  Date:   2017-06-02 (Fri, 02 Jun 2017)

  Changed paths:
    M disas/libvixl/Makefile.objs
    M hw/arm/aspeed.c
    M hw/arm/virt-acpi-build.c
    M hw/arm/virt.c
    M hw/core/loader.c
    M hw/i2c/aspeed_i2c.c
    M hw/intc/arm_gicv3_cpuif.c
    M hw/intc/armv7m_nvic.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/machine.c
    M target/arm/op_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170602' 
into staging

target-arm queue:
 * virt: numa: provide ACPI distance info when needed
 * aspeed: fix i2c controller bugs
 * M profile: support MPU
 * gicv3: fix mishandling of BPR1, VBPR1
 * load_uboot_image: don't assume a full header read
 * libvixl: Correct build failures on NetBSD

# gpg: Signature made Fri 02 Jun 2017 12:00:42 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170602: (25 commits)
  hw/arm/virt: fdt: generate distance-map when needed
  hw/arm/virt-acpi-build: build SLIT when needed
  aspeed: add some I2C devices to the Aspeed machines
  aspeed/i2c: introduce a state machine
  aspeed/i2c: handle LAST command under the RX command
  aspeed/i2c: improve command handling
  arm: Implement HFNMIENA support for M profile MPU
  arm: add MPU support to M profile CPUs
  armv7m: Classify faults as MemManage or BusFault
  arm: All M profile cores are PMSA
  armv7m: Implement M profile default memory map
  armv7m: Improve "-d mmu" tracing for PMSAv7 MPU
  arm: Remove unnecessary check on cpu->pmsav7_dregion
  arm: Don't let no-MPU PMSA cores write to SCTLR.M
  arm: Don't clear ARM_FEATURE_PMSA for no-mpu configs
  arm: Clean up handling of no-MPU PMSA CPUs
  arm: Use different ARMMMUIdx values for M profile
  arm: Add support for M profile CPUs having different MMU index semantics
  arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access()
  target/arm: clear PMUVER field of AA64DFR0 when vPMU=off
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/43771d5d9231...7693cd7cb622