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[Qemu-commits] [qemu/qemu] 001b3c: arm: HVC and SMC encodings don't exis


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 001b3c: arm: HVC and SMC encodings don't exist for M profi...
Date: Mon, 20 Mar 2017 06:45:09 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 001b3cab51ebfcb13e8dd03ea25bfa3bd0c517a3
      
https://github.com/qemu/qemu/commit/001b3cab51ebfcb13e8dd03ea25bfa3bd0c517a3
  Author: Peter Maydell <address@hidden>
  Date:   2017-03-20 (Mon, 20 Mar 2017)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  arm: HVC and SMC encodings don't exist for M profile

M profile doesn't have the HVC or SMC encodings, so make them always
UNDEF rather than generating calls to helper functions that assume
A/R profile.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: 43ac65742319ef5ac4461daf43316b189cd21e89
      
https://github.com/qemu/qemu/commit/43ac65742319ef5ac4461daf43316b189cd21e89
  Author: Peter Maydell <address@hidden>
  Date:   2017-03-20 (Mon, 20 Mar 2017)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  arm: Don't decode MRS(banked) or MSR(banked) for M profile

M profile doesn't have the MSR(banked) and MRS(banked) instructions
and uses the encodings for different kinds of M-profile MRS/MSR.
Guard the relevant bits of the decode logic to make sure we don't
accidentally fall into them by accident on M-profile.

(The bit being checked for this (bit 5) is part of the SYSm field on
M-profile, but since no currently allocated system registers have
encodings with bit 5 of SYSm set, this hasn't been a problem in
practice.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: 3d54026fb06d1aea7ebb4e9825970b06bebcacac
      
https://github.com/qemu/qemu/commit/3d54026fb06d1aea7ebb4e9825970b06bebcacac
  Author: Peter Maydell <address@hidden>
  Date:   2017-03-20 (Mon, 20 Mar 2017)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  arm: Enforce should-be-1 bits in MRS decoding

The MRS instruction requires that bits [19..16] are all 1s, and for
A/R profile also that bits [7..0] are all 0s.  At this point in the
decode tree we have checked all of the rest of the instruction but
were allowing these to be any value.  If these bits are not set then
the result is architecturally UNPREDICTABLE, but choosing to UNDEF is
more helpful to the user and avoids unexpected odd behaviour if the
encodings are used for some purpose in future architecture versions.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: b28b3377d7e9ba35611d454d5a63ef50cab1f8c5
      
https://github.com/qemu/qemu/commit/b28b3377d7e9ba35611d454d5a63ef50cab1f8c5
  Author: Peter Maydell <address@hidden>
  Date:   2017-03-20 (Mon, 20 Mar 2017)

  Changed paths:
    M target/arm/helper.c
    M target/arm/translate.c

  Log Message:
  -----------
  arm: Fix APSR writes via M profile MSR

Our implementation of writes to the APSR for M-profile via the MSR
instruction was badly broken.

First and worst, we had the sense wrong on the test of bit 2 of the
SYSm field -- this is supposed to request an APSR write if bit 2 is 0
but we were doing it if bit 2 was 1.  This bug was introduced in
commit 58117c9bb429cd, so hasn't been in a QEMU release.

Secondly, the choice of exactly which parts of APSR should be written
is defined by bits in the 'mask' field.  We were not passing these
through from instruction decode, making it impossible to check them
in the helper.

Pass the mask bits through from the instruction decode to the helper
function and process them appropriately; fix the wrong sense of the
SYSm bit 2 check.

Invalid mask values and invalid combinations of mask and register
number are UNPREDICTABLE; we choose to treat them as if the mask
values were valid.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Alex Bennée <address@hidden>


  Commit: 32f70d7659986ab73665cfa67b7d3913901cdb3b
      
https://github.com/qemu/qemu/commit/32f70d7659986ab73665cfa67b7d3913901cdb3b
  Author: Peter Maydell <address@hidden>
  Date:   2017-03-20 (Mon, 20 Mar 2017)

  Changed paths:
    M target/arm/helper.c
    M target/arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170320' 
into staging

target-arm queue:
 * fix MSR/MRS decoding for M profile CPUs

# gpg: Signature made Mon 20 Mar 2017 12:53:26 GMT
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170320:
  arm: Fix APSR writes via M profile MSR
  arm: Enforce should-be-1 bits in MRS decoding
  arm: Don't decode MRS(banked) or MSR(banked) for M profile
  arm: HVC and SMC encodings don't exist for M profile

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/00e7c07b06d0...32f70d765998

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