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[Qemu-commits] [qemu/qemu] 6ecd0b: target/arm: implement armv8 PMUSERENR


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 6ecd0b: target/arm: implement armv8 PMUSERENR (user-mode e...
Date: Tue, 14 Mar 2017 08:00:12 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 6ecd0b6ba0591ef280ed984103924d4bdca5ac32
      
https://github.com/qemu/qemu/commit/6ecd0b6ba0591ef280ed984103924d4bdca5ac32
  Author: Andrew Baumann <address@hidden>
  Date:   2017-03-14 (Tue, 14 Mar 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: implement armv8 PMUSERENR (user-mode enable bits)

In armv8, this register implements more than a single bit, with
fine-grained enables for read access to event counters, cycles
counters, and write access to the software increment. This change
implements those checks using custom access functions for the relevant
registers.

Signed-off-by: Andrew Baumann <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: move a couple of access functions to be only compiled
 ifndef CONFIG_USER_ONLY to avoid compiler warnings]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d5affb0d8677e1a8a8fe03fa25005b669e7cdc02
      
https://github.com/qemu/qemu/commit/d5affb0d8677e1a8a8fe03fa25005b669e7cdc02
  Author: Andrew Jones <address@hidden>
  Date:   2017-03-14 (Tue, 14 Mar 2017)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm/arm-powerctl: Fix psci info return values

The power state spec section 5.1.5 AFFINITY_INFO defines the
affinity info return values as

  0 ON
  1 OFF
  2 ON_PENDING

I grepped QEMU for power_state to ensure that no assumptions
of OFF=0 were being made.

Signed-off-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 486fc7a837ccbe00f78bdaafc32dbe0235a7883d
      
https://github.com/qemu/qemu/commit/486fc7a837ccbe00f78bdaafc32dbe0235a7883d
  Author: Peter Maydell <address@hidden>
  Date:   2017-03-14 (Tue, 14 Mar 2017)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170314' 
into staging

target-arm queue:
 * arm-powerctl: Fix psci info return values
 * implement armv8 PMUSERENR (user-mode enable bits)

# gpg: Signature made Tue 14 Mar 2017 11:31:11 GMT
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170314:
  target/arm/arm-powerctl: Fix psci info return values
  target/arm: implement armv8 PMUSERENR (user-mode enable bits)

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/591bce29b10a...486fc7a837cc

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