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[Qemu-commits] [qemu/qemu] 83fd96: vl/cpus: be smarter with icount and M

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 83fd96: vl/cpus: be smarter with icount and MTTCG
Date: Mon, 13 Mar 2017 04:30:13 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 83fd9629a39ee8a58f1f772a2ca3a7745a4c5743
      
https://github.com/qemu/qemu/commit/83fd9629a39ee8a58f1f772a2ca3a7745a4c5743
  Author: Alex Bennée <address@hidden>
  Date:   2017-03-09 (Thu, 09 Mar 2017)

  Changed paths:
    M cpus.c
    M vl.c

  Log Message:
  -----------
  vl/cpus: be smarter with icount and MTTCG

The sense of the test was inverted. Make it simple, if icount is
enabled then we disabled MTTCG by default. If the user tries to force
MTTCG upon us then we tell them "no".

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 72c1701f62e8d44eb24a0583a958edc280105455
      
https://github.com/qemu/qemu/commit/72c1701f62e8d44eb24a0583a958edc280105455
  Author: Alex Bennée <address@hidden>
  Date:   2017-03-09 (Thu, 09 Mar 2017)

  Changed paths:
    M target/i386/cpu.h

  Log Message:
  -----------
  target/i386/cpu.h: declare TCG_GUEST_DEFAULT_MO

This suppresses the incorrect warning when forcing MTTCG for x86
guests on x86 hosts. A future patch will still warn when
TARGET_SUPPORT_MTTCG hasn't been defined for the guest (which is still
pending for x86).

Reported-by: Paolo Bonzini <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Acked-by: Eduardo Habkost <address@hidden>


  Commit: c34c762015fec023c3ea5cf3629cbac462a80973
      
https://github.com/qemu/qemu/commit/c34c762015fec023c3ea5cf3629cbac462a80973
  Author: Alex Bennée <address@hidden>
  Date:   2017-03-09 (Thu, 09 Mar 2017)

  Changed paths:
    M cpus.c

  Log Message:
  -----------
  cpus.c: add additional error_report when !TARGET_SUPPORT_MTTCG

While we may fail the memory ordering check later that can be
confusing. So in cases where TARGET_SUPPORT_MTTCG has yet to be
defined we should say so specifically.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 5ee5993001cf32addb86a92e2ae8cb090fbc1462
      
https://github.com/qemu/qemu/commit/5ee5993001cf32addb86a92e2ae8cb090fbc1462
  Author: Alex Bennée <address@hidden>
  Date:   2017-03-09 (Thu, 09 Mar 2017)

  Changed paths:
    M hw/sparc/sun4m.c
    M hw/sparc64/sparc64.c
    M target/sparc/int64_helper.c
    M target/sparc/win_helper.c

  Log Message:
  -----------
  sparc/sparc64: grab BQL before calling cpu_check_irqs

IRQ modification is part of device emulation and should be done while
the BQL is held to prevent races when MTTCG is enabled. This adds
assertions in the hw emulation layer and wraps the calls from helpers
in the BQL.

Reported-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>


  Commit: 278f5e98c647f74e93636e8b6f9ba20a71765a44
      
https://github.com/qemu/qemu/commit/278f5e98c647f74e93636e8b6f9ba20a71765a44
  Author: Alex Bennée <address@hidden>
  Date:   2017-03-09 (Thu, 09 Mar 2017)

  Changed paths:
    M target/s390x/misc_helper.c

  Log Message:
  -----------
  s390x/misc_helper.c: wrap IO instructions in BQL

Helpers that can trigger IO events (including interrupts) need to be
protected by the BQL. I've updated all the helpers that call into an
ioinst_handle_* functions.

Reported-by: Thomas Huth <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 47e20887970c3f267a4be9afacb72dbd51e6655f
      
https://github.com/qemu/qemu/commit/47e20887970c3f267a4be9afacb72dbd51e6655f
  Author: Alex Bennée <address@hidden>
  Date:   2017-03-09 (Thu, 09 Mar 2017)

  Changed paths:
    M target/xtensa/helper.c
    M target/xtensa/op_helper.c

  Log Message:
  -----------
  target/xtensa: hold BQL for interrupt processing

Make sure we have the BQL held when processing interrupts.

Reported-by: Thomas Huth <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Acked-by: Max Filippov <address@hidden>


  Commit: d8b2239bcd8872a5c5f7534d1658fc2365caab2d
      
https://github.com/qemu/qemu/commit/d8b2239bcd8872a5c5f7534d1658fc2365caab2d
  Author: Alex Bennée <address@hidden>
  Date:   2017-03-09 (Thu, 09 Mar 2017)

  Changed paths:
    M translate-all.c

  Log Message:
  -----------
  translate-all: exit cpu_restore_state early if translating

The translation code uses cpu_ld*_code which can trigger a tlb_fill
which if it fails will erroneously attempts a fault resolution. This
never works during translation as the TB being generated hasn't been
added yet. The target should have checked retaddr before calling
cpu_restore_state but for those that have yet to be fixed we do it
here to avoid a recursive tb_lock() under MTTCG's new locking regime.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: d394698d73836d1c50545bdb32dc58d09708fcfb
      
https://github.com/qemu/qemu/commit/d394698d73836d1c50545bdb32dc58d09708fcfb
  Author: Yongbok Kim <address@hidden>
  Date:   2017-03-09 (Thu, 09 Mar 2017)

  Changed paths:
    M target/mips/op_helper.c

  Log Message:
  -----------
  target/mips: hold BQL for timer interrupts

Hold BQL when accessing timer which can cause interrupts

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>


  Commit: 10cde894b63146139f981857e4eedf756fa53dcb
      
https://github.com/qemu/qemu/commit/10cde894b63146139f981857e4eedf756fa53dcb
  Author: Paolo Bonzini <address@hidden>
  Date:   2017-03-09 (Thu, 09 Mar 2017)

  Changed paths:
    M target/i386/cpu.h
    M target/i386/seg_helper.c
    M target/i386/svm_helper.c

  Log Message:
  -----------
  target-i386: defer VMEXIT to do_interrupt

Paths through the softmmu code during code generation now need to be audited
to check for double locking of tb_lock.  In particular, VMEXIT can take tb_lock
through cpu_vmexit -> cpu_x86_update_cr4 -> tlb_flush.

To avoid this, split VMEXIT delivery in two parts, similar to what is done with
exceptions.  cpu_vmexit only records the VMEXIT exit code and information, and
cc->do_interrupt can then deliver it when it is safe to take the lock.

Reported-by: Alexander Boettcher <address@hidden>
Suggested-by: Richard Henderson <address@hidden>
Tested-by: Alexander Boettcher <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 6568da459b611845ef55526cd23afc9fa9f4647f
      
https://github.com/qemu/qemu/commit/6568da459b611845ef55526cd23afc9fa9f4647f
  Author: Alex Bennée <address@hidden>
  Date:   2017-03-09 (Thu, 09 Mar 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm/helper: make it clear the EC field is also in hex

..just like the rest of the displayed ESR register. Otherwise people
might scratch their heads if a not obviously hex number is displayed
for the EC field.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: KONRAD Frederic <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 68bf93ce9dc5c84c45a827ce2bd6eab768524e79
      
https://github.com/qemu/qemu/commit/68bf93ce9dc5c84c45a827ce2bd6eab768524e79
  Author: Alex Bennée <address@hidden>
  Date:   2017-03-09 (Thu, 09 Mar 2017)

  Changed paths:
    M hw/intc/arm_gic.c

  Log Message:
  -----------
  hw/intc/arm_gic: modernise the DPRINTF

While I was debugging the icount issues I realised a bunch of the
messages look quite similar. I've fixed this by including __func__ in
the debug print. At the same time I move the a modern if (GATE) style
printf which ensures the compiler can check for format string errors
even if the code gets optimised away in the non-DEBUG_GIC case.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 95b0eca46e03ffa0b20d29d1b3127c291accea39
      
https://github.com/qemu/qemu/commit/95b0eca46e03ffa0b20d29d1b3127c291accea39
  Author: Peter Maydell <address@hidden>
  Date:   2017-03-09 (Thu, 09 Mar 2017)

  Changed paths:
    M cpus.c
    M hw/intc/arm_gic.c
    M hw/sparc/sun4m.c
    M hw/sparc64/sparc64.c
    M target/arm/helper.c
    M target/i386/cpu.h
    M target/i386/seg_helper.c
    M target/i386/svm_helper.c
    M target/mips/op_helper.c
    M target/s390x/misc_helper.c
    M target/sparc/int64_helper.c
    M target/sparc/win_helper.c
    M target/xtensa/helper.c
    M target/xtensa/op_helper.c
    M translate-all.c
    M vl.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/stsquad/tags/pull-mttcg-fixups-090317-1' into staging

Fix-ups for MTTCG regressions for 2.9

This is the same as v3 posted a few days ago except with a few extra
Reviewed-by tags added.

# gpg: Signature made Thu 09 Mar 2017 10:45:18 GMT
# gpg:                using RSA key 0xFBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <address@hidden>"
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* remotes/stsquad/tags/pull-mttcg-fixups-090317-1:
  hw/intc/arm_gic: modernise the DPRINTF
  target/arm/helper: make it clear the EC field is also in hex
  target-i386: defer VMEXIT to do_interrupt
  target/mips: hold BQL for timer interrupts
  translate-all: exit cpu_restore_state early if translating
  target/xtensa: hold BQL for interrupt processing
  s390x/misc_helper.c: wrap IO instructions in BQL
  sparc/sparc64: grab BQL before calling cpu_check_irqs
  cpus.c: add additional error_report when !TARGET_SUPPORT_MTTCG
  target/i386/cpu.h: declare TCG_GUEST_DEFAULT_MO
  vl/cpus: be smarter with icount and MTTCG

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/dd4d2578215c...95b0eca46e03
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