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[Qemu-commits] [qemu/qemu] 54a5ba: target-arm: Implement BCM2835 hardwar
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[Qemu-commits] [qemu/qemu] 54a5ba: target-arm: Implement BCM2835 hardware RNG |
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Date: |
Tue, 28 Feb 2017 08:00:13 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 54a5ba13a9ffe7d25fc649b0fa9f8314734c8ccc
https://github.com/qemu/qemu/commit/54a5ba13a9ffe7d25fc649b0fa9f8314734c8ccc
Author: Marcin Chojnacki <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/arm/bcm2835_peripherals.c
M hw/misc/Makefile.objs
A hw/misc/bcm2835_rng.c
M include/hw/arm/bcm2835_peripherals.h
A include/hw/misc/bcm2835_rng.h
Log Message:
-----------
target-arm: Implement BCM2835 hardware RNG
Recent vanilla Raspberry Pi kernels started to make use of
the hardware random number generator in BCM2835 SoC. As a
result, those kernels wouldn't work anymore under QEMU
but rather just freeze during the boot process.
This patch implements a trivial BCM2835 compatible RNG,
and adds it as a peripheral to BCM2835 platform, which
allows to boot a vanilla Raspberry Pi kernel under Qemu.
Changes since v1:
* Prevented guest from writing [31..20] bits in rng_status
* Removed redundant minimum_version_id_old
* Added field entries for the state
* Changed realize function to reset
Signed-off-by: Marcin Chojnacki <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 373442ea3a96249991cfad3fc0e83fca5f8558d5
https://github.com/qemu/qemu/commit/373442ea3a96249991cfad3fc0e83fca5f8558d5
Author: Peter Maydell <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/misc/bcm2835_rng.c
Log Message:
-----------
bcm2835_rng: Use qcrypto_random_bytes() rather than rand()
Switch to using qcrypto_random_bytes() rather than rand() as
our source of randomness for the BCM2835 RNG.
If qcrypto_random_bytes() fails, we don't want to return the guest a
non-random value in case they're really using it for cryptographic
purposes, so the best we can do is a fatal error. This shouldn't
happen unless something's broken, though.
In theory we could implement this device's full FIFO and interrupt
semantics and then just stop filling the FIFO. That's a lot of work,
though, and doesn't really give a very nice diagnostic to the user
since the guest will just seem to hang.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Daniel P. Berrange <address@hidden>
Commit: 8b20aefac4ee8874bb9c8826e4b30e1dc8cd7511
https://github.com/qemu/qemu/commit/8b20aefac4ee8874bb9c8826e4b30e1dc8cd7511
Author: Prasad J Pandit <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/sd/sdhci.c
Log Message:
-----------
sd: sdhci: mask transfer mode register value
In SDHCI protocol, the transfer mode register is defined
to be of 6 bits. Mask its value with '0x0037' so that an
invalid value could not be assigned.
Signed-off-by: Prasad J Pandit <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 6e86d90352adf6cb08295255220295cf23c4286e
https://github.com/qemu/qemu/commit/6e86d90352adf6cb08295255220295cf23c4286e
Author: Prasad J Pandit <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/sd/sdhci.c
Log Message:
-----------
sd: sdhci: check transfer mode register in multi block transfer
In the SDHCI protocol, the transfer mode register value
is used during multi block transfer to check if block count
register is enabled and should be updated. Transfer mode
register could be set such that, block count register would
not be updated, thus leading to an infinite loop. Add check
to avoid it.
Reported-by: Wjjzhang <address@hidden>
Reported-by: Jiang Xin <address@hidden>
Signed-off-by: Prasad J Pandit <address@hidden>
Message-id: address@hidden
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 45ba9f761bde329cc5ef276b571bd4f3c41a044e
https://github.com/qemu/qemu/commit/45ba9f761bde329cc5ef276b571bd4f3c41a044e
Author: Prasad J Pandit <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/sd/sdhci.c
Log Message:
-----------
sd: sdhci: conditionally invoke multi block transfer
In sdhci_write invoke multi block transfer if it is enabled
in the transfer mode register 's->trnmod'.
Signed-off-by: Prasad J Pandit <address@hidden>
Message-id: address@hidden
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 241999bf4c0dd75d300ceee46f7ad28b3a39fe97
https://github.com/qemu/qemu/commit/241999bf4c0dd75d300ceee46f7ad28b3a39fe97
Author: Prasad J Pandit <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/sd/sdhci.c
Log Message:
-----------
sd: sdhci: Remove block count enable check in single block transfers
In SDHCI protocol, the 'Block count enable' bit of the Transfer
Mode register is relevant only in multi block transfers. We need
not check it in single block transfers.
Signed-off-by: Prasad J Pandit <address@hidden>
Message-id: address@hidden
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: dbb74759fae6f521709e16e19cbb7d6fb2307700
https://github.com/qemu/qemu/commit/dbb74759fae6f521709e16e19cbb7d6fb2307700
Author: Igor Mammedov <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: fix cpu object reference leak
object_new(FOO) returns an object with ref_cnt == 1
and following
object_property_set_bool(cpuobj, true, "realized", NULL)
set parent of cpuobj to '/machine/unattached' which makes
ref_cnt == 2.
Since machvirt_init() doesn't take ownership of cpuobj
returned by object_new() it should explicitly drop
reference to cpuobj when dangling pointer is about to
go out of scope like it's done pc_new_cpu() to avoid
object leak.
Signed-off-by: Igor Mammedov <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: a4f5c5b72380deeccd53a6890ea3782f10ca8054
https://github.com/qemu/qemu/commit/a4f5c5b72380deeccd53a6890ea3782f10ca8054
Author: Nick Reilly <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
Add missing fp_access_check() to aarch64 crypto instructions
The aarch64 crypto instructions for AES and SHA are missing the
check for if the FPU is enabled.
Signed-off-by: Nick Reilly <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 44d7ce0ef39cb45e13d384574d79799eb3d39834
https://github.com/qemu/qemu/commit/44d7ce0ef39cb45e13d384574d79799eb3d39834
Author: Peter Maydell <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M cputlb.c
Log Message:
-----------
cputlb: Don't assume do_unassigned_access() never returns
In get_page_addr_code(), if the guest PC doesn't correspond to RAM
then we currently run the CPU's do_unassigned_access() hook if it has
one, and otherwise we give up and exit QEMU with a more-or-less
useful message. This code assumes that the do_unassigned_access hook
will never return, because if it does then we'll plough on attempting
to use a non-RAM TLB entry to get a RAM address and will abort() in
qemu_ram_addr_from_host_nofail(). Unfortunately some CPU
implementations of this hook do return: Microblaze, SPARC and the ARM
v7M.
Change the code to call report_bad_exec() if the hook returns, as
well as if it didn't have one. This means we can tidy it up to use
the cpu_unassigned_access() function which wraps the "get the CPU
class and call the hook if it has one" work, since we aren't trying
to distinguish "no hook" from "hook existed and returned" any more.
This brings the handling of this hook into line with the handling
used for data accesses, where "hook returned" is treated the
same as "no hook existed" and gets you the default behaviour.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: ccc11b027923d738e5196ef355c48aac866802a9
https://github.com/qemu/qemu/commit/ccc11b027923d738e5196ef355c48aac866802a9
Author: Eric Auger <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
hw/arm/virt: Add a user option to disallow ITS instantiation
In 2.9 ITS will block save/restore and migration use cases. As such,
let's introduce a user option that allows to turn its instantiation
off, along with GICv3. With the "its" option turned false, migration
will be possible, obviously at the expense of MSI support (with GICv3).
Signed-off-by: Eric Auger <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: c98c9eba888c9ae450d41d92b1e6abbb66832e4c
https://github.com/qemu/qemu/commit/c98c9eba888c9ae450d41d92b1e6abbb66832e4c
Author: Kurban Mallachiev <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/timer/imx_gpt.c
Log Message:
-----------
ARM i.MX timers: fix reset handling
The i.MX timer device can be reset by writing to the SWR bit
of the CR register. This has to behave differently from hard
(power-on) reset because it does not reset all of the bits
in the CR register.
We were incorrectly implementing soft reset and hard reset
the same way, and in addition had a logic error which meant
that we were clearing the bits that soft-reset is supposed
to preserve and not touching the bits that soft-reset clears.
This was not correct behaviour for either kind of reset.
Separate out the soft reset and hard reset code paths, and
correct the handling of reset of the CR register so that it
is correct in both cases.
Signed-off-by: Kurban Mallachiev <address@hidden>
[PMM: rephrased commit message, spacing on operators;
use bool rather than int for is_soft_reset]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: f797c07507b4af66ae6817390001dbc1036591ef
https://github.com/qemu/qemu/commit/f797c07507b4af66ae6817390001dbc1036591ef
Author: Peter Maydell <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
Log Message:
-----------
armv7m: Rename nvic_state to NVICState
Rename the nvic_state struct to NVICState, to match
our naming conventions.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Commit: 1004102a772744fbb31d8001ade0090be8b02a93
https://github.com/qemu/qemu/commit/1004102a772744fbb31d8001ade0090be8b02a93
Author: Peter Maydell <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
Log Message:
-----------
armv7m: Implement reading and writing of PRIGROUP
Add a state field for the v7M PRIGROUP register and implent
reading and writing it. The current NVIC doesn't honour
the values written, but the new version will.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Commit: da6d674e509f0939b2960eef2ce1c3443e9736df
https://github.com/qemu/qemu/commit/da6d674e509f0939b2960eef2ce1c3443e9736df
Author: Michael Davidsaver <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M hw/intc/trace-events
Log Message:
-----------
armv7m: Rewrite NVIC to not use any GIC code
Despite some superficial similarities of register layout, the
M-profile NVIC is really very different from the A-profile GIC.
Our current attempt to reuse the GIC code means that we have
significant bugs in our NVIC.
Implement the NVIC as an entirely separate device, to give
us somewhere we can get the behaviour correct.
This initial commit does not attempt to implement exception
priority escalation, since the GIC-based code didn't either.
It does fix a few bugs in passing:
* ICSR.RETTOBASE polarity was wrong and didn't account for
internal exceptions
* ICSR.VECTPENDING was 16 too high if the pending exception
was for an external interrupt
* UsageFault, BusFault and MemFault were not disabled on reset
as they are supposed to be
Signed-off-by: Michael Davidsaver <address@hidden>
[PMM: reworked, various bugs and stylistic cleanups]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Commit: 7ecdaa4a9635f1ded0dfa9218c25273b6d4dcd44
https://github.com/qemu/qemu/commit/7ecdaa4a9635f1ded0dfa9218c25273b6d4dcd44
Author: Peter Maydell <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.c
M target/arm/cpu.h
Log Message:
-----------
armv7m: Fix condition check for taking exceptions
The M profile condition for when we can take a pending exception or
interrupt is not the same as that for A/R profile. The code
originally copied from the A/R profile version of the
cpu_exec_interrupt function only worked by chance for the
very simple case of exceptions being masked by PRIMASK.
Replace it with a call to a function in the NVIC code that
correctly compares the priority of the pending exception
against the current execution priority of the CPU.
[Michael Davidsaver's patchset had a patch to do something
similar but the implementation ended up being a rewrite.]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Commit: 7c14b3ac072c48614ca888e101d17ee64312c89f
https://github.com/qemu/qemu/commit/7c14b3ac072c48614ca888e101d17ee64312c89f
Author: Michael Davidsaver <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/intc/arm_gic.c
M hw/intc/arm_gic_common.c
M hw/intc/gic_internal.h
Log Message:
-----------
arm: gic: Remove references to NVIC
Now that the NVIC is its own separate implementation, we can
clean up the GIC code by removing REV_NVIC and conditionals
which use it.
Signed-off-by: Michael Davidsaver <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Commit: a73c98e159d18155445d29b6044be6ad49fd802f
https://github.com/qemu/qemu/commit/a73c98e159d18155445d29b6044be6ad49fd802f
Author: Michael Davidsaver <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/helper.c
Log Message:
-----------
armv7m: Escalate exceptions to HardFault if necessary
The v7M exception architecture requires that if a synchronous
exception cannot be taken immediately (because it is disabled
or at too low a priority) then it should be escalated to
HardFault (and the HardFault exception is then taken).
Implement this escalation logic.
Signed-off-by: Michael Davidsaver <address@hidden>
[PMM: extracted from another patch]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Commit: a5d8235545e98c1ce02560d5f4f57552d937efe9
https://github.com/qemu/qemu/commit/a5d8235545e98c1ce02560d5f4f57552d937efe9
Author: Peter Maydell <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value
Having armv7m_nvic_acknowledge_irq() return the new value of
env->v7m.exception and its one caller assign the return value
back to env->v7m.exception is pointless. Just make the return
type void instead.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Commit: a25dc805e2e63a55029e787a52335e12dabf07dc
https://github.com/qemu/qemu/commit/a25dc805e2e63a55029e787a52335e12dabf07dc
Author: Michael Davidsaver <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
armv7m: Simpler and faster exception start
All the places in armv7m_cpu_do_interrupt() which pend an
exception in the NVIC are doing so for synchronous
exceptions. We know that we will always take some
exception in this case, so we can just acknowledge it
immediately, rather than returning and then immediately
being called again because the NVIC has raised its outbound
IRQ line.
Signed-off-by: Michael Davidsaver <address@hidden>
[PMM: tweaked commit message; added DEBUG to the set of
exceptions we handle immediately, since it is synchronous
when it results from the BKPT instruction]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Commit: 14790f730a9b7da026f5562505d1004f67abebf5
https://github.com/qemu/qemu/commit/14790f730a9b7da026f5562505d1004f67abebf5
Author: Michael Davidsaver <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
Log Message:
-----------
armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE
The VECTCLRACTIVE and VECTRESET bits in the AIRCR are both
documented as UNPREDICTABLE if you write a 1 to them when
the processor is not halted in Debug state (ie stopped
and under the control of an external JTAG debugger).
Since we don't implement Debug state or emulated JTAG
these bits are always UNPREDICTABLE for us. Instead of
logging them as unimplemented we can simply log writes
as guest errors and ignore them.
Signed-off-by: Michael Davidsaver <address@hidden>
[PMM: change extracted from another patch; commit message
constructed from scratch]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Commit: 39ae2474e337247e5930e8be783b689adc9f6215
https://github.com/qemu/qemu/commit/39ae2474e337247e5930e8be783b689adc9f6215
Author: Peter Maydell <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
armv7m: Extract "exception taken" code into functions
Extract the code from the tail end of arm_v7m_do_interrupt() which
enters the exception handler into a pair of utility functions
v7m_exception_taken() and v7m_push_stack(), which correspond roughly
to the pseudocode PushStack() and ExceptionTaken().
This also requires us to move the arm_v7m_load_vector() utility
routine up so we can call it.
Handling illegal exception returns has some cases where we want to
take a UsageFault either on an existing stack frame or with a new
stack frame but with a specific LR value, so we want to be able to
call these without having to go via arm_v7m_cpu_do_interrupt().
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Commit: aa488fe3bb5460c6675800ccd80f6dccbbd70159
https://github.com/qemu/qemu/commit/aa488fe3bb5460c6675800ccd80f6dccbbd70159
Author: Peter Maydell <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
armv7m: Check exception return consistency
Implement the exception return consistency checks
described in the v7M pseudocode ExceptionReturn().
Inspired by a patch from Michael Davidsaver's series, but
this is a reimplementation from scratch based on the
ARM ARM pseudocode.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Commit: e13886e3a790b52f0b2e93cb5e84fdc2ada5471a
https://github.com/qemu/qemu/commit/e13886e3a790b52f0b2e93cb5e84fdc2ada5471a
Author: Peter Maydell <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M linux-user/main.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate.c
Log Message:
-----------
armv7m: Raise correct kind of UsageFault for attempts to execute ARM code
M profile doesn't implement ARM, and the architecturally required
behaviour for attempts to execute with the Thumb bit clear is to
generate a UsageFault with the CFSR INVSTATE bit set. We were
incorrectly implementing this as generating an UNDEFINSTR UsageFault;
fix this.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Commit: 5db53e353dfe08492aca793b4748d8182f9780b3
https://github.com/qemu/qemu/commit/5db53e353dfe08492aca793b4748d8182f9780b3
Author: Peter Maydell <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
Log Message:
-----------
armv7m: Allow SHCSR writes to change pending and active bits
Implement the NVIC SHCSR write behaviour which allows pending and
active status of some exceptions to be changed.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Commit: 43ddc182e2858a4f2354ba1095dc8a3b09d828ca
https://github.com/qemu/qemu/commit/43ddc182e2858a4f2354ba1095dc8a3b09d828ca
Author: Clement Deschamps <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/sd/Makefile.objs
A hw/sd/bcm2835_sdhost.c
A include/hw/sd/bcm2835_sdhost.h
Log Message:
-----------
bcm2835_sdhost: add bcm2835 sdhost controller
This adds the BCM2835 SDHost controller from Arasan.
Signed-off-by: Clement Deschamps <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 1e0228fd20aa46ac1f02cffee946cdd4ffaf8b96
https://github.com/qemu/qemu/commit/1e0228fd20aa46ac1f02cffee946cdd4ffaf8b96
Author: Krzysztof Kozlowski <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/arm/exynos4210.c
M hw/misc/Makefile.objs
A hw/misc/exynos4210_clk.c
Log Message:
-----------
hw/arm/exynos: Fix Linux kernel division by zero for PLLs
Without any clock controller, the Linux kernel was hitting division by
zero during boot or with clk_summary:
[ 0.000000] [<c031054c>] (unwind_backtrace) from [<c030ba6c>]
(show_stack+0x10/0x14)
[ 0.000000] [<c030ba6c>] (show_stack) from [<c05b2660>]
(dump_stack+0x88/0x9c)
[ 0.000000] [<c05b2660>] (dump_stack) from [<c05b11a4>] (Ldiv0+0x8/0x10)
[ 0.000000] [<c05b11a4>] (Ldiv0) from [<c06ad1e0>]
(samsung_pll45xx_recalc_rate+0x58/0x74)
[ 0.000000] [<c06ad1e0>] (samsung_pll45xx_recalc_rate) from [<c0692ec0>]
(clk_register+0x39c/0x63c)
[ 0.000000] [<c0692ec0>] (clk_register) from [<c125d360>]
(samsung_clk_register_pll+0x2e0/0x3d4)
[ 0.000000] [<c125d360>] (samsung_clk_register_pll) from [<c125d7e8>]
(exynos4_clk_init+0x1b0/0x5e4)
[ 0.000000] [<c125d7e8>] (exynos4_clk_init) from [<c12335f4>]
(of_clk_init+0x17c/0x210)
[ 0.000000] [<c12335f4>] (of_clk_init) from [<c1204700>]
(time_init+0x24/0x2c)
[ 0.000000] [<c1204700>] (time_init) from [<c1200b2c>]
(start_kernel+0x24c/0x38c)
[ 0.000000] [<c1200b2c>] (start_kernel) from [<4020807c>] (0x4020807c)
Provide stub for clock controller returning reset values for PLLs.
Signed-off-by: Krzysztof Kozlowski <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: f3a6339a5bbc160d327299c67bb68c6d07fa4a61
https://github.com/qemu/qemu/commit/f3a6339a5bbc160d327299c67bb68c6d07fa4a61
Author: Krzysztof Kozlowski <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M hw/arm/exynos4210.c
Log Message:
-----------
hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID
The Exynos4210 has cluster ID 0x9 in its MPIDR register (raw value
0x8000090x). If this cluster ID is not provided, then Linux kernel
cannot map DeviceTree nodes to MPIDR values resulting in kernel
warning and lack of any secondary CPUs:
DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map
...
smp: Bringing up secondary CPUs ...
smp: Brought up 1 node, 1 CPU
SMP: Total of 1 processors activated (24.00 BogoMIPS).
Provide a cluster ID so Linux will see proper MPIDR and will try to
bring the secondary CPU online.
Signed-off-by: Krzysztof Kozlowski <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 1bbe5dc66b770d7bedd1d51d7935da948a510dd6
https://github.com/qemu/qemu/commit/1bbe5dc66b770d7bedd1d51d7935da948a510dd6
Author: Peter Maydell <address@hidden>
Date: 2017-02-28 (Tue, 28 Feb 2017)
Changed paths:
M cputlb.c
M hw/arm/bcm2835_peripherals.c
M hw/arm/exynos4210.c
M hw/arm/virt.c
M hw/intc/arm_gic.c
M hw/intc/arm_gic_common.c
M hw/intc/armv7m_nvic.c
M hw/intc/gic_internal.h
M hw/intc/trace-events
M hw/misc/Makefile.objs
A hw/misc/bcm2835_rng.c
A hw/misc/exynos4210_clk.c
M hw/sd/Makefile.objs
A hw/sd/bcm2835_sdhost.c
M hw/sd/sdhci.c
M hw/timer/imx_gpt.c
M include/hw/arm/bcm2835_peripherals.h
M include/hw/arm/virt.h
A include/hw/misc/bcm2835_rng.h
A include/hw/sd/bcm2835_sdhost.h
M linux-user/main.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate-a64.c
M target/arm/translate.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170228'
into staging
target-arm queue:
* raspi2: implement RNG module
* raspi2: implement new SD card controller (but don't wire it up)
* sdhci: bugfixes for block transfers
* virt: fix cpu object reference leak
* Add missing fp_access_check() to aarch64 crypto instructions
* cputlb: Don't assume do_unassigned_access() never returns
* virt: Add a user option to disallow ITS instantiation
* i.MX timers: fix reset handling
* ARMv7M NVIC: rewrite to fix broken priority handling and masking
* exynos: Fix proper mapping of CPUs by providing real cluster ID
* exynos: Fix Linux kernel division by zero for PLLs
# gpg: Signature made Tue 28 Feb 2017 12:40:51 GMT
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20170228: (27 commits)
hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID
hw/arm/exynos: Fix Linux kernel division by zero for PLLs
bcm2835_sdhost: add bcm2835 sdhost controller
armv7m: Allow SHCSR writes to change pending and active bits
armv7m: Raise correct kind of UsageFault for attempts to execute ARM code
armv7m: Check exception return consistency
armv7m: Extract "exception taken" code into functions
armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE
armv7m: Simpler and faster exception start
armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value
armv7m: Escalate exceptions to HardFault if necessary
arm: gic: Remove references to NVIC
armv7m: Fix condition check for taking exceptions
armv7m: Rewrite NVIC to not use any GIC code
armv7m: Implement reading and writing of PRIGROUP
armv7m: Rename nvic_state to NVICState
ARM i.MX timers: fix reset handling
hw/arm/virt: Add a user option to disallow ITS instantiation
cputlb: Don't assume do_unassigned_access() never returns
Add missing fp_access_check() to aarch64 crypto instructions
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/c8c0a1a784cd...1bbe5dc66b77
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