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[Qemu-commits] [qemu/qemu] f84461: spapr: cpu core: separate child threa
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[Qemu-commits] [qemu/qemu] f84461: spapr: cpu core: separate child threads destructio... |
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Date: |
Fri, 24 Feb 2017 05:00:12 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: f844616bf6ff623fd6691b022cb5227faa269675
https://github.com/qemu/qemu/commit/f844616bf6ff623fd6691b022cb5227faa269675
Author: Igor Mammedov <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/ppc/spapr_cpu_core.c
Log Message:
-----------
spapr: cpu core: separate child threads destruction from machine state
operations
Split off destroying VCPU threads from drc callback
spapr_core_release() into new spapr_cpu_core_unrealizefn()
which takes care of internal cpu core state cleanup (i.e.
VCPU threads) and is called when object_unparent(core)
is called.
That leaves spapr_core_release() only with board mgmt
code, which will be moved to board related file in
follow up patch along with the rest on hotplug callbacks.
Signed-off-by: Igor Mammedov <address@hidden>
Reviewed-by: Bharata B Rao <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ff9006ddbfd194a946ce3ee46b175919beeaf160
https://github.com/qemu/qemu/commit/ff9006ddbfd194a946ce3ee46b175919beeaf160
Author: Igor Mammedov <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
M include/hw/ppc/spapr_cpu_core.h
Log Message:
-----------
spapr: move spapr_core_[foo]plug() callbacks close to machine code in spapr.c
spapr_core_pre_plug/spapr_core_plug/spapr_core_unplug() are managing
wiring CPU core into spapr machine state and not internal CPU core state.
So move them from spapr_cpu_core.c to spapr.c where other similar
(spapr_memory_[foo]plug()) callbacks are located, which also matches
x86 target practice.
Signed-off-by: Igor Mammedov <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 115debf26cdca3154157976b446b209a94665526
https://github.com/qemu/qemu/commit/115debf26cdca3154157976b446b209a94665526
Author: Igor Mammedov <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: make cpu core unplug follow expected hotunplug call flow
spapr_core_unplug() were essentially spapr_core_unplug_request()
handler that requested CPU removal and registered callback
which did actual cpu core removali but it was called from
spapr_machine_device_unplug() which is intended for actual object
removal. Commit (cf632463 spapr: Memory hot-unplug support)
sort of fixed it introducing spapr_machine_device_unplug_request()
and calling spapr_core_unplug() but it hasn't renamed callback and
by mistake calls it from spapr_machine_device_unplug().
However spapr_machine_device_unplug() isn't ever called for
cpu core since spapr_core_release() doesn't follow expected
hotunplug call flow which is:
1: device_del() ->
hotplug_handler_unplug_request() ->
set destroy_cb()
2: destroy_cb() ->
hotplug_handler_unplug() ->
object_unparent // actual device removal
Fix it by renaming spapr_core_unplug() to spapr_core_unplug_request()
which is called from spapr_machine_device_unplug_request() and
making spapr_core_release() call hotplug_handler_unplug() which
will call spapr_machine_device_unplug() -> spapr_core_unplug()
to remove cpu core.
Signed-off-by: Igor Mammedov <address@hidden>
Reveiwed-by: Bharata B Rao <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: be07ad58427a575cdd1f4ab9833ef46b21c6be3e
https://github.com/qemu/qemu/commit/be07ad58427a575cdd1f4ab9833ef46b21c6be3e
Author: Jose Ricardo Ziviani <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/internal.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
ppc: implement xsrqpi[x] instruction
xsrqpi[x]: VSX Scalar Round to Quad-Precision Integer
[with Inexact].
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 917950d7f54551db9c85c4d06cf559bd19da10a9
https://github.com/qemu/qemu/commit/917950d7f54551db9c85c4d06cf559bd19da10a9
Author: Jose Ricardo Ziviani <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
ppc: implement xsrqpxp instruction
xsrqpxp: VSX Scalar Round Quad-Precision to Double-Extended Precision.
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a4a68476def684f2f424a9ae1daed3de469da7cb
https://github.com/qemu/qemu/commit/a4a68476def684f2f424a9ae1daed3de469da7cb
Author: Jose Ricardo Ziviani <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
ppc: implement xssqrtqp instruction
xssqrtqp: VSX Scalar Square Root Quad-Precision.
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f6b99afdc33e94cd09ee68979f2db409e7f56517
https://github.com/qemu/qemu/commit/f6b99afdc33e94cd09ee68979f2db409e7f56517
Author: Jose Ricardo Ziviani <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
ppc: implement xssubqp instruction
xssubqp: VSX Scalar Subtract Quad-Precision.
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 802fc7abd01b641032123906dad8578fb9ea017d
https://github.com/qemu/qemu/commit/802fc7abd01b641032123906dad8578fb9ea017d
Author: Thomas Huth <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
hw/ppc/pnv: Remove superfluous "qemu" prefix from error strings
error_report() already puts a prefix with the program name in front
of the error strings, so the "qemu:" prefix is not necessary here
anymore.
Reported-by: Markus Armbruster <address@hidden>
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2770deede0ad4a7f1e9e41a75b96e4eeb9a8305d
https://github.com/qemu/qemu/commit/2770deede0ad4a7f1e9e41a75b96e4eeb9a8305d
Author: Bharata B Rao <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xsmaxcdp and xsmincdp instructions
xsmaxcdp: VSX Scalar Maximum Type-C Double-Precision
xsmincdp: VSX Scalar Minimum Type-C Double-Precision
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d4ccd87e6894569f5535eed94e45bf1bbba0478c
https://github.com/qemu/qemu/commit/d4ccd87e6894569f5535eed94e45bf1bbba0478c
Author: Bharata B Rao <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xsmaxjdp and xsminjdp instructions
xsmaxjdp: VSX Scalar Maximum Type-J Double-Precision
xsminjdp: VSX Scalar Minimum Type-J Double-Precision
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: fe93e3e6ec1b1bf4a4c9d4bf55f8776318da6847
https://github.com/qemu/qemu/commit/fe93e3e6ec1b1bf4a4c9d4bf55f8776318da6847
Author: Sam Bobroff <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/ppc/spapr_ovec.c
Log Message:
-----------
spapr: fix off-by-one error in spapr_ovec_populate_dt()
The last byte of the option vector was missing due to an off-by-one
error. Without this fix, client architecture support negotiation will
fail because the last byte of option vector 5, which contains the MMU
support, will be missed.
Signed-off-by: Sam Bobroff <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Michael Roth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a68a6146738c524ce5ed0d379501b2797d689c0d
https://github.com/qemu/qemu/commit/a68a6146738c524ce5ed0d379501b2797d689c0d
Author: Balamuruhan S <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/internal.h
M target/ppc/translate.c
Log Message:
-----------
target-ppc: implement load atomic instruction
lwat: Load Word Atomic
ldat: Load Doubleword Atomic
The instruction includes as function code (5 bits) which gives a detail
on the operation to be performed. The patch implements five such
functions.
Signed-off-by: Balamuruhan S <address@hidden>
Signed-off-by: Harish S <address@hidden>
Signed-off-by: Athira Rajeev <address@hidden>
[ combine both lwat/ldat implementation using macro ]
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a34011881c433c759d0fc964614a7d26b0824b24
https://github.com/qemu/qemu/commit/a34011881c433c759d0fc964614a7d26b0824b24
Author: Balamuruhan S <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target-ppc: implement store atomic instruction
stwat: Store Word Atomic
stdat: Store Doubleword Atomic
The instruction includes as function code (5 bits) which gives a detail
on the operation to be performed. The patch implements five such
functions.
Signed-off-by: Balamuruhan S <address@hidden>
Signed-off-by: Harish S <address@hidden>
Signed-off-by: Athira Rajeev <address@hidden>
[ implement stdat, use macro and combine both implementation ]
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 80b8c1ee0571a96e13d0fc212a8eec01c3dca607
https://github.com/qemu/qemu/commit/80b8c1ee0571a96e13d0fc212a8eec01c3dca607
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target-ppc: generate exception for copy/paste
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a63f1dfc6213c765b62e93b720229d522cd156f4
https://github.com/qemu/qemu/commit/a63f1dfc6213c765b62e93b720229d522cd156f4
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/helper.h
M target/ppc/mmu-hash64.c
M target/ppc/translate.c
Log Message:
-----------
target-ppc: add slbieg instruction
slbieg: SLB Invalidate Entry Global
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 62d897ca8b6ede0acee6647d2db5d5333b71286d
https://github.com/qemu/qemu/commit/62d897ca8b6ede0acee6647d2db5d5333b71286d
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target-ppc: add slbsync implementation
slbsync: SLB Synchoronize
The instruction provides an ordering function for the effects of all
slbieg instructions executed by the thread executing the slbsync
instruction.
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c09cec683b713d585b74825a911ee45338cb7778
https://github.com/qemu/qemu/commit/c09cec683b713d585b74825a911ee45338cb7778
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target-ppc: add wait instruction
Use the available wait instruction implementation.
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2635531f2006bfb0f943ad25b41e176709b79b37
https://github.com/qemu/qemu/commit/2635531f2006bfb0f943ad25b41e176709b79b37
Author: Sam Bobroff <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M linux-user/main.c
Log Message:
-----------
target-ppc, tcg: fix usermode segfault with pthread_create()
Programs run under qemu-ppc64 on an x86_64 host currently segfault
if they use pthread_create() due to the adjustment made to the NIP in
commit bd6fefe71cec5a0c7d2be4ac96307f25db56abf9.
This patch changes cpu_loop() to set the NIP back to the
pre-incremented value before calling do_syscall(), which causes the
correct address to be used for the new thread and corrects the fault.
Signed-off-by: Sam Bobroff <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5283c27fc57757eb6b5bd286749711fbc4fb7a1b
https://github.com/qemu/qemu/commit/5283c27fc57757eb6b5bd286749711fbc4fb7a1b
Author: Laurent Vivier <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/ppc/mac_newworld.c
M hw/ppc/trace-events
Log Message:
-----------
mac99: replace debug printf with trace points
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f4af7d44381b5df2fbd0b184b504e72b4c0d9c22
https://github.com/qemu/qemu/commit/f4af7d44381b5df2fbd0b184b504e72b4c0d9c22
Author: Laurent Vivier <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/ppc/ppc4xx_pci.c
M hw/ppc/trace-events
Log Message:
-----------
ppc4xx: replace debug printf with trace points
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5b929608b94fc3ee4104553f961b6b1fae3d7b88
https://github.com/qemu/qemu/commit/5b929608b94fc3ee4104553f961b6b1fae3d7b88
Author: Laurent Vivier <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/ppc/spapr_ovec.c
M hw/ppc/trace-events
Log Message:
-----------
spapr: replace debug printf with trace points
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 9ee6f678f473007e252934d6acd09c24490d9d42
https://github.com/qemu/qemu/commit/9ee6f678f473007e252934d6acd09c24490d9d42
Author: Bharata B Rao <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: Add round-to-odd rounding mode
Power ISA 3.0 introduces a few quadruple precision floating point
instructions that support round-to-odd rounding mode. The
round-to-odd mode is explained as under:
Let Z be the intermediate arithmetic result or the operand of a convert
operation. If Z can be represented exactly in the target format, the
result is Z. Otherwise the result is either Z1 or Z2 whichever is odd.
Here Z1 and Z2 are the next larger and smaller numbers representable
in the target format respectively.
Signed-off-by: Bharata B Rao <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2e6d85683576c970c714c1cc071dca742835b9d4
https://github.com/qemu/qemu/commit/2e6d85683576c970c714c1cc071dca742835b9d4
Author: Bharata B Rao <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: Add float128_to_uint64_round_to_zero()
Implement float128_to_uint64() and use that to implement
float128_to_uint64_round_to_zero()
This is required by xscvqpudz instruction of PowerPC ISA 3.0.
Signed-off-by: Bharata B Rao <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: fd425037d25cecaaffdb3831697e0adc10ca2ba3
https://github.com/qemu/qemu/commit/fd425037d25cecaaffdb3831697e0adc10ca2ba3
Author: Bharata B Rao <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: Add float128_to_uint32_round_to_zero()
float128_to_uint32_round_to_zero() is needed by xscvqpuwz instruction
of PowerPC ISA 3.0.
Signed-off-by: Bharata B Rao <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a8d411abac9347aadeac87687b8a3c9895ea0fd7
https://github.com/qemu/qemu/commit/a8d411abac9347aadeac87687b8a3c9895ea0fd7
Author: Bharata B Rao <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Implement round to odd variants of quad FP instructions
xsaddqpo: VSX Scalar Add Quad-Precision using round to Odd
xsmulqo: VSX Scalar Multiply Quad-Precision using round to Odd
xsdivqpo: VSX Scalar Divide Quad-Precision using round to Odd
xscvqpdpo: VSX Scalar round & Convert Quad-Precision format to
Double-Precision format using round to Odd
xssqrtqpo: VSX Scalar Square Root Quad-Precision using round to Odd
xssubqpo: VSX Scalar Subtract Quad-Precision using round to Odd
In addition, fix the invalid bitmask in the instruction encoding
of xssqrtqp[o].
Signed-off-by: Bharata B Rao <address@hidden>
CC: Jose Ricardo Ziviani <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e0aee726bf166b36ddcbd31511bd96d7fa136ae0
https://github.com/qemu/qemu/commit/e0aee726bf166b36ddcbd31511bd96d7fa136ae0
Author: Bharata B Rao <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xscvqpudz and xscvqpuwz instructions
xscvqpudz: VSX Scalar truncate & Convert Quad-Precision format to
Unsigned Doubleword format
xscvqpuwz: VSX Scalar truncate & Convert Quad-Precision format to
Unsigned Word format
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 7659ca1a3e22aa298022b1ecb21bf3650a01e814
https://github.com/qemu/qemu/commit/7659ca1a3e22aa298022b1ecb21bf3650a01e814
Author: Suraj Jitindar Singh <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: Fix LPCR DPFD mask define
The DPFD field in the LPCR is 3 bits wide. This has always been defined
as 0x3 << shift which indicates a 2 bit field, which is incorrect.
Correct this.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 86cf1e9fe852e5c322968c2c708a7efa8b7be5d9
https://github.com/qemu/qemu/commit/86cf1e9fe852e5c322968c2c708a7efa8b7be5d9
Author: Suraj Jitindar Singh <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/mmu_helper.c
M target/ppc/translate_init.c
Log Message:
-----------
target/ppc/POWER9: Add ISAv3.00 MMU definition
POWER9 processors implement the mmu as defined in version 3.00 of the ISA.
Add a definition for this mmu model and set the POWER9 cpu model to use
this mmu model.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 18aa49ecf40b002dcaad9ea5491923358f512e72
https://github.com/qemu/qemu/commit/18aa49ecf40b002dcaad9ea5491923358f512e72
Author: Suraj Jitindar Singh <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/cpu.h
M target/ppc/mmu-hash64.c
M target/ppc/translate_init.c
Log Message:
-----------
target/ppc/POWER9: Adapt LPCR handling for POWER9
The logical partitioning control register controls a threads operation
based on the partition it is currently executing. Add new definitions and
update the mask used when writing to the LPCR based on the POWER9 spec.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 506590836144af7d0de3fc4c691bb5ed49d41645
https://github.com/qemu/qemu/commit/506590836144af7d0de3fc4c691bb5ed49d41645
Author: Suraj Jitindar Singh <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/mmu-hash64.c
Log Message:
-----------
target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv
The vpm0 bit was removed from the LPCR in POWER9, this bit controlled
whether ISI and DSI interrupts were directed to the hypervisor or the
partition. These interrupts now go to the hypervisor irrespective, thus
it is no longer necessary to check the vmp0 bit in the LPCR.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: fb38ebfbfe16ed776a895869d2a018c9d417b754
https://github.com/qemu/qemu/commit/fb38ebfbfe16ed776a895869d2a018c9d417b754
Author: Thomas Huth <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/pci-host/prep.c
Log Message:
-----------
hw/pci-host/prep: Do not use hw_error() in realize function
hw_error() is for CPU related errors only (it prints out a
register dump and calls abort()), so we should not use it
if we just failed to load the bios image. Apart from that,
realize() functions should not exit directly but always set
the errp with error_setg() in case of errors instead.
Additionally, move some code around and delete the bios memory
subregion again in case of such an error, so that we leave a
clean state when returning to the caller.
Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: Hervé Poussineau <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 38690a1ca7cd4771800b1581329f09fafad3f2d6
https://github.com/qemu/qemu/commit/38690a1ca7cd4771800b1581329f09fafad3f2d6
Author: Igor Mammedov <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/i386/pc.c
M include/hw/boards.h
M include/hw/i386/pc.h
Log Message:
-----------
machine: move possible_cpus to MachineState
so that it would be possible to reuse it with
spapr/virt-aarch64 targets.
Signed-off-by: Igor Mammedov <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c96a1c0ba6b88fb47ca734013ae9b9248f78fbb4
https://github.com/qemu/qemu/commit/c96a1c0ba6b88fb47ca734013ae9b9248f78fbb4
Author: Igor Mammedov <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/i386/pc.c
Log Message:
-----------
pc: move pcms->possible_cpus init out of pc_cpus_init()
possible_cpus could be initialized earlier then cpu objects,
i.e. when -smp is parsed so move init code to possible_cpu_arch_ids()
interface func and do initialization on the first call.
it should help later with making -numa cpu/-smp parsing a machine state
properties.
Signed-off-by: Igor Mammedov <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c67ae9333cf94de2af043d65f3ce55ec26081c17
https://github.com/qemu/qemu/commit/c67ae9333cf94de2af043d65f3ce55ec26081c17
Author: Igor Mammedov <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/i386/pc.c
M include/hw/boards.h
Log Message:
-----------
pc: calculate topology only once when possible_cpus is initialised
Fill in CpuInstanceProperties once at board init time and
just copy them whenever query_hotpluggable_cpus() is called.
It will keep topology info always available without need
to recalculate it every time it's needed.
Considering it has NUMA node id, it will be used to keep
NUMA node to cpu mapping instead of numa_info[i].node_cpu
bitmasks.
Signed-off-by: Igor Mammedov <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1ea69c0e254094d3d45269ca2259d3bebd1ba9f5
https://github.com/qemu/qemu/commit/1ea69c0e254094d3d45269ca2259d3bebd1ba9f5
Author: Igor Mammedov <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/i386/pc.c
Log Message:
-----------
pc: pass apic_id to pc_find_cpu_slot() directly so lookup could be done
without CPU object
Signed-off-by: Igor Mammedov <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 8aba3842980954191a061d4618f80f368226ef5c
https://github.com/qemu/qemu/commit/8aba3842980954191a061d4618f80f368226ef5c
Author: Igor Mammedov <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/acpi/cpu.c
M hw/i386/pc.c
M include/hw/boards.h
Log Message:
-----------
change CPUArchId.cpu type to Object*
so it could be reused for SPAPR cores as well
Signed-off-by: Igor Mammedov <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 535455fdee60e4e7979a5060ba7a4e4588ee1a1e
https://github.com/qemu/qemu/commit/535455fdee60e4e7979a5060ba7a4e4588ee1a1e
Author: Igor Mammedov <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr: reuse machine->possible_cpus instead of cores[]
Replace SPAPR specific cores[] array with generic
machine->possible_cpus and store core objects there.
It makes cores bookkeeping similar to x86 cpus and
will allow to unify similar code.
It would allow to replace cpu_index based NUMA node
mapping with iproperty based one (for -device created
cores) since possible_cpus carries board defined
topology/layout.
Signed-off-by: Igor Mammedov <address@hidden>
Acked-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f2d672c248e359dd36081bbebc8854609cc9f112
https://github.com/qemu/qemu/commit/f2d672c248e359dd36081bbebc8854609cc9f112
Author: Igor Mammedov <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/core/machine.c
M hw/i386/pc.c
M hw/ppc/spapr.c
M include/hw/boards.h
Log Message:
-----------
machine: unify [pc_|spapr_]query_hotpluggable_cpus() callbacks
All callbacks FOO_query_hotpluggable_cpus() are practically
the same except of setting vcpus_count to different values.
Convert them to a generic machine_query_hotpluggable_cpus()
callback by moving vcpus_count initialization to per machine
specific callback possible_cpu_arch_ids().
Signed-off-by: Igor Mammedov <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c5514d0e4bafde751ec09439ba042b1f1cda37a7
https://github.com/qemu/qemu/commit/c5514d0e4bafde751ec09439ba042b1f1cda37a7
Author: Igor Mammedov <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/i386/pc.c
M hw/ppc/spapr.c
M include/hw/boards.h
M monitor.c
M vl.c
Log Message:
-----------
machine: replace query_hotpluggable_cpus() callback with
has_hotpluggable_cpus flag
Generic helper machine_query_hotpluggable_cpus() replaced
target specific query_hotpluggable_cpus() callbacks so
there is no need in it anymore. However inon NULL callback
value is used to detect/report hotpluggable cpus support,
therefore it can be removed completely.
Replace it with MachineClass.has_hotpluggable_cpus boolean
which is sufficient for the task.
Suggested-by: David Gibson <address@hidden>
Signed-off-by: Igor Mammedov <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 87684b4c4039fcf29ac9a95d46fed166e57d7ed9
https://github.com/qemu/qemu/commit/87684b4c4039fcf29ac9a95d46fed166e57d7ed9
Author: Sam Bobroff <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/net/spapr_llan.c
Log Message:
-----------
hw/net/spapr_llan: 6 byte mac address device tree entry
The spapr-vlan device in QEMU has always presented it's MAC address in
the device tree as an 8 byte value, even though PAPR requires it to be
6 bytes. This is because, at the time, AIX required the value to be 8
bytes. However, modern versions of AIX support the (correct) 6
byte value so they no longer require the workaround.
It would be neatest to always provide a 6 byte value but that would
cause a problem with old Linux kernel ibmveth drivers, so the old 8
byte value is still presented when necessary.
Since commit 13f85203e (3.10, May 2013) the driver has been able to
handle 6 or 8 byte addresses so versions after that don't need to be
considered specially.
Drivers from kernels before that can also handle either type of
address, but not always:
* If the first byte's lowest bits are 10, the address must be 6 bytes.
* Otherwise, the address must be 8 bytes.
(The two bits in question are significant in a MAC address: they
indicate a locally-administered unicast address.)
So to maintain compatibility the old 8 byte value is presented when
the lowest two bits of the first byte are not 10.
Signed-off-by: Sam Bobroff <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 0a4c774086d2246ca14abc5471bf2173d63a3d65
https://github.com/qemu/qemu/commit/0a4c774086d2246ca14abc5471bf2173d63a3d65
Author: Alex Zuepke <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M target/ppc/mmu_helper.c
Log Message:
-----------
target-ppc: fix Book-E TLB matching
The Book-E TLB matching process should bail out early when a TLB
entry matches, but the access permissions are wrong. The CPU
will then raise a DSI error instead of a Data TLB error, as
described for TLB matching in Freescale and IBM documents.
Signed-off-by: Alex Zuepke <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: df58713396f8b2deb923e39c00b10744c5c63909
https://github.com/qemu/qemu/commit/df58713396f8b2deb923e39c00b10744c5c63909
Author: Thomas Huth <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/ppc/spapr.c
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
Log Message:
-----------
hw/ppc/spapr: Check for valid page size when hot plugging memory
On POWER, the valid page sizes that the guest can use are bound
to the CPU and not to the memory region. QEMU already has some
fancy logic to find out the right maximum memory size to tell
it to the guest during boot (see getrampagesize() in the file
target/ppc/kvm.c for more information).
However, once we're booted and the guest is using huge pages
already, it is currently still possible to hot-plug memory regions
that does not support huge pages - which of course does not work
on POWER, since the guest thinks that it is possible to use huge
pages everywhere. The KVM_RUN ioctl will then abort with -EFAULT,
QEMU spills out a not very helpful error message together with
a register dump and the user is annoyed that the VM unexpectedly
died.
To avoid this situation, we should check the page size of hot-plugged
DIMMs to see whether it is possible to use it in the current VM.
If it does not fit, we can print out a better error message and
refuse to add it, so that the VM does not die unexpectely and the
user has a second chance to plug a DIMM with a matching memory
backend instead.
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1419466
Signed-off-by: Thomas Huth <address@hidden>
[dwg: Fix a build error on 32-bit builds with KVM]
Signed-off-by: David Gibson <address@hidden>
Commit: fb6971c110387cf597b58c411658e3d15cc6c6fb
https://github.com/qemu/qemu/commit/fb6971c110387cf597b58c411658e3d15cc6c6fb
Author: Peter Maydell <address@hidden>
Date: 2017-02-22 (Wed, 22 Feb 2017)
Changed paths:
M hw/ppc/ppc405_uc.c
Log Message:
-----------
hw/ppc/ppc405_uc.c: Avoid integer overflows
When performing clock calculations, the ppc405_uc code
has several places where it multiplies together two
32-bit variables and assigns the result to a 64-bit
variable. This doesn't quite do what is intended because
C will compute a 32-bit multiply result. Add casts to
ensure we don't truncate the result.
(Spotted by Coverity, CID 1005504, 1005505.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 55229247181c40baa3e92b08ee043d4e8453087e
https://github.com/qemu/qemu/commit/55229247181c40baa3e92b08ee043d4e8453087e
Author: Peter Maydell <address@hidden>
Date: 2017-02-24 (Fri, 24 Feb 2017)
Changed paths:
M fpu/softfloat.c
M hw/acpi/cpu.c
M hw/core/machine.c
M hw/i386/pc.c
M hw/net/spapr_llan.c
M hw/pci-host/prep.c
M hw/ppc/mac_newworld.c
M hw/ppc/pnv.c
M hw/ppc/ppc405_uc.c
M hw/ppc/ppc4xx_pci.c
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_ovec.c
M hw/ppc/trace-events
M include/fpu/softfloat.h
M include/hw/boards.h
M include/hw/i386/pc.h
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_cpu_core.h
M linux-user/main.c
M monitor.c
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/internal.h
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
M target/ppc/mmu-hash64.c
M target/ppc/mmu_helper.c
M target/ppc/translate.c
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
M target/ppc/translate_init.c
M vl.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170222' into
staging
ppc patch queue for 2017-02-22
This pull request has:
* Yet more POWER9 instruction implementations
* Some extensions to the softfloat code which are necesssary for
some of those instructions
* Some preliminary patches in preparation for POWER9 softmmu
implementation
* Igor Mammedov's cleanups to unify hotplug cpu handling across
architectures
* Assorted bugfixes
The softfloat and cpu hotplug changes aren't entirely ppc specific (in
fact the hotplug stuff contains some pc specific patches). However
they're included here because ppc is one of the main beneficiaries,
and the series depend on some ppc specific patches.
# gpg: Signature made Wed 22 Feb 2017 06:29:47 GMT
# gpg: using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg: aka "David Gibson (Red Hat) <address@hidden>"
# gpg: aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg: aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.9-20170222: (43 commits)
hw/ppc/ppc405_uc.c: Avoid integer overflows
hw/ppc/spapr: Check for valid page size when hot plugging memory
target-ppc: fix Book-E TLB matching
hw/net/spapr_llan: 6 byte mac address device tree entry
machine: replace query_hotpluggable_cpus() callback with
has_hotpluggable_cpus flag
machine: unify [pc_|spapr_]query_hotpluggable_cpus() callbacks
spapr: reuse machine->possible_cpus instead of cores[]
change CPUArchId.cpu type to Object*
pc: pass apic_id to pc_find_cpu_slot() directly so lookup could be done
without CPU object
pc: calculate topology only once when possible_cpus is initialised
pc: move pcms->possible_cpus init out of pc_cpus_init()
machine: move possible_cpus to MachineState
hw/pci-host/prep: Do not use hw_error() in realize function
target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv
target/ppc/POWER9: Adapt LPCR handling for POWER9
target/ppc/POWER9: Add ISAv3.00 MMU definition
target/ppc: Fix LPCR DPFD mask define
target-ppc: Add xscvqpudz and xscvqpuwz instructions
target-ppc: Implement round to odd variants of quad FP instructions
softfloat: Add float128_to_uint32_round_to_zero()
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/2d896b454a0e...55229247181c
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