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[Qemu-commits] [qemu/qemu] 4a09d0: target/openrisc: Rename the cpu from
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[Qemu-commits] [qemu/qemu] 4a09d0: target/openrisc: Rename the cpu from or32 to or1k |
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Date: |
Tue, 14 Feb 2017 03:15:10 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 4a09d0bb34ab030e09e87173b2e3ec0fd7616cff
https://github.com/qemu/qemu/commit/4a09d0bb34ab030e09e87173b2e3ec0fd7616cff
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M configure
A default-configs/or1k-linux-user.mak
A default-configs/or1k-softmmu.mak
R default-configs/or32-linux-user.mak
R default-configs/or32-softmmu.mak
M hw/openrisc/openrisc_sim.c
M target/openrisc/cpu.h
M tests/tcg/openrisc/Makefile
Log Message:
-----------
target/openrisc: Rename the cpu from or32 to or1k
This is in keeping with the toolchain and or1ksim.
Signed-off-by: Richard Henderson <address@hidden>
Commit: ab9023385576389e68b937d744de8ef8a0a4dc7a
https://github.com/qemu/qemu/commit/ab9023385576389e68b937d744de8ef8a0a4dc7a
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M linux-user/openrisc/target_syscall.h
Log Message:
-----------
linux-user: Add MMAP_SHIFT for openrisc
The page size on openrisc is 8k. Sync the shift
required for the mmap2 syscall.
Signed-off-by: Richard Henderson <address@hidden>
Commit: a0adc417a0b22e9b33a529133e04822753067f33
https://github.com/qemu/qemu/commit/a0adc417a0b22e9b33a529133e04822753067f33
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M linux-user/main.c
Log Message:
-----------
linux-user: Fix openrisc cpu_loop
We need to handle EXCP_DEBUG and EXCP_INTERRUPT.
We need to send signals to the guest using queue_signal.
Signed-off-by: Richard Henderson <address@hidden>
Commit: c40413a65eeb98d6f9eeb92544ab782c812ccc51
https://github.com/qemu/qemu/commit/c40413a65eeb98d6f9eeb92544ab782c812ccc51
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M linux-user/openrisc/target_cpu.h
Log Message:
-----------
linux-user: Honor CLONE_SETTLS for openrisc
Threads work much better when you set the TLS register.
This was fixed in the upstream kernel for Linux 4.9.
Signed-off-by: Richard Henderson <address@hidden>
Commit: c56e3b86701501364a4756201b6a9db9454463ab
https://github.com/qemu/qemu/commit/c56e3b86701501364a4756201b6a9db9454463ab
Author: Stafford Horne <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/interrupt.c
Log Message:
-----------
target/openrisc: Fix exception handling status registers
I am working on testing instruction emulation patches for the linux
kernel. During testing I found these 2 issues:
- sets DSX (delay slot exception) but never clears it
- EEAR for illegal insns should point to the bad exception (as per
openrisc spec) but its not
This patch fixes these two issues by clearing the DSX flag when not in a
delay slot and by setting EEAR to exception PC when handling illegal
instruction exceptions.
After this patch the openrisc kernel with latest patches boots great on
qemu and instruction emulation works.
Cc: address@hidden
Cc: address@hidden
Signed-off-by: Stafford Horne <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 930c3d0074ad0a5e26560f2133f82d803369bec3
https://github.com/qemu/qemu/commit/930c3d0074ad0a5e26560f2133f82d803369bec3
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/cpu.c
M target/openrisc/cpu.h
M target/openrisc/interrupt.c
M target/openrisc/interrupt_helper.c
M target/openrisc/machine.c
M target/openrisc/mmu.c
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Implement lwa, swa
Signed-off-by: Richard Henderson <address@hidden>
Commit: 111ece5133e1f301c43545e9400cbb2f121c0cc3
https://github.com/qemu/qemu/commit/111ece5133e1f301c43545e9400cbb2f121c0cc3
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Tidy insn dumping
Avoids warnings from unused variables etc.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 6da544a6c4572ed11931218e940f45d00b1fe3a7
https://github.com/qemu/qemu/commit/6da544a6c4572ed11931218e940f45d00b1fe3a7
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Rationalize immediate extraction
The architecture manual is consistent in using "I" for signed
fields and "K" for unsigned fields. Mirror that.
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 9ecaa27e7123211f45ca723a736ffae14f6c1f42
https://github.com/qemu/qemu/commit/9ecaa27e7123211f45ca723a736ffae14f6c1f42
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/Makefile.objs
M target/openrisc/exception_helper.c
M target/openrisc/helper.h
R target/openrisc/int_helper.c
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Streamline arithmetic and OVE
Fix incorrect overflow calculation. Move overflow exception check
to a helper function, to eliminate inline branches. Remove some
incorrect special casing of R0. Implement multiply inline.
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 0c53d7342b4e8412f3b81eed67f053304813dc5d
https://github.com/qemu/qemu/commit/0c53d7342b4e8412f3b81eed67f053304813dc5d
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/cpu.h
M target/openrisc/exception_helper.c
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Put SR[OVE] in TB flags
Removes a call at execution time for overflow exceptions.
Signed-off-by: Richard Henderson <address@hidden>
Commit: cf2ae4428f320f3d8027a50c1cd45f4b5a6c93bb
https://github.com/qemu/qemu/commit/cf2ae4428f320f3d8027a50c1cd45f4b5a6c93bb
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Invert the decoding in dec_calc
Decoding the opcodes in the right order reduces by 100+ lines.
Also, it happens to put the opcodes in the same order as Chapter 17.
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 84775c43f390d4f5dd9adf8732e7e0b6deed8f61
https://github.com/qemu/qemu/commit/84775c43f390d4f5dd9adf8732e7e0b6deed8f61
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M linux-user/elfload.c
M linux-user/main.c
M target/openrisc/cpu.h
M target/openrisc/gdbstub.c
M target/openrisc/interrupt.c
M target/openrisc/interrupt_helper.c
M target/openrisc/machine.c
M target/openrisc/sys_helper.c
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Keep SR_F in a separate variable
This avoids having to keep merging and extracting the flag from SR.
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 9745807191a81c45970f780166f44a7f93b18653
https://github.com/qemu/qemu/commit/9745807191a81c45970f780166f44a7f93b18653
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/cpu.h
M target/openrisc/exception_helper.c
M target/openrisc/helper.h
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Keep SR_CY and SR_OV in a separate variables
This significantly streamlines carry and overflow production.
Signed-off-by: Richard Henderson <address@hidden>
Commit: 784696d119d2c6709920e8f4c8c9b445a43a8e8c
https://github.com/qemu/qemu/commit/784696d119d2c6709920e8f4c8c9b445a43a8e8c
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Use movcond where appropriate
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 9fba702bd4be03f1df156d4d60178c4badc8ff2d
https://github.com/qemu/qemu/commit/9fba702bd4be03f1df156d4d60178c4badc8ff2d
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/helper.h
Log Message:
-----------
target/openrisc: Set flags on helpers
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 20dc52a37c81b672a5239b20527335508bcea02e
https://github.com/qemu/qemu/commit/20dc52a37c81b672a5239b20527335508bcea02e
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Enable trap, csync, msync, psync for user mode
Not documented as disabled for user mode.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 24fc5c0feb0d8ed3367c6628c14ac3ba6ebcbb89
https://github.com/qemu/qemu/commit/24fc5c0feb0d8ed3367c6628c14ac3ba6ebcbb89
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Implement msync
Signed-off-by: Richard Henderson <address@hidden>
Commit: 6f7332ba713bc4d36f1078990c5a48618933d6c3
https://github.com/qemu/qemu/commit/6f7332ba713bc4d36f1078990c5a48618933d6c3
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/cpu.h
M target/openrisc/machine.c
M target/openrisc/sys_helper.c
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Represent MACHI:MACLO as a single unit
Significantly simplifies the implementation of the use of MAC.
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: cc5de49ebe5b2881b88b22c13410f13657b472e0
https://github.com/qemu/qemu/commit/cc5de49ebe5b2881b88b22c13410f13657b472e0
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Implement muld, muldu, macu, msbu
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 762e22edcd021035e1dbcf0dbc31b4794c5c1027
https://github.com/qemu/qemu/commit/762e22edcd021035e1dbcf0dbc31b4794c5c1027
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/cpu.h
M target/openrisc/fpu_helper.c
M target/openrisc/helper.h
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Fix madd
Note that the specification for lf.madd.s is confused. It's
the only mention of supposed FPMADDHI/FPMADDLO special registers.
On the other hand, or1ksim implements a somewhat normal non-fused
multiply and add. Mirror that.
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: a8000cb480c8cfb612b039bf0382c41b9d6c7d45
https://github.com/qemu/qemu/commit/a8000cb480c8cfb612b039bf0382c41b9d6c7d45
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Optimize l.jal to next
This allows the tcg optimizer to see, and fold, all of the
constants involved in a GOT base register load sequence.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 24c328521b19aff2559118809ddf0522d6dfaaea
https://github.com/qemu/qemu/commit/24c328521b19aff2559118809ddf0522d6dfaaea
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/cpu.h
M target/openrisc/gdbstub.c
M target/openrisc/interrupt_helper.c
M target/openrisc/machine.c
M target/openrisc/sys_helper.c
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Tidy ppc/npc implementation
The NPC SPR is really only supposed to be used for FPGA debugging.
It contains the same contents as PC, unless one plays games. Follow
the or1ksim implementation in flushing delayed branch state when it
is changed.
The PPC SPR need not be updated every instruction, merely when we
exit the TB or attempt to read its contents.
Signed-off-by: Richard Henderson <address@hidden>
Commit: a01deb36a685365b4a3117112da3cc4f0f79e955
https://github.com/qemu/qemu/commit/a01deb36a685365b4a3117112da3cc4f0f79e955
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/cpu.h
M target/openrisc/gdbstub.c
M target/openrisc/interrupt.c
M target/openrisc/sys_helper.c
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Tidy handling of delayed branches
Signed-off-by: Richard Henderson <address@hidden>
Commit: 6597c28d618a3d16d468770b7c30a0237a8c8ea9
https://github.com/qemu/qemu/commit/6597c28d618a3d16d468770b7c30a0237a8c8ea9
Author: Richard Henderson <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M target/openrisc/cpu.h
M target/openrisc/exception_helper.c
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Optimize for r0 being zero
The HW does not special-case r0, but the ABI specifies that r0 should
contain 0. If we expose this fact to the optimizer, we can simplify
a lot of the generated code. We must of course verify that r0==0, but
that is trivial to do with a TB flag.
Signed-off-by: Richard Henderson <address@hidden>
Commit: 5dae13cd71f0755a1395b5a4cde635b8a6ee3f58
https://github.com/qemu/qemu/commit/5dae13cd71f0755a1395b5a4cde635b8a6ee3f58
Author: Peter Maydell <address@hidden>
Date: 2017-02-14 (Tue, 14 Feb 2017)
Changed paths:
M configure
A default-configs/or1k-linux-user.mak
A default-configs/or1k-softmmu.mak
R default-configs/or32-linux-user.mak
R default-configs/or32-softmmu.mak
M hw/openrisc/openrisc_sim.c
M linux-user/elfload.c
M linux-user/main.c
M linux-user/openrisc/target_cpu.h
M linux-user/openrisc/target_syscall.h
M target/openrisc/Makefile.objs
M target/openrisc/cpu.c
M target/openrisc/cpu.h
M target/openrisc/exception_helper.c
M target/openrisc/fpu_helper.c
M target/openrisc/gdbstub.c
M target/openrisc/helper.h
R target/openrisc/int_helper.c
M target/openrisc/interrupt.c
M target/openrisc/interrupt_helper.c
M target/openrisc/machine.c
M target/openrisc/mmu.c
M target/openrisc/sys_helper.c
M target/openrisc/translate.c
M tests/tcg/openrisc/Makefile
Log Message:
-----------
Merge remote-tracking branch 'remotes/rth/tags/pull-or-20170214' into staging
Queued openrisc patches
# gpg: Signature made Mon 13 Feb 2017 21:21:03 GMT
# gpg: using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <address@hidden>"
# gpg: aka "Richard Henderson <address@hidden>"
# gpg: aka "Richard Henderson <address@hidden>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B
* remotes/rth/tags/pull-or-20170214: (24 commits)
target/openrisc: Optimize for r0 being zero
target/openrisc: Tidy handling of delayed branches
target/openrisc: Tidy ppc/npc implementation
target/openrisc: Optimize l.jal to next
target/openrisc: Fix madd
target/openrisc: Implement muld, muldu, macu, msbu
target/openrisc: Represent MACHI:MACLO as a single unit
target/openrisc: Implement msync
target/openrisc: Enable trap, csync, msync, psync for user mode
target/openrisc: Set flags on helpers
target/openrisc: Use movcond where appropriate
target/openrisc: Keep SR_CY and SR_OV in a separate variables
target/openrisc: Keep SR_F in a separate variable
target/openrisc: Invert the decoding in dec_calc
target/openrisc: Put SR[OVE] in TB flags
target/openrisc: Streamline arithmetic and OVE
target/openrisc: Rationalize immediate extraction
target/openrisc: Tidy insn dumping
target/openrisc: Implement lwa, swa
target/openrisc: Fix exception handling status registers
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/ec7a9bd5bb2c...5dae13cd71f0
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