[Qemu-commits] [qemu/qemu] 26d320: integratorcp: adding vmstate for save/restore

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 26d320220778973310de0afa96974a2e9e987caf
      
https://github.com/qemu/qemu/commit/26d320220778973310de0afa96974a2e9e987caf
  Author: Pavel Dovgalyuk <address@hidden>
  Date:   2017-02-07 (Tue, 07 Feb 2017)

  Changed paths:
    M hw/arm/integratorcp.c

  Log Message:
  -----------
  integratorcp: adding vmstate for save/restore

VMState added by this patch preserves correct
loading of the integratorcp device state.

Signed-off-by: Pavel Dovgalyuk <address@hidden>
Message-id: address@hidden
[PMM: removed unnecessary minimum_version_id_old lines]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 854123bf8d4b8f4dcedcb03d0201e4305da45fe8
      
https://github.com/qemu/qemu/commit/854123bf8d4b8f4dcedcb03d0201e4305da45fe8
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-02-07 (Tue, 07 Feb 2017)

  Changed paths:
    M hw/watchdog/Makefile.objs
    A hw/watchdog/wdt_aspeed.c
    A include/hw/watchdog/wdt_aspeed.h

  Log Message:
  -----------
  wdt: Add Aspeed watchdog device model

The Aspeed SoC includes a set of watchdog timers using 32-bit
decrement counters, which can be based either on the APB clock or
a 1 MHz clock.

The watchdog timer is designed to prevent system deadlock and, in
general, it should be restarted before timeout. When a timeout occurs,
different types of signals can be generated, ARM reset, SOC reset,
System reset, CPU Interrupt, external signal or boot from alternate
block. The current model only performs the system reset function as
this is used by U-Boot and Linux.

Signed-off-by: Joel Stanley <address@hidden>
Message-id: address@hidden
[clg: - fixed compile breakage
      - fixed io region size
      - added watchdog_perform_action() on timer expiry
      - wrote a commit log
      - merged fixes from Andrew Jeffery to scale the reload value ]
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 013befe1ca055f555062c8ead083b3c214be97b1
      
https://github.com/qemu/qemu/commit/013befe1ca055f555062c8ead083b3c214be97b1
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-02-07 (Tue, 07 Feb 2017)

  Changed paths:
    M hw/arm/aspeed_soc.c
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  aspeed: add a watchdog controller

This enables reboot of a guest from U-Boot and Linux.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 42922105beb14c2fc58185ea022b9f72fb5465e9
      
https://github.com/qemu/qemu/commit/42922105beb14c2fc58185ea022b9f72fb5465e9
  Author: Prasad J Pandit <address@hidden>
  Date:   2017-02-07 (Tue, 07 Feb 2017)

  Changed paths:
    M hw/sd/sdhci.c

  Log Message:
  -----------
  sd: sdhci: check data length during dma_memory_read

While doing multi block SDMA transfer in routine
'sdhci_sdma_transfer_multi_blocks', the 's->fifo_buffer' starting
index 'begin' and data length 's->data_count' could end up to be same.
This could lead to an OOB access issue. Correct transfer data length
to avoid it.

Cc: address@hidden
Reported-by: Jiang Xin <address@hidden>
Signed-off-by: Prasad J Pandit <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 00909b585861ee3dca15f3d7624aac9be0f9080f
      
https://github.com/qemu/qemu/commit/00909b585861ee3dca15f3d7624aac9be0f9080f
  Author: Julian Brown <address@hidden>
  Date:   2017-02-07 (Tue, 07 Feb 2017)

  Changed paths:
    M hw/arm/integratorcp.c

  Log Message:
  -----------
  hw/arm/integratorcp: Support specifying features via -cpu

Since the integratorcp board creates the CPU object directly
rather than via cpu_arm_init(), we have to call the CPU
class parse_features() method ourselves if we want to
support the user passing features via the -cpu command
line argument as well as just the cpu name. Do so.

Signed-off-by: Julian Brown <address@hidden>
[PMM: split out into its own patch]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3a062d5730266b2386eeda68b1a1c6e96451db31
      
https://github.com/qemu/qemu/commit/3a062d5730266b2386eeda68b1a1c6e96451db31
  Author: Julian Brown <address@hidden>
  Date:   2017-02-07 (Tue, 07 Feb 2017)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Add cfgend parameter for ARM CPU selection.

Add a new "cfgend" property which selects whether the CPU resets into
big-endian mode or not.  This setting affects whether we reset with
SCTLR_B (ARMv6 and earlier) or SCTLR_EE (ARMv7 and later) set.

Signed-off-by: Julian Brown <address@hidden>
Message-id: address@hidden
[PMM: use error_report_err() rather than error_report();
 move the integratorcp changes to their own patch;
 drop an unnecessary extra #include;
 rephrase commit message accordingly;
 move setting of reset_sctlr above registration of cpregs
 so it actually has an effect]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f7478a92dd9ee2276bfaa5b7317140d3f9d6a53b
      
https://github.com/qemu/qemu/commit/f7478a92dd9ee2276bfaa5b7317140d3f9d6a53b
  Author: Julian Brown <address@hidden>
  Date:   2017-02-07 (Tue, 07 Feb 2017)

  Changed paths:
    M disas.c
    M include/disas/bfd.h
    M target/arm/arm_ldst.h
    M target/arm/cpu.c

  Log Message:
  -----------
  Fix Thumb-1 BE32 execution and disassembly.

Thumb-1 code has some issues in BE32 mode (as currently implemented). In
short, since bytes are swapped within words at load time for BE32
executables, this also swaps pairs of adjacent Thumb-1 instructions.

This patch un-swaps those pairs of instructions again, both for execution,
and for disassembly. (The previous version of the patch always read four
bytes in arm_read_memory_func and then extracted the proper two bytes,
in a probably misguided attempt to match the behaviour of actual hardware
as described by e.g. the ARM9TDMI TRM, section 3.3 "Endian effects for
instruction fetches". It's less complicated to just read the correct
two bytes though.)

Signed-off-by: Julian Brown <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 40612000599e52e792d23c998377a0fa429c4036
      
https://github.com/qemu/qemu/commit/40612000599e52e792d23c998377a0fa429c4036
  Author: Julian Brown <address@hidden>
  Date:   2017-02-07 (Tue, 07 Feb 2017)

  Changed paths:
    M exec.c
    M include/qom/cpu.h
    M qom/cpu.c
    M target/arm/cpu.c
    M target/arm/internals.h
    M target/arm/op_helper.c

  Log Message:
  -----------
  arm: Correctly handle watchpoints for BE32 CPUs

In BE32 mode, sub-word size watchpoints can fail to trigger because the
address of the access is adjusted in the opcode helpers before being
compared with the watchpoint registers.  This patch reverses the address
adjustment before performing the comparison with the help of a new CPUClass
hook.

This version of the patch augments and tidies up comments a little.

Signed-off-by: Julian Brown <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 63f26fcfda8e19f94ce23336726d14805250a5b6
      
https://github.com/qemu/qemu/commit/63f26fcfda8e19f94ce23336726d14805250a5b6
  Author: Peter Maydell <address@hidden>
  Date:   2017-02-07 (Tue, 07 Feb 2017)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode

In the ARM ldr/str decode path, rather than directly testing
"insn & (1 << 21)" and "insn & (1 << 24)", abstract these
bits out into wbit and pbit local flags. (We will want to
do more tests against them to determine whether we need to
provide syndrome information.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 9bb6558a218bf7e466e5ac1100639517d8a30d33
      
https://github.com/qemu/qemu/commit/9bb6558a218bf7e466e5ac1100639517d8a30d33
  Author: Peter Maydell <address@hidden>
  Date:   2017-02-07 (Tue, 07 Feb 2017)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: A32, T32: Create Instruction Syndromes for Data Aborts

Add support for generating the ISS (Instruction Specific Syndrome)
for Data Abort exceptions taken from AArch32. These syndromes are
used by hypervisors for example to trap and emulate memory accesses.

This is the equivalent for AArch32 guests of the work done for AArch64
guests in commit aaa1f954d4cab243.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 394c8bbfb7aeaa788c2bc99ca972d359847a6459
      
https://github.com/qemu/qemu/commit/394c8bbfb7aeaa788c2bc99ca972d359847a6459
  Author: Peter Maydell <address@hidden>
  Date:   2017-02-07 (Tue, 07 Feb 2017)

  Changed paths:
    M hw/arm/stellaris.c

  Log Message:
  -----------
  stellaris: Document memory map and which SoC devices are unimplemented

Add a comment documenting the memory map of the SoC devices and which
are not implemented.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: f5095aa3805f8cf91c4df6e7e1dab0d914bc40bc
      
https://github.com/qemu/qemu/commit/f5095aa3805f8cf91c4df6e7e1dab0d914bc40bc
  Author: Peter Maydell <address@hidden>
  Date:   2017-02-07 (Tue, 07 Feb 2017)

  Changed paths:
    M hw/misc/Makefile.objs
    A hw/misc/unimp.c
    A include/hw/misc/unimp.h

  Log Message:
  -----------
  hw/misc: New "unimplemented" sysbus device

Create a new "unimplemented" sysbus device, which simply accepts
all read and write accesses, and implements them as read-as-zero,
write-ignored, with logging of the access as LOG_UNIMP.

This is useful for stubbing out bits of an SoC or board model
which haven't been written yet.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: aecfbbc97a2e52bbee34a53c32f961a182046a95
      
https://github.com/qemu/qemu/commit/aecfbbc97a2e52bbee34a53c32f961a182046a95
  Author: Peter Maydell <address@hidden>
  Date:   2017-02-07 (Tue, 07 Feb 2017)

  Changed paths:
    M hw/arm/stellaris.c

  Log Message:
  -----------
  stellaris: Use the 'unimplemented' device for parts we don't implement

Use the 'unimplemented' dummy device to cover regions of the
SoC device memory map which we don't have proper device
implementations for yet.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: f073cd3a2bf1054135271b837c58a7da650dd84b
      
https://github.com/qemu/qemu/commit/f073cd3a2bf1054135271b837c58a7da650dd84b
  Author: Peter Maydell <address@hidden>
  Date:   2017-02-07 (Tue, 07 Feb 2017)

  Changed paths:
    M disas.c
    M exec.c
    M hw/arm/aspeed_soc.c
    M hw/arm/integratorcp.c
    M hw/arm/stellaris.c
    M hw/misc/Makefile.objs
    A hw/misc/unimp.c
    M hw/sd/sdhci.c
    M hw/watchdog/Makefile.objs
    A hw/watchdog/wdt_aspeed.c
    M include/disas/bfd.h
    M include/hw/arm/aspeed_soc.h
    A include/hw/misc/unimp.h
    A include/hw/watchdog/wdt_aspeed.h
    M include/qom/cpu.h
    M qom/cpu.c
    M target/arm/arm_ldst.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/internals.h
    M target/arm/op_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20170207-1' into staging

target-arm:
 * new "unimplemented" device for stubbing out devices in a
   system model so accesses can be logged
 * stellaris: document the SoC memory map
 * arm: create instruction syndromes for AArch32 data aborts
 * arm: Correctly handle watchpoints for BE32 CPUs
 * Fix Thumb-1 BE32 execution and disassembly
 * arm: Add cfgend parameter for ARM CPU selection
 * sd: sdhci: check data length during dma_memory_read
 * aspeed: add a watchdog controller
 * integratorcp: adding vmstate for save/restore

# gpg: Signature made Tue 07 Feb 2017 19:20:19 GMT
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170207-1:
  stellaris: Use the 'unimplemented' device for parts we don't implement
  hw/misc: New "unimplemented" sysbus device
  stellaris: Document memory map and which SoC devices are unimplemented
  target/arm: A32, T32: Create Instruction Syndromes for Data Aborts
  target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode
  arm: Correctly handle watchpoints for BE32 CPUs
  Fix Thumb-1 BE32 execution and disassembly.
  target/arm: Add cfgend parameter for ARM CPU selection.
  hw/arm/integratorcp: Support specifying features via -cpu
  sd: sdhci: check data length during dma_memory_read
  aspeed: add a watchdog controller
  wdt: Add Aspeed watchdog device model
  integratorcp: adding vmstate for save/restore

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/d0dff238a87f...f073cd3a2bf1