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[Qemu-commits] [qemu/qemu] bd97a5: disas/ppc: Fix indefinite articles in
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[Qemu-commits] [qemu/qemu] bd97a5: disas/ppc: Fix indefinite articles in comments |
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Date: |
Fri, 03 Feb 2017 02:00:06 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: bd97a59eeccc732fc67a821eeacafda8cf23b2f2
https://github.com/qemu/qemu/commit/bd97a59eeccc732fc67a821eeacafda8cf23b2f2
Author: Stefan Weil <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M disas/ppc.c
Log Message:
-----------
disas/ppc: Fix indefinite articles in comments
Signed-off-by: Stefan Weil <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 985e3023f7a041b35ee9590e393e3e5f7f224414
https://github.com/qemu/qemu/commit/985e3023f7a041b35ee9590e393e3e5f7f224414
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/internal.h
M target/ppc/translate.c
Log Message:
-----------
target-ppc: Consolidate instruction decode helpers
Move instruction decode helpers to target-ppc/internal.h so that some
of these can be used from outside of translate.c. This movement also
helps to get rid of some duplicate helpers from target-ppc/fpu_helper.c.
Suggested-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: efa7319619e92809c12b5f12f7f5bcdb044e7e21
https://github.com/qemu/qemu/commit/efa7319619e92809c12b5f12f7f5bcdb044e7e21
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/cpu.h
M target/ppc/int_helper.c
M target/ppc/translate.c
Log Message:
-----------
target-ppc: rename CRF_* defines as CRF_*_BIT
Add _BIT to CRF_[GT,LT,EQ_SO] and introduce CRF_[GT,LT,EQ,SO] for usage
without shifts in the code. This would simplify the code.
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 855f7a657e6061c241b5aa52c2a22cc94be4a63b
https://github.com/qemu/qemu/commit/855f7a657e6061c241b5aa52c2a22cc94be4a63b
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target-ppc: Fix xscmpodp and xscmpudp instructions
- xscmpodp & xscmpudp are missing flags reset.
- In xscmpodp, VXCC should be set only if VE is 0 for signalling NaN case
and VXCC should be set by explicitly checking for quiet NaN case.
- Comparison is being done only if the operands are not NaNs. However as
per ISA, it should be done even when operands are NaNs.
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3a20d11d451e9573af19ff312d61ee4da61cbbf0
https://github.com/qemu/qemu/commit/3a20d11d451e9573af19ff312d61ee4da61cbbf0
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xscmpexp[dp,qp] instructions
xscmpexpdp: VSX Scalar Compare Exponents Double-Precision
xscmpexpqp: VSX Scalar Compare Exponents Quad-Precision
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: be0a4faf35fa49d22dfd6a11ed858610881affde
https://github.com/qemu/qemu/commit/be0a4faf35fa49d22dfd6a11ed858610881affde
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xscmpoqp and xscmpuqp instructions
xscmpoqp - VSX Scalar Compare Ordered Quad-Precision
xscmpuqp - VSX Scalar Compare Unordered Quad-Precision
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5cb091a4fd434ae29fd329308dc2cb3d78a068e6
https://github.com/qemu/qemu/commit/5cb091a4fd434ae29fd329308dc2cb3d78a068e6
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/translate.c
M target/ppc/translate/fp-ops.inc.c
M target/ppc/translate/vsx-impl.inc.c
Log Message:
-----------
target-ppc: implement lxsd and lxssp instructions
lxsd: Load VSX Scalar Dword
lxssp: Load VSX Scalar Single
Moreover, DS-Form instructions shares the same primary opcode, bits
30:31 are used to decode the instruction. Use a common routine to decode
primary opcode(0x39) - ds-form instructions and branch-out depending on
bits 30:31.
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e3001664f1725de98e21196ae7aa53488c8e9029
https://github.com/qemu/qemu/commit/e3001664f1725de98e21196ae7aa53488c8e9029
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/translate.c
M target/ppc/translate/fp-ops.inc.c
M target/ppc/translate/vsx-impl.inc.c
Log Message:
-----------
target-ppc: implement stxsd and stxssp
stxsd: Store VSX Scalar Dword
stxssp: Store VSX Scalar SP
Moreover, DQ-Form/DS-FORM instructions shares the same primary
opcode(0x3D). For DQ-FORM bits 29:31 are used, for DS-FORM bits 30:31
are used. Common routine to decode primary opcode(0x3D) -
ds-form/dq-form instructions is required.
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d59ba5838073226312a34074d4b15c6acc4a228d
https://github.com/qemu/qemu/commit/d59ba5838073226312a34074d4b15c6acc4a228d
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/internal.h
M target/ppc/translate.c
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: implement lxv/lxvx and stxv/stxvx
lxv: Load VSX Vector
lxvx: Load VSX Vector Indexed
Little/Big-endian Storage
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Vector load results:
BE:
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
LE:
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|E7|E6|E5|E4|E3|E2|E1|E0|F7|F6|F5|F4|F3|F2|F1|F0|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
stxv: Store VSX Vector
stxvx: Store VSX Vector Indexed
Vector (8-bit elements) in BE:
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Vector (8-bit elements) in LE:
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|E7|E6|E5|E4|E3|E2|E1|E0|F7|F6|F5|F4|F3|F2|F1|F0|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Store results in following:
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a406c058e7ae2470facf0db85dbd91ae5df634fc
https://github.com/qemu/qemu/commit/a406c058e7ae2470facf0db85dbd91ae5df634fc
Author: Jose Ricardo Ziviani <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.inc.c
Log Message:
-----------
target-ppc: Implement bcdcfsq. instruction
bcdcfsq.: Decimal convert from signed quadword. It is not possible
to convert values less than -10^31-1 or greater than 10^31-1 to be
represented in packed decimal format.
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
[dwg: Corrected constant which should be 10^16-1 but was 10^17-1]
Signed-off-by: David Gibson <address@hidden>
Commit: c85bc7dd90219c2b0ebe278187f5efa7e465687c
https://github.com/qemu/qemu/commit/c85bc7dd90219c2b0ebe278187f5efa7e465687c
Author: Jose Ricardo Ziviani <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.inc.c
Log Message:
-----------
target-ppc: Implement bcdctsq. instruction
bcdctsq.: Decimal convert to signed quadword. It is possible to
convert packed decimal values to signed quadwords.
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c3025c3b0aa6baea66be11fa97c5ecbcbff09677
https://github.com/qemu/qemu/commit/c3025c3b0aa6baea66be11fa97c5ecbcbff09677
Author: Jose Ricardo Ziviani <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.inc.c
M target/ppc/translate/vmx-ops.inc.c
Log Message:
-----------
target-ppc: Implement bcdcpsgn. instruction
bcdcpsgn.: Decimal copy sign. Given two registers vra and vrb, it
copies the vra value with vrb sign to the result register vrt.
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 466a3f9ca34dabb40f5e2c9c143939304cd6fb9e
https://github.com/qemu/qemu/commit/466a3f9ca34dabb40f5e2c9c143939304cd6fb9e
Author: Jose Ricardo Ziviani <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.inc.c
Log Message:
-----------
target-ppc: Implement bcdsetsgn. instruction
bcdsetsgn.: Decimal set sign. This instruction copies the register
value to the result register but adjust the signal according to
the preferred sign value.
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 60caf2216bf03d0f32ef11cb670279d0dea6d593
https://github.com/qemu/qemu/commit/60caf2216bf03d0f32ef11cb670279d0dea6d593
Author: Avinesh Kumar <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.inc.c
M target/ppc/translate/vmx-ops.inc.c
Log Message:
-----------
target-ppc: add vextu[bhw][lr]x instructions
vextublx: Vector Extract Unsigned Byte Left
vextuhlx: Vector Extract Unsigned Halfword Left
vextuwlx: Vector Extract Unsigned Word Left
vextubrx: Vector Extract Unsigned Byte Right-Indexed VX-form
vextuhrx: Vector Extract Unsigned Halfword Right-Indexed VX-form
vextuwrx: Vector Extract Unsigned Word Right-Indexed VX-form
Signed-off-by: Avinesh Kumar <address@hidden>
Signed-off-by: Hariharan T.S. <address@hidden>
[ implement using int128_rshift ]
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 0c86d0fd92aaecc2e69041dc747299dbc0be4bb9
https://github.com/qemu/qemu/commit/0c86d0fd92aaecc2e69041dc747299dbc0be4bb9
Author: David Gibson <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
M include/hw/ppc/spapr.h
Log Message:
-----------
pseries: Always use core objects for CPU construction
Currently the pseries machine has two paths for constructing CPUs. On
newer machine type versions, which support cpu hotplug, it constructs
cpu core objects, which in turn construct CPU threads. For older machine
versions it individually constructs the CPU threads.
This division is going to make some future changes to the cpu construction
harder, so this patch unifies them. Now cpu core objects are always
created. This requires some updates to allow core objects to be created
without a full complement of threads (since older versions allowed a
number of cpus not a multiple of the threads-per-core). Likewise it needs
some changes to the cpu core hot/cold plug path so as not to choke on the
old machine types without hotplug support.
For good measure, we move the cpu construction to its own subfunction,
spapr_init_cpus().
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: 5b120785e70a9a48b43e3f1f156a10a015334a28
https://github.com/qemu/qemu/commit/5b120785e70a9a48b43e3f1f156a10a015334a28
Author: David Gibson <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr.h
Log Message:
-----------
pseries: Make cpu_update during CAS unconditional
spapr_h_cas_compose_response() includes a cpu_update parameter which
controls whether it includes updated information on the CPUs in the device
tree fragment returned from the ibm,client-architecture-support (CAS) call.
Providing the updated information is essential when CAS has negotiated
compatibility options which require different cpu information to be
presented to the guest. However, it should be safe to provide in other
cases (it will just override the existing data in the device tree with
identical data). This simplifies the code by removing the parameter and
always providing the cpu update information.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Commit: 1d1be34d26b66069e20cbbcd798ea57763a0f152
https://github.com/qemu/qemu/commit/1d1be34d26b66069e20cbbcd798ea57763a0f152
Author: David Gibson <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
M target/ppc/cpu.h
M target/ppc/excp_helper.c
M target/ppc/translate_init.c
Log Message:
-----------
ppc: Clean up and QOMify hypercall emulation
The pseries machine type is a bit unusual in that it runs a paravirtualized
guest. The guest expects to interact with a hypervisor, and qemu
emulates the functions of that hypervisor directly, rather than executing
hypervisor code within the emulated system.
To implement this in TCG, we need to intercept hypercall instructions and
direct them to the machine's hypercall handlers, rather than attempting to
perform a privilege change within TCG. This is controlled by a global
hook - cpu_ppc_hypercall.
This cleanup makes the handling a little cleaner and more extensible than
a single global variable. Instead, each CPU to have hypercalls intercepted
has a pointer set to a QOM object implementing a new virtual hypervisor
interface. A method in that interface is called by TCG when it sees a
hypercall instruction. It's possible we may want to add other methods in
future.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Commit: d6e166c08203f47017555f5f52b70f35399c824c
https://github.com/qemu/qemu/commit/d6e166c08203f47017555f5f52b70f35399c824c
Author: David Gibson <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M target/ppc/cpu.h
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
M target/ppc/translate_init.c
Log Message:
-----------
ppc: Rename cpu_version to compat_pvr
The 'cpu_version' field in PowerPCCPU is badly named. It's named after the
'cpu-version' device tree property where it is advertised, but that meaning
may not be obvious in most places it appears.
Worse, it doesn't even really correspond to that device tree property. The
property contains either the processor's PVR, or, if the CPU is running in
a compatibility mode, a special "logical PVR" representing which mode.
Rename the cpu_version field, and a number of related variables to
compat_pvr to make this clearer.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Commit: 1c7ad77e56767fb36a7ccc954d304d4ac768b374
https://github.com/qemu/qemu/commit/1c7ad77e56767fb36a7ccc954d304d4ac768b374
Author: Nicholas Piggin <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr.h
Log Message:
-----------
ppc/spapr: implement H_SIGNAL_SYS_RESET
The H_SIGNAL_SYS_RESET hcall allows a guest CPU to raise a system reset
exception on CPUs within the same guest -- all CPUs, all-but-self, or a
specific CPU (including self).
This has not made its way to a PAPR release yet, but we have an hcall
number assigned.
H_SIGNAL_SYS_RESET = 0x380
Syntax:
hcall(uint64 H_SIGNAL_SYS_RESET, int64 target);
Generate a system reset NMI on the threads indicated by target.
Values for target:
-1 = target all online threads including the caller
-2 = target all online threads except for the caller
All other negative values: reserved
Positive values: The thread to be targeted, obtained from the value
of the "ibm,ppc-interrupt-server#s" property of the CPU in the OF
device tree.
Semantics:
- Invalid target: return H_Parameter.
- Otherwise: Generate a system reset NMI on target thread(s),
return H_Success.
Signed-off-by: Nicholas Piggin <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f9f2ed5ae012d5023a77d847e962ecde22823102
https://github.com/qemu/qemu/commit/f9f2ed5ae012d5023a77d847e962ecde22823102
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/internal.h
Log Message:
-----------
target-ppc: move ppc_vsr_t to common header
The structure and corresponding defines and functions need to be used
outside of fpu_helper.c as well.
Add u8, u16, u32 and Int128 to the structure.
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: cdee0e72d0a03fe8b7f1b201ead0737cca4997db
https://github.com/qemu/qemu/commit/cdee0e72d0a03fe8b7f1b201ead0737cca4997db
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target-ppc: implement stop instruction
Use the nap code.
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3259dbd9df967554dd8f77ec0afbb863e2664a2a
https://github.com/qemu/qemu/commit/3259dbd9df967554dd8f77ec0afbb863e2664a2a
Author: David Gibson <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: implement xsabsqp/xsnabsqp instruction
xsabsqp: VSX Scalar Absolute Quad-Precision
xsnabsqp: VSX Scalar Negative Absolute Quad-Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 071663dfc3b93e3f3e573d726cfb685fd25472fa
https://github.com/qemu/qemu/commit/071663dfc3b93e3f3e573d726cfb685fd25472fa
Author: Jose Ricardo Ziviani <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/int_helper.c
Log Message:
-----------
target-ppc: Implement bcd_is_valid function
A function to check if all digits of a given BCD number is valid is
here presented because more instructions will need to reuse the
same code.
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 8497d7fc69c04d253ae5b0ee5db7745ea07dbe19
https://github.com/qemu/qemu/commit/8497d7fc69c04d253ae5b0ee5db7745ea07dbe19
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: implement xsnegqp instruction
xsnegqp: VSX Scalar Negate Quad-Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 014ed3bb2015dcbe614b8ee2d505a43ab197db07
https://github.com/qemu/qemu/commit/014ed3bb2015dcbe614b8ee2d505a43ab197db07
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: implement xscpsgnqp instruction
xscpsgnqp: VSX Scalar Copy Sign Quad-Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 234068abfb345f08b160be71e0a4099c19384712
https://github.com/qemu/qemu/commit/234068abfb345f08b160be71e0a4099c19384712
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xxperm and xxpermr instructions
xxperm: VSX Vector Permute
xxpermr: VSX Vector Permute Right-indexed
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 6914bc4fb5c16cdf92d59e620e3f69de302ed838
https://github.com/qemu/qemu/commit/6914bc4fb5c16cdf92d59e620e3f69de302ed838
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/helper.h
M target/ppc/mem_helper.c
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: implement lxvl instruction
lxvl: Load VSX Vector with Length
Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Loading 14 bytes results in:
Vector (8-bit elements) in BE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Vector (8-bit elements) in LE:
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|00|00|“T”|“S”|“E”|“T”|“ ”|“a”|“ ”|“s”|“i”|“ ”|“s”|“i”|"h"|"T"|
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 176e44e7ebd6da47165c9444f2330ef8f7011deb
https://github.com/qemu/qemu/commit/176e44e7ebd6da47165c9444f2330ef8f7011deb
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/helper.h
M target/ppc/mem_helper.c
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: implement lxvll instruction
lxvll: Load VSX Vector Left-justified with Length
Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Loading 14 bytes to vector (8-bit elements) in BE/LE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 681c247833430edb4d91a8fd9c754f470a9f2074
https://github.com/qemu/qemu/commit/681c247833430edb4d91a8fd9c754f470a9f2074
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/helper.h
M target/ppc/mem_helper.c
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: implement stxvl instruction
stxvl: Store VSX Vector with Length
Vector (8-bit elements) in BE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Vector (8-bit elements) in LE:
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|00|00|“T”|“S”|“E”|“T”|“ ”|“a”|“ ”|“s”|“i”|“ ”|“s”|“i”|"h"|"T"|
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Storing 14 bytes would result in following Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e122090df3e681b42d19a55486ff5c54f2c1e717
https://github.com/qemu/qemu/commit/e122090df3e681b42d19a55486ff5c54f2c1e717
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/helper.h
M target/ppc/mem_helper.c
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: implement stxvll instructions
stxvll: Store VSX Vector Left-justified with Length
Vector (8-bit elements) in BE/LE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Storing 14 bytes would result in following Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b99260ebbb5844da9e77fbcaa73b7b6980a68acf
https://github.com/qemu/qemu/commit/b99260ebbb5844da9e77fbcaa73b7b6980a68acf
Author: Thomas Huth <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/spapr.c
M hw/usb/host-libusb.c
M hw/usb/host-stub.c
M include/hw/usb.h
Log Message:
-----------
hw/ppc/spapr: Fix boot path of usb-host storage devices
When passing through an USB storage device to a pseries guest, it
is currently not possible to automatically boot from the device
if the "bootindex" property has been specified, too (e.g. when using
"-device nec-usb-xhci -device usb-host,hostbus=1,hostaddr=2,bootindex=0"
at the command line). The problem is that QEMU builds a device tree path
like "/address@hidden/address@hidden/address@hidden" and passes it to SLOF
in the /chosen/qemu,boot-list property. SLOF, however, probes the
USB device, recognizes that it is a storage device and thus changes
its name to "storage", and additionally adds a child node for the
SCSI LUN, so the correct boot path in SLOF is something like
"/address@hidden/address@hidden/address@hidden/address@hidden" instead.
So when we detect an USB mass storage device with SCSI interface,
we've got to adjust the firmware boot-device path properly that
SLOF can automatically boot from the device.
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1354177
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5904bca84ed3b41b983e14a5adc388400cf737e6
https://github.com/qemu/qemu/commit/5904bca84ed3b41b983e14a5adc388400cf737e6
Author: Hervé Poussineau <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/prep.c
Log Message:
-----------
prep: do not use global variable to access nvram
Signed-off-by: Hervé Poussineau <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: fa325e6cbf343eba3a5ad8294929e503187ec0b9
https://github.com/qemu/qemu/commit/fa325e6cbf343eba3a5ad8294929e503187ec0b9
Author: David Gibson <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
pseries: Add pseries-2.9 machine type
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Commit: 9d6f106552fa5ad9e3128b5052863835526ba271
https://github.com/qemu/qemu/commit/9d6f106552fa5ad9e3128b5052863835526ba271
Author: David Gibson <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/Makefile.objs
A target/ppc/compat.c
M target/ppc/cpu.h
M target/ppc/translate_init.c
Log Message:
-----------
ppc: Rewrite ppc_set_compat()
This rewrites the ppc_set_compat() function so that instead of open coding
the various compatibility modes, it reads the relevant data from a table.
This is a first step in consolidating the information on compatibility
modes scattered across the code into a single place.
It also makes one change to the logic. The old code masked the bits
to be set in the PCR (Processor Compatibility Register) by which bits
are valid on the host CPU. This made no sense, since it was done
regardless of whether our guest CPU was the same as the host CPU or
not. Furthermore, the actual PCR bits are only relevant for TCG[1] -
KVM instead uses the compatibility mode we tell it in
kvmppc_set_compat(). When using TCG host cpu information usually
isn't even present.
While we're at it, we put the new implementation in a new file to make the
enormous translate_init.c a little smaller.
[1] Actually it doesn't even do anything in TCG, but it will if / when we
get to implementing compatibility mode logic at that level.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Commit: 12dbeb16d0984fe03bd4bc5cd952187627a22ce9
https://github.com/qemu/qemu/commit/12dbeb16d0984fe03bd4bc5cd952187627a22ce9
Author: David Gibson <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/spapr.c
M target/ppc/compat.c
M target/ppc/cpu.h
M target/ppc/translate_init.c
Log Message:
-----------
ppc: Rewrite ppc_get_compat_smt_threads()
To continue consolidation of compatibility mode information, this rewrites
the ppc_get_compat_smt_threads() function using the table of compatiblity
modes in target-ppc/compat.c.
It's not a direct replacement, the new ppc_compat_max_threads() function
has simpler semantics - it just returns the number of threads the cpu
model has, taking into account any compatiblity mode it is in.
This no longer takes into account kvmppc_smt_threads() as the previous
version did. That check wasn't useful because we check in
ppc_cpu_realizefn() that CPUs aren't instantiated with more threads
than kvm allows (or if we didn't things will already be broken and
this won't make it any worse).
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Commit: 9d2179d6f960aef1b8aab4d014fd8385f0a187e5
https://github.com/qemu/qemu/commit/9d2179d6f960aef1b8aab4d014fd8385f0a187e5
Author: David Gibson <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/compat.c
M target/ppc/cpu.h
Log Message:
-----------
ppc: Validate compatibility modes when setting
Current ppc_set_compat() will attempt to set any compatiblity mode
specified, regardless of whether it's available on the CPU. The caller is
expected to make sure it is setting a possible mode, which is awkwward
because most of the information to make that decision is at the CPU level.
This begins to clean this up by introducing a ppc_check_compat() function
which will determine if a given compatiblity mode is supported on a CPU
(and also whether it lies within specified minimum and maximum compat
levels, which will be useful later). It also contains an assertion that
the CPU has a "virtual hypervisor"[1], that is, that the guest isn't
permitted to execute hypervisor privilege code. Without that, the guest
would own the PCR and so could override any mode set here. Only machine
types which use a virtual hypervisor (i.e. 'pseries') should use
ppc_check_compat().
ppc_set_compat() is modified to validate the compatibility mode it is given
and fail if it's not available on this CPU.
[1] Or user-only mode, which also obviously doesn't allow access to the
hypervisor privileged PCR. We don't use that now, but could in future.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Commit: 2f8e4906ff1cb2fdd2637ced9596a3d675fee861
https://github.com/qemu/qemu/commit/2f8e4906ff1cb2fdd2637ced9596a3d675fee861
Author: Laurent Vivier <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M tests/Makefile.include
Log Message:
-----------
qtest: add netfilter tests for ppc64
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Tested-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f38a0b2fd7fdf30272225018284c8afdab4c1977
https://github.com/qemu/qemu/commit/f38a0b2fd7fdf30272225018284c8afdab4c1977
Author: Laurent Vivier <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M tests/Makefile.include
M tests/display-vga-test.c
Log Message:
-----------
qtest: add display-vga-test to ppc64
Only enable for ppc64 in the Makefile, but added
code in the file to check cirrus card only on architectures
supporting it (alpha, mips, i386, x86_64).
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Tested-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b84541693b373112d30e54c42815d7b6d2623fd6
https://github.com/qemu/qemu/commit/b84541693b373112d30e54c42815d7b6d2623fd6
Author: Laurent Vivier <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M tests/libqos/pci-spapr.c
Log Message:
-----------
libqos: fix spapr qpci_map()
Signed-off-by: Laurent Vivier <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d69487d573e37f46d14c92a51d39e1db496bc431
https://github.com/qemu/qemu/commit/d69487d573e37f46d14c92a51d39e1db496bc431
Author: Laurent Vivier <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M tests/ivshmem-test.c
Log Message:
-----------
qtest: convert ivshmem-test to use libqos
This will allow to use it with ppc64.
Signed-off-by: Laurent Vivier <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2bf25e07bb2d2b0e1a551c86189afc896ca35dea
https://github.com/qemu/qemu/commit/2bf25e07bb2d2b0e1a551c86189afc896ca35dea
Author: Laurent Vivier <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M tests/Makefile.include
M tests/ivshmem-test.c
Log Message:
-----------
qtest: add ivshmem-test for ppc64
The test has been converted to use libqos, we can
now use it on ppc64. We also make the test fail on
all other architectures.
As libqos on ppc64 is not able to manage hotplug
and IRQ/MSI, we disable this part in the test on ppc64.
Signed-off-by: Laurent Vivier <address@hidden>
[dwg: Make test conditional on CONFIG_EVENTFD]
Signed-off-by: David Gibson <address@hidden>
Commit: 396781f62739329263651ebfe50c4f98a821f721
https://github.com/qemu/qemu/commit/396781f62739329263651ebfe50c4f98a821f721
Author: xiaoqiang zhao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/gpio/mpc8xxx.c
Log Message:
-----------
hw/gpio: QOM'ify mpc8xxx.c
* Drop the old SysBus init function and use instance_init
* Change mpc8xxx_gpio_reset to a DeviceClass::reset function
Signed-off-by: xiaoqiang zhao <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d0c2b0d089898b261179c5daac0db291aded3389
https://github.com/qemu/qemu/commit/d0c2b0d089898b261179c5daac0db291aded3389
Author: xiaoqiang zhao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/e500.c
Log Message:
-----------
hw/ppc: QOM'ify e500.c
Drop the old SysBus init function and use instance_init
Signed-off-by: xiaoqiang zhao <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 09a7eb978f819f0ef537f305f88e609835cfb0f2
https://github.com/qemu/qemu/commit/09a7eb978f819f0ef537f305f88e609835cfb0f2
Author: xiaoqiang zhao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/ppce500_spin.c
Log Message:
-----------
hw/ppc: QOM'ify ppce500_spin.c
Drop the old SysBus init function and use instance_init
Signed-off-by: xiaoqiang zhao <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 0f358a0710cf8fe9ebf5aed144adb3199a68e6a7
https://github.com/qemu/qemu/commit/0f358a0710cf8fe9ebf5aed144adb3199a68e6a7
Author: xiaoqiang zhao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/spapr_vio.c
Log Message:
-----------
hw/ppc: QOM'ify spapr_vio.c
Drop the old and empty SysBus init
Signed-off-by: xiaoqiang zhao <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 8ad901e55884055e0ec5ee7f47b955f42b66cb9a
https://github.com/qemu/qemu/commit/8ad901e55884055e0ec5ee7f47b955f42b66cb9a
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xxextractuw instruction
xxextractuw: VSX Vector Extract Unsigned Word
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3398b7428ba3964f6150590cde46d45c68d2fc25
https://github.com/qemu/qemu/commit/3398b7428ba3964f6150590cde46d45c68d2fc25
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xxinsertw instruction
xxinsertw: VSX Vector Insert Word
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d2f8415226611984b62d4e1d72acb7aba8903cb4
https://github.com/qemu/qemu/commit/d2f8415226611984b62d4e1d72acb7aba8903cb4
Author: Hervé Poussineau <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/Makefile.objs
A hw/ppc/prep_systemio.c
M hw/ppc/trace-events
Log Message:
-----------
prep: add PReP System I/O
This device is a partial duplicate of System I/O device available in
hw/ppc/prep.c
This new one doesn't have all the Motorola-specific registers.
The old one should be deprecated and removed with the 'prep' machine.
Partial documentation available at
ftp://ftp.software.ibm.com/rs6000/technology/spec/srp1_1.exe
section 6.1.5 (I/O Device Mapping)
Signed-off-by: Hervé Poussineau <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 79623312c68fc07376ca7d3923137ad1abc7496c
https://github.com/qemu/qemu/commit/79623312c68fc07376ca7d3923137ad1abc7496c
Author: Hervé Poussineau <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M default-configs/ppc-softmmu.mak
M default-configs/ppc64-softmmu.mak
M hw/ppc/Makefile.objs
A hw/ppc/rs6000_mc.c
M hw/ppc/trace-events
Log Message:
-----------
prep: add IBM RS/6000 7020 (40p) memory controller
Signed-off-by: Hervé Poussineau <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[dwg: Added CONFIG_RS6000_MC to ppc64 or it breaks testcases]
Signed-off-by: David Gibson <address@hidden>
Commit: 34b9b5575b7752ea13fd147b3e7a3e24b2975e8f
https://github.com/qemu/qemu/commit/34b9b5575b7752ea13fd147b3e7a3e24b2975e8f
Author: Hervé Poussineau <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M default-configs/ppc-softmmu.mak
M hw/ppc/prep.c
Log Message:
-----------
prep: add IBM RS/6000 7020 (40p) machine emulation
Machine supports both Open Hack'Ware and OpenBIOS.
Open Hack'Ware is the default because OpenBIOS is currently unable to boot
PReP boot partitions or PReP kernels.
Signed-off-by: Hervé Poussineau <address@hidden>
[dwg: Correct compile failure with KVM located by Thomas Huth]
Signed-off-by: David Gibson <address@hidden>
Commit: 1383602e0daed0f4f9faefce0a88a296d6e94ae7
https://github.com/qemu/qemu/commit/1383602e0daed0f4f9faefce0a88a296d6e94ae7
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target-ppc: Use float64 arg in helper_compute_fprf()
Use float64 argument instead of unit64_t in helper_compute_fprf()
This allows code in helper_compute_fprf() to be reused later to
work with float128 argument too.
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5dc22bf58184a8da41e5d346570665fc99c0ca5f
https://github.com/qemu/qemu/commit/5dc22bf58184a8da41e5d346570665fc99c0ca5f
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target-ppc: Replace isden by float64_is_zero_or_denormal
Replace isden() by float64_is_zero_or_denormal() so that code in
helper_compute_fprf() can be reused to work with float128 argument.
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ffc67420f9d96fd30a6b51ee0d3e19a067750bc0
https://github.com/qemu/qemu/commit/ffc67420f9d96fd30a6b51ee0d3e19a067750bc0
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.inc.c
Log Message:
-----------
target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64
Since helper_compute_fprf() works on float64 argument, rename it
to helper_compute_fprf_float64(). Also use a macro to generate
helper_compute_fprf_float64() so that float128 version of the same
helper can be introduced easily later.
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f566c0474a9b9bbd9ed248607e4007e24d3358c0
https://github.com/qemu/qemu/commit/f566c0474a9b9bbd9ed248607e4007e24d3358c0
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M include/fpu/softfloat.h
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/internal.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xscvdphp, xscvhpdp
xscvdphp: VSX Scalar round & Convert Double-Precision format to
Half-Precision format
xscvhpdp: VSX Scalar Convert Half-Precision format to
Double-Precision format
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 9aeae8e16e6153aa2f28272dc75904c94f0e8cac
https://github.com/qemu/qemu/commit/9aeae8e16e6153aa2f28272dc75904c94f0e8cac
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/internal.h
Log Message:
-----------
target-ppc: Use correct precision for FPRF setting
Use correct FP precision when setting FPRF in FP conversion helpers
instead of always assuming float64 precision.
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 08e149869e4c391f7006c3621cfbe0945a19b4dd
https://github.com/qemu/qemu/commit/08e149869e4c391f7006c3621cfbe0945a19b4dd
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xsxexpdp instruction
xsxexpdp: VSX Scalar Extract Exponent Dual Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 9eceae320e7300473b5eb20c160c1730714f1692
https://github.com/qemu/qemu/commit/9eceae320e7300473b5eb20c160c1730714f1692
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xsxexpqp instruction
xsxexpqp: VSX Scalar Extract Exponent Quad Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 05538220acaad3c7e8e438221fe97e483b451637
https://github.com/qemu/qemu/commit/05538220acaad3c7e8e438221fe97e483b451637
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xsxsigdp instruction
xsxsigdp: VSX Scalar Extract Significand Dual Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 29f8ddb72fb689f08deecc61a42f66eabd10f361
https://github.com/qemu/qemu/commit/29f8ddb72fb689f08deecc61a42f66eabd10f361
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xsxsigqp instructions
xsxsigqp: VSX Scalar Extract Significand Quad Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ef291226494f53f10c5cbe90bff550a52bda7b76
https://github.com/qemu/qemu/commit/ef291226494f53f10c5cbe90bff550a52bda7b76
Author: David Gibson <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M default-configs/i386-softmmu.mak
M default-configs/x86_64-softmmu.mak
M hw/pci-bridge/Makefile.objs
Log Message:
-----------
pxb: Restrict to x86
The PCI Expander Bridge (PXB) device is essentially a hack to allow
different PCIe devices to be assigned to different NUMA nodes on x86. Each
PXB is sort-of a separate PCI host bridge, except that its config space
is shared with the config space of the main PCI host bridge, rather than
being independent.
This is only necessary if the platform doesn't (easily) allow truly
independent PCI host bridges. AFAIK that's just x86.
This patch makes it possible to configure PXB out of the build, and adjusts
the default configs so it's only included on x86 targets.
Signed-off-by: David Gibson <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Commit: 152ef803ceb1959e2380a1da7736b935b109222e
https://github.com/qemu/qemu/commit/152ef803ceb1959e2380a1da7736b935b109222e
Author: David Gibson <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/spapr_hcall.c
M hw/ppc/trace-events
Log Message:
-----------
pseries: Rewrite CAS PVR compatibility logic
During boot, PAPR guests negotiate CPU model support with the
ibm,client-architecture-support mechanism. The logic to implement this in
qemu is very convoluted. This cleans it up to be cleaner, using the new
ppc_check_compat() call.
The new logic for choosing a compatibility mode is:
1. Usually, use the most recent compatibility mode that is
a) supported by the guest
b) supported by the CPU
and c) no later than the maximum allowed (if specified)
2. If no suitable compatibility mode was found, the guest *does*
support this CPU explicitly, and no maximum compatibility mode is
specified, then use "raw" mode for the current CPU
3. Otherwise, fail the boot.
This differs from the results of the old code: the old code preferred using
"raw" mode to a compatibility mode, whereas the new code prefers a
compatibility mode if available. Using compatibility mode preferentially
means that we're more likely to be able to migrate the guest to a similar
but not identical host.
Signed-off-by: David Gibson <address@hidden>
Commit: f6f242c7578fbedcdb53a14d4b057a7059b8dd1d
https://github.com/qemu/qemu/commit/f6f242c7578fbedcdb53a14d4b057a7059b8dd1d
Author: David Gibson <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/spapr_hcall.c
M target/ppc/compat.c
M target/ppc/cpu.h
Log Message:
-----------
ppc: Add ppc_set_compat_all()
Once a compatiblity mode is negotiated with the guest,
h_client_architecture_support() uses run_on_cpu() to update each CPU to
the new mode. We're going to want this logic somewhere else shortly,
so make a helper function to do this global update.
We put it in target-ppc/compat.c - it makes as much sense at the CPU level
as it does at the machine level. We also move the cpu_synchronize_state()
into ppc_set_compat(), since it doesn't really make any sense to call that
without synchronizing state.
Signed-off-by: David Gibson <address@hidden>
Commit: 07bdd2478b56b035c270404fe3f84e3da1f8682a
https://github.com/qemu/qemu/commit/07bdd2478b56b035c270404fe3f84e3da1f8682a
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/internal.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xsaddqp instructions
xsaddqp: VSX Scalar Add Quad-Precision
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e548780359818debcd10e9d8b6be1abe17c885c0
https://github.com/qemu/qemu/commit/e548780359818debcd10e9d8b6be1abe17c885c0
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xscvdpqp instruction
xscvdpqp: VSX Scalar Convert Double-Precision format to
Quad-Precision format
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2a084dadcbc207b27d3efc9d6c05cafb72fc83f0
https://github.com/qemu/qemu/commit/2a084dadcbc207b27d3efc9d6c05cafb72fc83f0
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xscvqpdp instruction
xscvqpdp: VSX Scalar round & Convert Quad-Precision format to
Double-Precision format
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 0dfe952dc5c2921488a1172407857d5bb81d17a4
https://github.com/qemu/qemu/commit/0dfe952dc5c2921488a1172407857d5bb81d17a4
Author: Roman Kapl <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/ppc_booke.c
Log Message:
-----------
ppc: Prevent inifnite loop in decrementer auto-reload.
If the DECAR register is set to 0, QEMU tries to reload the decrementer with
zero in an inifinite loop. According to PPC documentation, the decrementer is
triggered on 1->0 transition, so avoid reloading the decrementer if if is
already zero.
The problem does not manifest under Linux, but it is valid to set DECAR to zero
(and may make sense as part of decrementer initialization when interrupts are
disabled).
Signed-off-by: Roman Kapl <address@hidden>
[dwg: Fixed style nit]
Signed-off-by: David Gibson <address@hidden>
Commit: 365206aeb3d0bb72043d157088a0ebcfaad851f7
https://github.com/qemu/qemu/commit/365206aeb3d0bb72043d157088a0ebcfaad851f7
Author: Jose Ricardo Ziviani <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/int_helper.c
Log Message:
-----------
ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macro
This commit fixes a warning in the code "(i * 2) ? .. : ..", which
should be better as "i ? .. : ..", and improves the BCD_DIG_BYTE
macro by placing parentheses around its argument to avoid possible
expansion issues like: BCD_DIG_BYTE(i + j).
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Reviewed-by: Eric Blake <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c3e4293ac9fcd62d2720b10bb7d1a96805d94fed
https://github.com/qemu/qemu/commit/c3e4293ac9fcd62d2720b10bb7d1a96805d94fed
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target-ppc: xscvqpdp zero VSR
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5d51eaea84899d88cb161fab3f089168e3812e9e
https://github.com/qemu/qemu/commit/5d51eaea84899d88cb161fab3f089168e3812e9e
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M fpu/softfloat-specialize.h
Log Message:
-----------
softfloat: Fix the default qNAN for target-ppc
Currently float128_default_nan() returns 0xFFFF800000000000 in the
higher double word, but it should return 0x7FFF800000000000 which
is the correct higher double word for default qNAN on PowerPC.
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 6758c192b063515b5c7bd2b0086217825c5b6d00
https://github.com/qemu/qemu/commit/6758c192b063515b5c7bd2b0086217825c5b6d00
Author: Jose Ricardo Ziviani <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M util/Makefile.objs
M util/host-utils.c
Log Message:
-----------
host-utils: Move 128-bit guard macro to .c file
It is not possible to implement functions in host-utils.c for
architectures with quadwords because the guard is implemented in the
Makefile. This patch move the guard out of the Makefile to the
implementation file.
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Reviewed-by: Eric Blake <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f539fbe33753fb1549e28c56225d0ab7a8cb0669
https://github.com/qemu/qemu/commit/f539fbe33753fb1549e28c56225d0ab7a8cb0669
Author: Jose Ricardo Ziviani <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M include/qemu/host-utils.h
M tests/.gitignore
M tests/Makefile.include
A tests/test-shift128.c
M util/host-utils.c
Log Message:
-----------
host-utils: Implement unsigned quadword left/right shift and unit tests
Implements 128-bit left shift and right shift as well as their
testcases. By design, shift silently mods by 128, so the caller is
responsible to assert the shift range if necessary.
Left shift sets the overflow flag if any non-zero digit is shifted out.
Examples:
ulshift(&low, &high, 250, &overflow);
equivalent: n << 122
urshift(&low, &high, -2);
equivalent: n << 126
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Reviewed-by: Eric Blake <address@hidden>
[dwg: Added test-shift128 to .gitignore]
Signed-off-by: David Gibson <address@hidden>
Commit: e04797f79e48b5410457ec093249676585361de0
https://github.com/qemu/qemu/commit/e04797f79e48b5410457ec093249676585361de0
Author: Jose Ricardo Ziviani <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.inc.c
M target/ppc/translate/vmx-ops.inc.c
Log Message:
-----------
ppc: Implement bcds. instruction
bcds.: Decimal shift. Given two registers vra and vrb, this instruction
shift the vrb value by vra bits into the result register.
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a49a95e9e4dc2652cdc8a1e4fb1bfb66dba2e1d8
https://github.com/qemu/qemu/commit/a49a95e9e4dc2652cdc8a1e4fb1bfb66dba2e1d8
Author: Jose Ricardo Ziviani <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.inc.c
M target/ppc/translate/vmx-ops.inc.c
Log Message:
-----------
ppc: Implement bcdus. instruction
bcdus.: Decimal unsigned shift. This instruction works like bcds. but
considers only unsigned BCDs (no sign in least meaning 4 bits).
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a54238adac8e6fc4ba8bffe8299216b73ef3d3ee
https://github.com/qemu/qemu/commit/a54238adac8e6fc4ba8bffe8299216b73ef3d3ee
Author: Jose Ricardo Ziviani <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.inc.c
M target/ppc/translate/vmx-ops.inc.c
Log Message:
-----------
ppc: Implement bcdsr. instruction
bcdsr.: Decimal shift and round. This instruction works like bcds.
however, when performing right shift, 1 will be added to the
result if the last digit was >= 5.
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1b8d663d620888b537020cd55890af5f4bbc41b8
https://github.com/qemu/qemu/commit/1b8d663d620888b537020cd55890af5f4bbc41b8
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xsiexpdp instruction
xsiexpdp: VSX Scalar Insert Exponent Double Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 8a9472ec389d6b47e7a0746b0c97b8073f6379be
https://github.com/qemu/qemu/commit/8a9472ec389d6b47e7a0746b0c97b8073f6379be
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xsiexpqp instruction
xsiexpqp: VSX Scalar Insert Exponent Quad Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d9031405a782d97c3c64be62bad90c7c44eae002
https://github.com/qemu/qemu/commit/d9031405a782d97c3c64be62bad90c7c44eae002
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xviexpsp instruction
xviexpsp: VSX Vector Insert Exponent Single Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e385e4b7dba4e62a4fd3dcf8d41a80d8b6a81c11
https://github.com/qemu/qemu/commit/e385e4b7dba4e62a4fd3dcf8d41a80d8b6a81c11
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xviexpdp instruction
xviexpdp: VSX Vector Insert Exponent Dual Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 08f1ee5a09a9afb912932d31b546a1faca4ddd35
https://github.com/qemu/qemu/commit/08f1ee5a09a9afb912932d31b546a1faca4ddd35
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xvxexpsp instruction
xvxexpsp: VSX Vector Extract Exponent Single Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 46804e2875e24d03c563a6ba6c59ee009a07816a
https://github.com/qemu/qemu/commit/46804e2875e24d03c563a6ba6c59ee009a07816a
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xvxexpdp instruction
xvxexpdp: VSX Vector Extract Exponent Dual Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c5969d2eb17103d6c38c2d244d33ed2404210cd9
https://github.com/qemu/qemu/commit/c5969d2eb17103d6c38c2d244d33ed2404210cd9
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xvxsigsp instruction
xvxsigsp: VSX Vector Extract Significand Single Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: cf9465a166acfca7ca30b720ca60a6634779910a
https://github.com/qemu/qemu/commit/cf9465a166acfca7ca30b720ca60a6634779910a
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xvxsigdp instruction
xvxsigdp: VSX Vector Extract Significand Dual Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 05590b925236c6366c4ac61f1ac3d9d7e853b4e2
https://github.com/qemu/qemu/commit/05590b925236c6366c4ac61f1ac3d9d7e853b4e2
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xscvqps[d,w]z instructions
xscvqpsdz: VSX Scalar truncate & Convert Quad-Precision format to
Signed Doubleword format
xscvqpswz: VSX Scalar truncate & Convert Quad-Precision format to
Signed Word format
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 8178e89cbc0711d690bbd5b049b1f36212bd5088
https://github.com/qemu/qemu/commit/8178e89cbc0711d690bbd5b049b1f36212bd5088
Author: Hervé Poussineau <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M MAINTAINERS
Log Message:
-----------
ppc/prep: update MAINTAINERS file
Signed-off-by: Hervé Poussineau <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 31bc4d114af6030a2ea9de8051f7edf28b4d4291
https://github.com/qemu/qemu/commit/31bc4d114af6030a2ea9de8051f7edf28b4d4291
Author: Jose Ricardo Ziviani <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.inc.c
M target/ppc/translate/vmx-ops.inc.c
Log Message:
-----------
ppc: Implement bcdtrunc. instruction
bcdtrunc.: Decimal integer truncate. Given a BCD number in vrb and the
number of bytes to truncate in vra, the return register will have vrb
with such bits truncated.
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5c32e2e4a077c1258f74c06cd3d3e7e9550dddbb
https://github.com/qemu/qemu/commit/5c32e2e4a077c1258f74c06cd3d3e7e9550dddbb
Author: Jose Ricardo Ziviani <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.inc.c
M target/ppc/translate/vmx-ops.inc.c
Log Message:
-----------
ppc: Implement bcdutrunc. instruction
bcdutrunc. Decimal unsigned truncate. Works like bcdtrunc. with
unsigned BCD numbers.
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c6d8c5ba5a12660559e036caa1f46a7d988c579b
https://github.com/qemu/qemu/commit/c6d8c5ba5a12660559e036caa1f46a7d988c579b
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target-ppc: Use ppc_vsr_t.f128 in xscmp[o,u,exp]qp
xscmpoqp, xscmpuqp & xscmpexpqp were added before f128 field was
introduced in ppc_vsr_t. Now that we have it, use it instead of
generating the 128 bit float using two 64bit fields.
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 48ef23cb265715cd39cba30fcc5a7e98cd09f5d7
https://github.com/qemu/qemu/commit/48ef23cb265715cd39cba30fcc5a7e98cd09f5d7
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xscvsdqp and xscvudqp instructions
xscvsdqp: VSX Scalar Convert Signed Doubleword format to
Quad-Precision format
xscvudqp: VSX Scalar Convert Unsigned Doubleword format to
Quad-Precision format
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 314c1163474f61bf7fce96e8c1cc1e7e73c5a6b3
https://github.com/qemu/qemu/commit/314c1163474f61bf7fce96e8c1cc1e7e73c5a6b3
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xsdivqp instruction
xsdivqp: VSX Scalar Divide Quad-Precision
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a811ec0491fb82797114627ac8018e3edacf7dfe
https://github.com/qemu/qemu/commit/a811ec0491fb82797114627ac8018e3edacf7dfe
Author: Bharata B Rao <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xsmulqp instruction
xsmulqp: VSX Scalar Multiply Quad-Precision
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 8b920d8abccc7c7cbd780d1c5a6d249177aea786
https://github.com/qemu/qemu/commit/8b920d8abccc7c7cbd780d1c5a6d249177aea786
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xvcv[hpsp, sphp] instructions
xvcvhpsp: VSX Vector Convert Half Precision to Single Precision
xvcvsphp: VSX Vector Convert Single Precision to Half Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c104949f64676a528347146027b5f71c4a2415c0
https://github.com/qemu/qemu/commit/c104949f64676a528347146027b5f71c4a2415c0
Author: Suraj Jitindar Singh <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/cpu-models.h
Log Message:
-----------
powerpc/cpu-models: rename ISAv3.00 logical PVR definition
This logical PVR value now corresponds to ISA version 3.00 so rename it
accordingly.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 216c944eebdcbc428beecd3b5aa53d4c5b81d682
https://github.com/qemu/qemu/commit/216c944eebdcbc428beecd3b5aa53d4c5b81d682
Author: Suraj Jitindar Singh <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/cpu.h
M target/ppc/translate_init.c
Log Message:
-----------
target/ppc: Add pcr_supported to POWER9 cpu class definition
pcr_supported is used to define the supported PCR values for a given
processor. A POWER9 processor can support 3.00, 2.07, 2.06 and 2.05
compatibility modes, thus we set this accordingly.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d9d6e78ea82b16a44fca0adf642ca5d5dad429d0
https://github.com/qemu/qemu/commit/d9d6e78ea82b16a44fca0adf642ca5d5dad429d0
Author: Thomas Huth <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/ppc.c
Log Message:
-----------
ppc: Remove unused function cpu_ppc601_rtc_init()
It is completely unused, thus it can be removed without problems.
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 42043e4f1241eeb77f87f5816b5cf0b6e9583ed7
https://github.com/qemu/qemu/commit/42043e4f1241eeb77f87f5816b5cf0b6e9583ed7
Author: Laurent Vivier <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/ppc.c
M hw/ppc/spapr.c
M target/ppc/cpu-qom.h
Log Message:
-----------
spapr: clock should count only if vm is running
This is a port to ppc of the i386 commit:
00f4d64 kvmclock: clock should count only if vm is running
We remove timebase_post_load function, and use the VM state
change handler to save and restore the guest_timebase (on stop
and continue).
We keep timebase_pre_save to reduce the clock difference on
migration like in:
6053a86 kvmclock: reduce kvmclock difference on migration
Time base offset has originally been introduced by commit
98a8b52 spapr: Add support for time base offset migration
So while VM is paused, the time is stopped. This allows to have
the same result with date (based on Time Base Register) and
hwclock (based on "get-time-of-day" RTAS call).
Moreover in TCG mode, the Time Base is always paused, so this
patch also adjust the behavior between TCG and KVM.
VM state field "time_of_the_day_ns" is now useless but we keep
it to be able to migrate to older version of the machine.
As vmstate_ppc_timebase structure (with timebase_pre_save() and
timebase_post_load() functions) was only used by vmstate_spapr,
we register the VM state change handler only in ppc_spapr_init().
Signed-off-by: Laurent Vivier <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 6a07692ffad3ee2e566c4494f7d5e88a8bdae9a6
https://github.com/qemu/qemu/commit/6a07692ffad3ee2e566c4494f7d5e88a8bdae9a6
Author: Thomas Huth <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/translate_init.c
Log Message:
-----------
target/ppc: Remove unused POWERPC_FAMILY(POWER)
We do not support POWER1 CPUs in QEMU, so it does not make sense
to keep this stub around.
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c636367311e892a9c5b93eaf53f59091729266e7
https://github.com/qemu/qemu/commit/c636367311e892a9c5b93eaf53f59091729266e7
Author: Thomas Huth <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M target/ppc/cpu-models.c
Log Message:
-----------
target/ppc/cpu-models: Fix/remove bad CPU aliases
There is no CPU model called "7447_v1.2" in our list, so the
"7447" alias should point to "7447_v1.1" instead. Let's also
remove the "codename" aliases that point to non-implemented
CPU models - they are really of no use here.
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 25e6a11832bcd0715068f0cc24fb46ec03de676e
https://github.com/qemu/qemu/commit/25e6a11832bcd0715068f0cc24fb46ec03de676e
Author: Michael S. Tsirkin <address@hidden>
Date: 2017-01-31 (Tue, 31 Jan 2017)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
ppc: switch to constants within BUILD_BUG_ON
We are switching BUILD_BUG_ON to verify that it's parameter is a
compile-time constant, and it turns out that some gcc versions
(specifically gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609) are
not smart enough to figure it out for expressions involving local
variables. This is harmless but means that the check is ineffective for
these platforms. To fix, replace the variable with macros.
Reported-by: Peter Maydell <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
[dwg: Correct a printf format warning]
Signed-off-by: David Gibson <address@hidden>
Commit: 00469dc3731e3d08536cd119c14dbdf149fed3e4
https://github.com/qemu/qemu/commit/00469dc3731e3d08536cd119c14dbdf149fed3e4
Author: Valentin Plotkin <address@hidden>
Date: 2017-02-02 (Thu, 02 Feb 2017)
Changed paths:
M hw/ppc/e500.c
M hw/ppc/ppc440_bamboo.c
M hw/ppc/virtex_ml507.c
Log Message:
-----------
target-ppc: Add MMU model check for booke machines
Machines bamboo, e500 and virtex-ml507 assume a certain MMU model,
otherwise resulting in unpredictable behavior. Add apropriate checks
into *_init functions.
Signed-off-by: Valentin Plotkin <address@hidden>
[regarding virtex parts]
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 403a884a40d009cc70d1471209166c6e00f57d03
https://github.com/qemu/qemu/commit/403a884a40d009cc70d1471209166c6e00f57d03
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-02-02 (Thu, 02 Feb 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/internal.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xvtstdc[sp,dp] instructions
xvtstdcsp: VSX Vector Test Data Class Single-Precision
xvtstdcdp: VSX Vector Test Data Class Double-Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 78241762c483c9bb7a4834a6d1e6db512bb6a744
https://github.com/qemu/qemu/commit/78241762c483c9bb7a4834a6d1e6db512bb6a744
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-02-02 (Thu, 02 Feb 2017)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/internal.h
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xststdc[sp, dp, qp] instructions
xststdcsp: VSX Scalar Test Data Class Single-Precision
xststdcdp: VSX Scalar Test Data Class Double-Precision
xststdcqp: VSX Scalar Test Data Class Quad-Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d801a61e9803593cf95ed3aeeb175c32c8acea95
https://github.com/qemu/qemu/commit/d801a61e9803593cf95ed3aeeb175c32c8acea95
Author: Suraj Jitindar Singh <address@hidden>
Date: 2017-02-02 (Thu, 02 Feb 2017)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc/debug: Print LPCR register value if register exists
It can be useful when debugging to print the LPCR value.
Thus we add the LPCR to the "info registers" output if the register had
been defined.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b8b4576e090d646be6a8f3f6a2465abc27a69aa5
https://github.com/qemu/qemu/commit/b8b4576e090d646be6a8f3f6a2465abc27a69aa5
Author: Suraj Jitindar Singh <address@hidden>
Date: 2017-02-02 (Thu, 02 Feb 2017)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
tcg/POWER9: NOOP the cp_abort instruction
The cp_abort instruction is used to remove the state of an in progress
copy paste sequence. POWER9 compilers add this in various places, such
as context switches which causes illegal instruction signals since we
don't yet implement this instruction.
Given there is no implementation of the copy paste facility and that we
don't claim to support it, we can just noop this instruction.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 76134d48b3a526ec5f5dec15630c51559577b2bf
https://github.com/qemu/qemu/commit/76134d48b3a526ec5f5dec15630c51559577b2bf
Author: Suraj Jitindar Singh <address@hidden>
Date: 2017-02-02 (Thu, 02 Feb 2017)
Changed paths:
M target/ppc/mmu-hash64.c
Log Message:
-----------
target/ppc/mmu_hash64: Fix printing unsigned as signed int
We were printing an unsigned value as a signed value, fix this.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 6925f12f4f02e55c73e738cb9e91e8cda2f23358
https://github.com/qemu/qemu/commit/6925f12f4f02e55c73e738cb9e91e8cda2f23358
Author: Suraj Jitindar Singh <address@hidden>
Date: 2017-02-02 (Thu, 02 Feb 2017)
Changed paths:
M target/ppc/mmu-hash64.h
Log Message:
-----------
target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation
We are calculating the authority mask register key value wrong.
The pte entry contains the key value with the two upper bits and the three
lower bits stored separately. We should use these two portions to get a 5
bit value, not or them together which will only give us a 3 bit value.
Fix this.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 715d4b96a444717ec1e5c3b10293b0315700b210
https://github.com/qemu/qemu/commit/715d4b96a444717ec1e5c3b10293b0315700b210
Author: Thomas Huth <address@hidden>
Date: 2017-02-02 (Thu, 02 Feb 2017)
Changed paths:
M target/ppc/kvm.c
Log Message:
-----------
ppc/kvm: Handle the "family" CPU via alias instead of registering new types
When running with KVM on POWER, we are registering a "family" CPU
type for the host CPU that we are running on. For example, on all
POWER8-compatible hosts, we register a "POWER8" CPU type, so that
you can always start QEMU with "-cpu POWER8" there, without the
need to know whether you are running on a POWER8, POWER8E or POWER8NVL
host machine.
However, we also have a "POWER8" CPU alias in the ppc_cpu_aliases list
(that is mainly useful for TCG). This leads to two cosmetical drawbacks:
If the user runs QEMU with "-cpu ?", we always claim that POWER8 is an
"alias for POWER8_v2.0" - which is simply not true when running with
KVM on POWER. And when using the 'query-cpu-definitions' QMP call,
there are currently two entries for "POWER8", one for the alias, and
one for the additional registered type.
To solve the two problems, we should rather update the "family" alias
instead of registering a new types. We then only have one "POWER8"
CPU definition around, an alias, which also points to the right
destination.
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1396536
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 7c6e8797337c24520b48d8b50a900a747e50f974
https://github.com/qemu/qemu/commit/7c6e8797337c24520b48d8b50a900a747e50f974
Author: Thomas Huth <address@hidden>
Date: 2017-02-02 (Thu, 02 Feb 2017)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
hw/ppc/pnv: Use error_report instead of hw_error if a ROM file can't be found
hw_error() is for CPU related errors only (it dumps the CPU registers
and calls abort()!), so using error_report() is the better choice
of reporting an error in case we simply did not find a file.
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5459ef3bff961bc462ac89460ab6b08a14624c8d
https://github.com/qemu/qemu/commit/5459ef3bff961bc462ac89460ab6b08a14624c8d
Author: Peter Maydell <address@hidden>
Date: 2017-02-02 (Thu, 02 Feb 2017)
Changed paths:
M MAINTAINERS
M default-configs/i386-softmmu.mak
M default-configs/ppc-softmmu.mak
M default-configs/ppc64-softmmu.mak
M default-configs/x86_64-softmmu.mak
M disas/ppc.c
M fpu/softfloat-specialize.h
M hw/gpio/mpc8xxx.c
M hw/pci-bridge/Makefile.objs
M hw/ppc/Makefile.objs
M hw/ppc/e500.c
M hw/ppc/pnv.c
M hw/ppc/ppc.c
M hw/ppc/ppc440_bamboo.c
M hw/ppc/ppc_booke.c
M hw/ppc/ppce500_spin.c
M hw/ppc/prep.c
A hw/ppc/prep_systemio.c
A hw/ppc/rs6000_mc.c
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_vio.c
M hw/ppc/trace-events
M hw/ppc/virtex_ml507.c
M hw/usb/host-libusb.c
M hw/usb/host-stub.c
M include/fpu/softfloat.h
M include/hw/ppc/spapr.h
M include/hw/usb.h
M include/qemu/host-utils.h
M target/ppc/Makefile.objs
A target/ppc/compat.c
M target/ppc/cpu-models.c
M target/ppc/cpu-models.h
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/excp_helper.c
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/internal.h
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
M target/ppc/mem_helper.c
M target/ppc/mmu-hash64.c
M target/ppc/mmu-hash64.h
M target/ppc/translate.c
M target/ppc/translate/fp-impl.inc.c
M target/ppc/translate/fp-ops.inc.c
M target/ppc/translate/vmx-impl.inc.c
M target/ppc/translate/vmx-ops.inc.c
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate/vsx-ops.inc.c
M target/ppc/translate_init.c
M tests/.gitignore
M tests/Makefile.include
M tests/display-vga-test.c
M tests/ivshmem-test.c
M tests/libqos/pci-spapr.c
A tests/test-shift128.c
M util/Makefile.objs
M util/host-utils.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170202' into
staging
ppc patch queue 2017-02-02
This obsoletes ppc-for-2.9-20170112, which had a MacOS build bug.
This is a long overdue ppc pull request for qemu-2.9. It's been a
long time coming due to some holidays and inconveniently timed
problems with testing. So, there's a lot in here:
* More POWER9 instruction implementations for TCG
* The simpler parts of my CPU compatibility mode cleanup
* This changes behaviour to prefer compatibility modes over
"raW" mode for new machine type versions
* New "40p" machine type which is essentially a modernized and
cleaned up "prep". The intention is that it will replace "prep"
once it has some more testing and polish.
* Add pseries-2.9 machine type
* Implement H_SIGNAL_SYS_RESET hypercall
* Consolidate the two alternate CPU init paths in pseries by
making it always go through CPU core objects to initialize CPU
* A number of bugfixes and cleanups
* Stop the guest timebase when the guest is stopped under KVM.
This makes the guest system clock also stop when paused, which
matches the x86 behaviour.
* Some preliminary cleanups leading towards implementation of the
POWER9 MMU.
There are also some changes not strictly related to ppc code, but for
its benefit:
* Limit the pxi-expander-bridge (PXB) device to x86 guests only
(it's essentially a hack to work around historical x86
limitations)
* Some additions to the 128-bit math in host_utils, necessary for
some of the new instructions.
* Revise a number of qtests and enable them for ppc
# gpg: Signature made Thu 02 Feb 2017 01:40:16 GMT
# gpg: using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg: aka "David Gibson (Red Hat) <address@hidden>"
# gpg: aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg: aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.9-20170202: (107 commits)
hw/ppc/pnv: Use error_report instead of hw_error if a ROM file can't be found
ppc/kvm: Handle the "family" CPU via alias instead of registering new types
target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation
target/ppc/mmu_hash64: Fix printing unsigned as signed int
tcg/POWER9: NOOP the cp_abort instruction
target/ppc/debug: Print LPCR register value if register exists
target-ppc: Add xststdc[sp, dp, qp] instructions
target-ppc: Add xvtstdc[sp,dp] instructions
target-ppc: Add MMU model check for booke machines
ppc: switch to constants within BUILD_BUG_ON
target/ppc/cpu-models: Fix/remove bad CPU aliases
target/ppc: Remove unused POWERPC_FAMILY(POWER)
spapr: clock should count only if vm is running
ppc: Remove unused function cpu_ppc601_rtc_init()
target/ppc: Add pcr_supported to POWER9 cpu class definition
powerpc/cpu-models: rename ISAv3.00 logical PVR definition
target-ppc: Add xvcv[hpsp, sphp] instructions
target-ppc: Add xsmulqp instruction
target-ppc: Add xsdivqp instruction
target-ppc: Add xscvsdqp and xscvudqp instructions
...
# Conflicts:
# hw/pci-bridge/Makefile.objs
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/4e9f5244e194...5459ef3bff96
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