[Qemu-commits] [qemu/qemu] ac2810: aspeed/smc: handle dummy bytes when doing fast rea...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: ac2810defa9d4ba856adbaa9c899defecd8585de
      
https://github.com/qemu/qemu/commit/ac2810defa9d4ba856adbaa9c899defecd8585de
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: handle dummy bytes when doing fast reads in command mode

When doing fast read, a certain amount of dummy bytes should be sent
before the read. This number is configurable in the controler CE0
Control Register and needs to be modeled using fake transfers to the
flash module.

This only supports command mode. User mode requires more work and a
possible extension of the m25p80 device model.

Signed-off-by: Cédric Le Goater <address@hidden>
Acked-by: Marcin Krzemiński <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 58117c9bb429cd9552d998687aa99088eb1d8528
      
https://github.com/qemu/qemu/commit/58117c9bb429cd9552d998687aa99088eb1d8528
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  armv7m: MRS/MSR: handle unprivileged access

The MRS and MSR instruction handling has a number of flaws:
 * unprivileged accesses should only be able to read
   CONTROL and the xPSR subfields, and only write APSR
   (others RAZ/WI)
 * privileged access should not be able to write xPSR
   subfields other than APSR
 * accesses to unimplemented registers should log as
   guest errors, not abort QEMU

Signed-off-by: Michael Davidsaver <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: rewrote commit message]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 542b3478a00cb7ef51c259255b3ab1e2a7daada2
      
https://github.com/qemu/qemu/commit/542b3478a00cb7ef51c259255b3ab1e2a7daada2
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M hw/arm/armv7m.c
    M target/arm/cpu.c
    M target/arm/translate.c

  Log Message:
  -----------
  armv7m: Replace armv7m.hack with unassigned_access handler

For v7m we need to catch attempts to execute from special
addresses at 0xfffffff0 and above. Previously we did this
with the aid of a hacky special purpose lump of memory
in the address space and a check in translate.c for whether
we were translating code at those addresses.

We can implement this more cleanly using a CPU
unassigned access handler which throws the exception
if the unassigned access is for one of the special addresses.

Signed-off-by: Michael Davidsaver <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
[PMM:
 * drop the deletion of the "don't interrupt if PC is magic"
   code in arm_v7m_cpu_exec_interrupt() -- this is still
   required
 * don't generate an exception for unassigned accesses
   which aren't to the magic address -- although doing
   this is in theory correct in practice it will break
   currently working guests which rely on the RAZ/WI
   behaviour when they touch devices which we haven't
   modelled.
 * trigger EXCP_EXCEPTION_EXIT on is_exec, not !is_write
]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1b9ea408fca1ce8caae67b792355b023c69c5ac5
      
https://github.com/qemu/qemu/commit/1b9ea408fca1ce8caae67b792355b023c69c5ac5
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  armv7m: Explicit error for bad vector table

Give an explicit error and abort when a load
from the vector table fails. Architecturally this
should HardFault (which will then immediately
fail to load the HardFault vector and go into Lockup).
Since we don't model Lockup, just report this guest
error via cpu_abort(). This is more helpful than the
previous behaviour of reading a zero, which is the
address of the reset stack pointer and not a sensible
location to jump to.

Signed-off-by: Michael Davidsaver <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
[PMM: expanded commit message]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: afb3141c660f3dca38227901c5c62cef7af86647
      
https://github.com/qemu/qemu/commit/afb3141c660f3dca38227901c5c62cef7af86647
  Author: Peter Maydell <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M include/hw/register.h
    A include/hw/registerfields.h

  Log Message:
  -----------
  hw/registerfields.h: Pull FIELD etc macros out of hw/register.h

hw/register.h provides macros like FIELD which make it easy to define
shift, mask and length constants for the fields within a register.
Unfortunately register.h also includes a lot of other things, some
of which will only compile in the softmmu build.

Pull the FIELD macro and friends out into a separate header file,
so they can be used in places like target/arm files which also
get built in the user-only configs.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: abc24d86cc0364f402e438fae3acb14289b40734
      
https://github.com/qemu/qemu/commit/abc24d86cc0364f402e438fae3acb14289b40734
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/machine.c

  Log Message:
  -----------
  armv7m: Fix reads of CONTROL register bit 1

The v7m CONTROL register bit 1 is SPSEL, which indicates
the stack being used. We were storing this information
not in v7m.control but in the separate v7m.other_sp
structure field. Unfortunately, the code handling reads
of the CONTROL register didn't take account of this, and
so if SPSEL was updated by an exception entry or exit then
a subsequent guest read of CONTROL would get the wrong value.

Using a separate structure field doesn't really gain us
anything in efficiency, so drop this unnecessary complexity
in favour of simply storing all the bits in v7m.control.

This is a migration compatibility break for M profile
CPUs only.

Signed-off-by: Michael Davidsaver <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
[PMM: rewrote commit message;
 use deposit32(); use FIELD to define constants for
 masking and shifting of CONTROL register fields
]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a20ee6005564590d33eabec11ed4dc7c432db36b
      
https://github.com/qemu/qemu/commit/a20ee6005564590d33eabec11ed4dc7c432db36b
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  armv7m: Clear FAULTMASK on return from non-NMI exceptions

FAULTMASK must be cleared on return from all
exceptions other than NMI.

Signed-off-by: Michael Davidsaver <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: feb0b1aa11f14ee71660aba46b46387d1f923c9e
      
https://github.com/qemu/qemu/commit/feb0b1aa11f14ee71660aba46b46387d1f923c9e
  Author: Peter Maydell <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M hw/block/pflash_cfi01.c
    M include/hw/compat.h

  Log Message:
  -----------
  pflash_cfi01: fix per-device sector length in CFI table

For configurations of the pflash_cfi01 device which set it up with a
device-width not equal to the width (ie where we are emulating
multiple narrow flash devices wired up in parallel), we were giving
incorrect values in the CFI data table:

(1) the sector length entry should specify the sector length for a
    single device, not the length for the overall collection of
    devices
(2) the number of blocks per device must not be divided by the
    number of devices because the resulting device size would not
    match the overall size
(3) this then means that the overall write block size must be
    modified depending on the number of devices because the entry is
    per device and when the guest writes into the flash it
    calculates the write size by using the CFI entry (write size
    per device) multiplied by the number of chips.
    (It would alternatively be possible to modify the write
    block size in the CFI table (currently hardcoded at 2048) and
    leave the overall write block size alone.)

This commit corrects these bugs, and adds a hw-compat property
to retain the old behaviour on 2.8 and earlier versions. (The
only board we have which uses this sort of flash config and
has machine versioning is the "virt" board -- the PC uses a
single flash device and so behaviour is unaffected whether
using old-multiple-chip-handling or not.)

Here is a configuration example from the vexpress board:

VEXPRESS_FLASH_SIZE = 64M
VEXPRESS_FLASH_SECT_SIZE 256K
num-blocks = VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE = 256
sector-length = 256K
width = 4
device-width = 2

The code will fill the CFI entry with the following entries:
  num-blocks = 256
  sector-length = 128K
  writeblock_size = 2048

This results in two chips, each with 256 * 128K = 32M device size and
a write block size of 2048.

A sector erase will be sent to both chips, thus 256K must be erased.
When the guest sends a block write command, it will write 4096 bytes
data at once (2048 per device).

Signed-off-by: David Engraf <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
[PMM: cleaned up and expanded commit message]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 531c60a97ab51618b4b9ccef1c5fe00607079706
      
https://github.com/qemu/qemu/commit/531c60a97ab51618b4b9ccef1c5fe00607079706
  Author: Peter Maydell <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Drop IS_M() macro

We only use the IS_M() macro in two places, and it's a bit of a
namespace grab to put in cpu.h.  Drop it in favour of just explicitly
calling arm_feature() in the places where it was used.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: d713ea6c464918f87d1dd480520dd4aedb685d9a
      
https://github.com/qemu/qemu/commit/d713ea6c464918f87d1dd480520dd4aedb685d9a
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  armv7m_nvic: keep a pointer to the CPU

Many NVIC operations access the CPU state, so store a pointer in
struct nvic_state rather than fetching it via qemu_get_cpu() every
time we need it.

As with the arm_gicv3_common code, we currently just call
qemu_get_cpu() in the NVIC's realize method, but in future we might
want to use a QOM property to pass the CPU to the NVIC.

This imposes an ordering requirement that the CPU is
realized before the NVIC, but that is always true since
both are dealt with in armv7m_init().

Signed-off-by: Michael Davidsaver <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
[PMM: Use qemu_get_cpu(0) rather than first_cpu; expand
 commit message]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2c4da50d9477fb830d778bb5d6a11215aa359b44
      
https://github.com/qemu/qemu/commit/2c4da50d9477fb830d778bb5d6a11215aa359b44
  Author: Peter Maydell <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/machine.c

  Log Message:
  -----------
  armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR

Add the structure fields, VMState fields, reset code and macros for
the v7M system control registers CCR, CFSR, HFSR, DFSR, MMFAR and
BFAR.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: e6b332097d1a4713173a82f17d039b4c78bc6f59
      
https://github.com/qemu/qemu/commit/e6b332097d1a4713173a82f17d039b4c78bc6f59
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR

Implement the v7M system registers CCR, CFSR, HFSR, DFSR, BFAR and
MMFAR.  For the moment these simply read as written (with some basic
handling of RAZ/WI bits and W1C semantics).

Signed-off-by: Michael Davidsaver <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
[PMM: drop warning about setting unimplemented CCR bits;
 tweak commit message; add DFSR]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dc858c6633a9af8b80c1509cf6f825e4390d3ad1
      
https://github.com/qemu/qemu/commit/dc858c6633a9af8b80c1509cf6f825e4390d3ad1
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  armv7m: honour CCR.STACKALIGN on exception entry

The CCR.STACKALIGN bit controls whether the CPU is supposed to force
8-alignment of the stack pointer on entry to the exception handler.

Signed-off-by: Michael Davidsaver <address@hidden>
Message-id: address@hidden
[PMM: commit message and comment tweaks]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 81dd9648c69bb89afdd6f4bb3ed6f3efdac96524
      
https://github.com/qemu/qemu/commit/81dd9648c69bb89afdd6f4bb3ed6f3efdac96524
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  armv7m: set CFSR.UNDEFINSTR on undefined instructions

When we take an exception for an undefined instruction, set the
appropriate CFSR bit.

Signed-off-by: Michael Davidsaver <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
[PMM: tweaked commit message, comment]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7517748e3f71a3099e57915fba95c4c308e6d842
      
https://github.com/qemu/qemu/commit/7517748e3f71a3099e57915fba95c4c308e6d842
  Author: Peter Maydell <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M linux-user/main.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/translate.c

  Log Message:
  -----------
  armv7m: Report no-coprocessor faults correctly

For v7M attempts to access a nonexistent coprocessor are reported
differently from plain undefined instructions (as UsageFaults of type
NOCP rather than type UNDEFINSTR).  Split them out into a new
EXCP_NOCP so we can report the FSR value correctly.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: bdd04fc76a78d61ae0f0e93ce345f9cf2e49a9a8
      
https://github.com/qemu/qemu/commit/bdd04fc76a78d61ae0f0e93ce345f9cf2e49a9a8
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  armv7m: Honour CCR.USERSETMPEND

The CCR.USERSETMPEND bit has to be set to permit unprivileged code to
write to the Software Triggered Interrupt register; honour this bit
rather than letting any code write to the register.

Signed-off-by: Michael Davidsaver <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
[PMM: Tweak commit message, comment, phrasing of condition]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dc7abe4d65ad39390b2db120f5ad18f8f6576f8b
      
https://github.com/qemu/qemu/commit/dc7abe4d65ad39390b2db120f5ad18f8f6576f8b
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  armv7m: FAULTMASK should be 0 on reset

For M profile CPUs, FAULTMASK should be 0 on reset, like PRIMASK.
QEMU stores FAULTMASK in the PSTATE F bit, so (as with PRIMASK in the
I bit) we have to clear these to undo the A profile default of 1.

Update the comment accordingly and move it so that it's closer to the
code it's referring to.

Signed-off-by: Michael Davidsaver <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
[PMM: rewrote commit message, moved comments]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 056f43df9168413f304500b69c33158d66efb7cf
      
https://github.com/qemu/qemu/commit/056f43df9168413f304500b69c33158d66efb7cf
  Author: Peter Maydell <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  armv7m: R14 should reset to 0xffffffff

For M profile (unlike A profile) the reset value of R14 is specified
as 0xffffffff.  (The rationale is that this is an illegal exception
return value, so if guest code tries to return to it it will result
in a helpful exception.)

Registers r0 to r12 and the flags are architecturally UNKNOWN on
reset, so we leave those at zero.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: d05a86285cacdcbfdd97e437d156545666fa5641
      
https://github.com/qemu/qemu/commit/d05a86285cacdcbfdd97e437d156545666fa5641
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M hw/net/stellaris_enet.c

  Log Message:
  -----------
  arm: stellaris: make MII accesses complete immediately

When the guest attempts to start an MII register
access via the MCTL register, clear the START bit,
so that when the guest reads it back the register
transaction will be signalled as having completed.
This avoids the guest spinning as it polls the
START bit waiting for it to clear (which it
previously never would).

The  MII registers themselves still aren't implemented,
but at least we can avoid guests spending quite so much
time busy waiting.

Signed-off-by: Michael Davidsaver <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: expand commit message]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e62694a078f182c822a7b6d3976b1bcc72e78ec2
      
https://github.com/qemu/qemu/commit/e62694a078f182c822a7b6d3976b1bcc72e78ec2
  Author: Peter Maydell <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M hw/char/exynos4210_uart.c

  Log Message:
  -----------
  hw/char/exynos4210_uart: Drop unused local variable frame_size

The frame_size local variable in exynos4210_uart_update_parameters()
is calculated but never used (and has been this way since the
device was introduced in commit e5a4914efc7). The qemu_chr_fe_ioctl()
doesn't need this information (if it really wanted it it could
calculate it from the parity/data_bits/stop_bits), so just drop
the variable entirely.

Fixes: https://bugs.launchpad.net/bugs/1655702

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: d87576e38df760ef1cb635197d51f207e2a8eda9
      
https://github.com/qemu/qemu/commit/d87576e38df760ef1cb635197d51f207e2a8eda9
  Author: Peter Maydell <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M hw/intc/arm_gicv3_cpuif.c

  Log Message:
  -----------
  arm_gicv3: Fix broken logic in ELRSR calculation

Fix a broken expression in the calculation of ELRSR
register bits: instead of "(lr & ICH_LR_EL2_HW) == 1"
we want to check for != 0, because the HW bit is not
bit 0 so a test for == 1 is always false.

Fixes: https://bugs.launchpad.net/bugs/1658506

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Message-id: address@hidden


  Commit: 146871c33eb70ca7090a0a55e69e5a8f9b5eb102
      
https://github.com/qemu/qemu/commit/146871c33eb70ca7090a0a55e69e5a8f9b5eb102
  Author: Prasad J Pandit <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M hw/dma/omap_dma.c

  Log Message:
  -----------
  dma: omap: check dma channel data_type

When setting dma channel 'data_type', if (value & 3) == 3,
the set 'data_type' is said to be bad. This also leads to an
OOB access in 'omap_dma_transfer_generic', while doing
cpu_physical_memory_r/w operations. Add check to avoid it.

Reported-by: Jiang Xin <address@hidden>
Signed-off-by: Prasad J Pandit <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3aca12f841fcd6f3a7477076dad0d564360500de
      
https://github.com/qemu/qemu/commit/3aca12f841fcd6f3a7477076dad0d564360500de
  Author: Peter Maydell <address@hidden>
  Date:   2017-01-27 (Fri, 27 Jan 2017)

  Changed paths:
    M hw/arm/armv7m.c
    M hw/block/pflash_cfi01.c
    M hw/char/exynos4210_uart.c
    M hw/dma/omap_dma.c
    M hw/intc/arm_gicv3_cpuif.c
    M hw/intc/armv7m_nvic.c
    M hw/net/stellaris_enet.c
    M hw/ssi/aspeed_smc.c
    M include/hw/compat.h
    M include/hw/register.h
    A include/hw/registerfields.h
    M linux-user/main.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/machine.c
    M target/arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170127' 
into staging

target-arm queue:
 * various minor M profile bugfixes
 * aspeed/smc: handle dummy bytes when doing fast reads in command mode
 * pflash_cfi01: fix per-device sector length in CFI table
 * arm: stellaris: make MII accesses complete immediately
 * hw/char/exynos4210_uart: Drop unused local variable frame_size
 * arm_gicv3: Fix broken logic in ELRSR calculation
 * dma: omap: check dma channel data_type

# gpg: Signature made Fri 27 Jan 2017 15:29:39 GMT
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170127: (22 commits)
  dma: omap: check dma channel data_type
  arm_gicv3: Fix broken logic in ELRSR calculation
  hw/char/exynos4210_uart: Drop unused local variable frame_size
  arm: stellaris: make MII accesses complete immediately
  armv7m: R14 should reset to 0xffffffff
  armv7m: FAULTMASK should be 0 on reset
  armv7m: Honour CCR.USERSETMPEND
  armv7m: Report no-coprocessor faults correctly
  armv7m: set CFSR.UNDEFINSTR on undefined instructions
  armv7m: honour CCR.STACKALIGN on exception entry
  armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR
  armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR
  armv7m_nvic: keep a pointer to the CPU
  target/arm: Drop IS_M() macro
  pflash_cfi01: fix per-device sector length in CFI table
  armv7m: Clear FAULTMASK on return from non-NMI exceptions
  armv7m: Fix reads of CONTROL register bit 1
  hw/registerfields.h: Pull FIELD etc macros out of hw/register.h
  armv7m: Explicit error for bad vector table
  armv7m: Replace armv7m.hack with unassigned_access handler
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/29ba0cdc1fd1...3aca12f841fc