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[Qemu-commits] [qemu/qemu] 643bb6: arm: Uniquely name imx25 I2C buses.
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[Qemu-commits] [qemu/qemu] 643bb6: arm: Uniquely name imx25 I2C buses. |
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Date: |
Fri, 20 Jan 2017 04:30:04 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 643bb6fca7102e49c156d4ba210d2ec3c160b844
https://github.com/qemu/qemu/commit/643bb6fca7102e49c156d4ba210d2ec3c160b844
Author: Alastair D'Silva <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/arm/imx25_pdk.c
M hw/i2c/imx_i2c.c
Log Message:
-----------
arm: Uniquely name imx25 I2C buses.
The imx25 chip provides 3 i2c buses, but they have all been named
"i2c", which makes it difficult to predict which bus a device will
be connected to when specified on the command line.
This patch addresses the issue by naming the buses uniquely:
i2c-bus.0 i2c-bus.1 i2c-bus.2
Signed-off-by: Alastair D'Silva <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 597c15f0ddadd3e731c8301a4034fe9ce0c846b3
https://github.com/qemu/qemu/commit/597c15f0ddadd3e731c8301a4034fe9ce0c846b3
Author: Marcin Krzeminski <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
block: m25p80: Add Quad Page Program 4byte
Some flash chips have additional page program opcode that
takes only 4 byte address. This commit adds support
for such command in Qemu.
Signed-off-by: Marcin Krzeminski <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f509dfeed31c652a1322643280767323aaf8514a
https://github.com/qemu/qemu/commit/f509dfeed31c652a1322643280767323aaf8514a
Author: Marcin Krzeminski <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
block: m25p80: Introduce die erase command
Modern big flash NOR devices consist of more than one die.
Some of them do not support chip erase and instead have a die
erase command that can erase one die only. This commit adds
support for defining the number of dies in the chip, and adds
support for die erase command.
The NOR flash model is not strict, so no option to
disable chip erase has been added.
Signed-off-by: Marcin Krzeminski <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: eca272138541df23821b3058416e9b672a2f84ac
https://github.com/qemu/qemu/commit/eca272138541df23821b3058416e9b672a2f84ac
Author: Marcin Krzeminski <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
block: m25p80: Improve 1GiB Micron flash definition
n25q00 and mt25q01 devices share the same JEDEC ID. The difference
between those two devices is number of dies and one bit in extended
JEDEC bytes. This commit adds proper entry for both devices by
introduction the number of dies and and new 25q00 entries.
Signed-off-by: Marcin Krzeminski <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 87a4b270348c69a446ebcddc039bfae31b1675cb
https://github.com/qemu/qemu/commit/87a4b270348c69a446ebcddc039bfae31b1675cb
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32()
To run a VM in 32-bit EL1 our AArch32 interrupt handling code
needs to be able to cope with VIRQ and VFIQ exceptions.
These behave like IRQ and FIQ except that we don't need to try
to route them to Monitor mode.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Commit: 4d2ec4da1c2d60c9fd8bad137506870c2f980410
https://github.com/qemu/qemu/commit/4d2ec4da1c2d60c9fd8bad137506870c2f980410
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement DBGVCR32_EL2 system register
The DBGVCR_EL2 system register is needed to run a 32-bit
EL1 guest under a Linux EL2 64-bit hypervisor. Its only
purpose is to provide AArch64 with access to the state of
the DBGVCR AArch32 register. Since we only have a dummy
DBGVCR, implement a corresponding dummy DBGVCR32_EL2.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Commit: eafbafa32f37af6bff3be5500858114d24afd119
https://github.com/qemu/qemu/commit/eafbafa32f37af6bff3be5500858114d24afd119
Author: Cédric Le Goater <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/ssi/aspeed_smc.c
Log Message:
-----------
aspeed/smc: remove call to reset in realize function
This is useless as reset will be called later on.
Signed-off-by: Cédric Le Goater <address@hidden>
Acked-by: Marcin Krzemiński <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 1d247bd0791c83774029ba5a8f29521e2025c302
https://github.com/qemu/qemu/commit/1d247bd0791c83774029ba5a8f29521e2025c302
Author: Cédric Le Goater <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/ssi/aspeed_smc.c
Log Message:
-----------
aspeed/smc: remove call to aspeed_smc_update_cs() in reset function
Instead, we can simply set the irq level when unselecting the slave
devices. This change prepares ground for a subsequent cleanup of the
aspeed_smc_update_cs() routine which uselessly loops on all slaves to
update their status.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f248a9dbd0cfb9f577f7cb6f799497c51690054a
https://github.com/qemu/qemu/commit/f248a9dbd0cfb9f577f7cb6f799497c51690054a
Author: Cédric Le Goater <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/ssi/aspeed_smc.c
Log Message:
-----------
aspeed/smc: rework the prototype of the AspeedSMCFlash helper routines
Change the routines prototype to use a 'AspeedSMCFlash *' instead of
'AspeedSMCState *'. The result will help in making future changes
clearer.
Also change aspeed_smc_update_cs() which uselessly loops on all slave
devices to update their status.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 0707b34dcb87b5446208362cd6c8ccff75f2e01c
https://github.com/qemu/qemu/commit/0707b34dcb87b5446208362cd6c8ccff75f2e01c
Author: Cédric Le Goater <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/ssi/aspeed_smc.c
Log Message:
-----------
aspeed/smc: autostrap CE0/1 configuration
On the AST2500 SoC, the FMC controller flash type is fixed to SPI for
CE0 and CE1 and 4BYTE mode is autodetected for CE0.
On the AST2400 SoC, the FMC controller flash type and 4BYTE mode are
strapped with register SCU70. We use the default settings from the
palmetto-bmc machine for now.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d09dc5b75bba7eee06679b5d1450998c0d43fc01
https://github.com/qemu/qemu/commit/d09dc5b75bba7eee06679b5d1450998c0d43fc01
Author: Cédric Le Goater <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/ssi/aspeed_smc.c
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
aspeed/smc: unfold the AspeedSMCController array
This is getting difficult to read. Also add a 'has_dma' field for each
controller type.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 087b57c993a6158148032a4e6e2ab2ac7285a5f4
https://github.com/qemu/qemu/commit/087b57c993a6158148032a4e6e2ab2ac7285a5f4
Author: Cédric Le Goater <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/ssi/aspeed_smc.c
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
aspeed/smc: adjust the size of the register region
The SPI controller of the AST2400 SoC has less registers. So we can
adjust the size of the memory region holding the registers depending
on the controller type. We can also remove the guest_error logging
which is useless as the range of the region is strict enough.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: fcdf2c59456fb6d0fdc656cf395b2aa15888b46c
https://github.com/qemu/qemu/commit/fcdf2c59456fb6d0fdc656cf395b2aa15888b46c
Author: Cédric Le Goater <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/ssi/aspeed_smc.c
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
aspeed/smc: handle SPI flash Command mode
The Aspeed SMC controllers have a mode (Command mode) in which
accesses to the flash content are no different than doing MMIOs. The
controller generates all the necessary commands to load (or store)
data in memory.
However, accesses are restricted to the segment window assigned the
the flash module by the controller. This window is defined by the
Segment Address Register.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
[PMM: Deleted now-unused aspeed_smc_is_usermode() function]
Signed-off-by: Peter Maydell <address@hidden>
Commit: bd9f5052007a6507912a02f9e6d8860e1232ca00
https://github.com/qemu/qemu/commit/bd9f5052007a6507912a02f9e6d8860e1232ca00
Author: Cédric Le Goater <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M tests/m25p80-test.c
Log Message:
-----------
aspeed/smc: reset flash after each test
Let's make sure when each test is run that the flash object is in an
initial state and did not keep configuration from the previous tests.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 371a3dd2042a935258451270f0dfd13dad728061
https://github.com/qemu/qemu/commit/371a3dd2042a935258451270f0dfd13dad728061
Author: Cédric Le Goater <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M tests/m25p80-test.c
Log Message:
-----------
aspeed/smc: extend tests for Command mode
The Aspeed SMC controllers have a mode (Command mode) in which
accesses to the flash content are no different than doing MMIOs. The
controller generates all the necessary commands to load (or store)
data in memory.
So add a couple of tests doing direct reads and writes on the AHB bus.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d769a1da342d6af58adcaf1db2752654963a6a8b
https://github.com/qemu/qemu/commit/d769a1da342d6af58adcaf1db2752654963a6a8b
Author: Cédric Le Goater <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
aspeed: use first FMC flash as a boot ROM
Create a ROM region, using the default size of the mapping window for
the CE0 FMC flash module, and fill it with the flash content.
This is a little hacky but until we can boot from a MMIO region, it
seems difficult to do anything else.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: abf3a4e5eeab9b1d4dea4149a9e77d970fe83fc5
https://github.com/qemu/qemu/commit/abf3a4e5eeab9b1d4dea4149a9e77d970fe83fc5
Author: Shannon Zhao <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
arm: virt: Fix segmentation fault when specifying an unsupported CPU
Using -cpu cortex-a9 (or any other unsupported CPU) with the virt
board will cause QEMU to segmentation fault. This bug was introduced
in commit 9ac4ef77, which incorrectly added a NULL terminator when
converting the VirtBoardInfo array into a simple array of strings
defining the valid CPUs. The cpuname_valid() loop already has
a termination condition based on ARRAY_SIZE, so the NULL is
spurious and causes the strcmp() to segfault if we reach it.
Delete the NULL.
Signed-off-by: Shannon Zhao <address@hidden>
Message-id: address@hidden
[PMM: expanded commit message]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: ebfcc03bf73548d3c8456e441a00b09c1e8f0976
https://github.com/qemu/qemu/commit/ebfcc03bf73548d3c8456e441a00b09c1e8f0976
Author: Ard Biesheuvel <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/arm/virt-acpi-build.c
Log Message:
-----------
hw/arm/virt-acpi - reserve ECAM space as PNP0C02 device
Linux for arm64 v4.10 and later will complain if the ECAM config space is
not reserved in the ACPI namespace:
acpi PNP0A08:00: [Firmware Bug]: ECAM area [mem 0x3f000000-0x3fffffff] not
reserved in ACPI namespace
The rationale is that OSes that don't consume the MCFG table should still
be able to infer that the PCI config space MMIO region is occupied.
So update the ACPI table generation routine to add this reservation.
Signed-off-by: Ard Biesheuvel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: b53db42bc0140a32e5196125b216a82d08992a7d
https://github.com/qemu/qemu/commit/b53db42bc0140a32e5196125b216a82d08992a7d
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/intc/arm_gicv3_common.c
M include/hw/intc/arm_gicv3_common.h
Log Message:
-----------
hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ
Augment the GICv3's QOM device interface by adding two
new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to
each CPU.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Commit: 6a228959081c12cc8a4f268ed00f77dbd0755404
https://github.com/qemu/qemu/commit/6a228959081c12cc8a4f268ed00f77dbd0755404
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/intc/arm_gic_common.c
M include/hw/intc/arm_gic_common.h
Log Message:
-----------
hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQ
Augment the GIC's QOM device interface by adding two
new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to
each CPU.
We never use these, but it's helpful to keep the v2-and-earlier
GIC's external interface in line with that of the GICv3 to
avoid board code having to add extra code conditional on which
version of the GIC is in use.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Commit: aa1b3111b3f3c53b9290ecade02f31acfc579c16
https://github.com/qemu/qemu/commit/aa1b3111b3f3c53b9290ecade02f31acfc579c16
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
Log Message:
-----------
target-arm: Expose output GPIO line for VCPU maintenance interrupt
The GICv3 support for virtualization includes an outbound
maintenance interrupt signal which is asserted when the
CPU interface wants to signal to the hypervisor that it
needs attention. Expose this as an outbound GPIO line from
the CPU object which can be wired up as a physical interrupt
line by the board code (as we do already for the CPU timers).
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Commit: 5454006a7cc6caf10c1816e6828b75a40fbcc16e
https://github.com/qemu/qemu/commit/5454006a7cc6caf10c1816e6828b75a40fbcc16e
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU
Wire the new VIRQ, VFIQ and maintenance interrupt lines from the
GIC to each CPU.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Commit: e45868a3f30a1fdf22bdee8b503b71d8f642f0f4
https://github.com/qemu/qemu/commit/e45868a3f30a1fdf22bdee8b503b71d8f642f0f4
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M target/arm/cpu.h
M target/arm/cpu64.c
Log Message:
-----------
target-arm: Add ARMCPU fields for GIC CPU i/f config
Add fields to the ARMCPU structure to allow CPU classes to
specify the configurable aspects of their GIC CPU interface.
In particular, the virtualization support allows different
values for number of list registers, priority bits and
preemption bits.
Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Commit: e69d2fa0650aec5e4e1a757c184ae294c902949a
https://github.com/qemu/qemu/commit/e69d2fa0650aec5e4e1a757c184ae294c902949a
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/intc/gicv3_internal.h
Log Message:
-----------
hw/intc/gicv3: Add defines for ICH system register fields
Add defines to gicv3_internal.h for fields in the ICH_*
system registers which form the GIC virtualization control
interface.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 4eb833b5dfcfda23877b03546915c0f45613b7b5
https://github.com/qemu/qemu/commit/4eb833b5dfcfda23877b03546915c0f45613b7b5
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/intc/arm_gicv3_common.c
M hw/intc/arm_gicv3_cpuif.c
M include/hw/intc/arm_gicv3_common.h
Log Message:
-----------
hw/intc/gicv3: Add data fields for virtualization support
As the first step in adding support for the virtualization
extensions to the GICv3 emulation:
* add the necessary data fields to the state structures
* add the fields to the migration state, as a subsection
which is only present if virtualization is enabled
The use of a subsection means we retain migration
compatibility as EL2 is not enabled on any CPUs currently.
Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Commit: 83f036fe3d56be237d87e32f44f3d46686e7eab7
https://github.com/qemu/qemu/commit/83f036fe3d56be237d87e32f44f3d46686e7eab7
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/trace-events
Log Message:
-----------
hw/intc/arm_gicv3: Add accessors for ICH_ system registers
The GICv3 virtualization interface includes system registers
accessible only to the hypervisor which form the control
interface for interrupt virtualization. Implement these
registers.
The function gicv3_cpuif_virt_update() which determines
whether it needs to signal vIRQ, vFIQ or a maintenance
interrupt is introduced here as a stub function -- its
implementation will be added in a subsequent commit.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 77620ba65ef32121de20848f9635c4afe233a1ce
https://github.com/qemu/qemu/commit/77620ba65ef32121de20848f9635c4afe233a1ce
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/trace-events
Log Message:
-----------
hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors
If the HCR_EL2.IMO or FMO bits are set, accesses to ICC_
system registers are redirected to be accesses to ICV_
registers (the guest-visible interface to the virtual
interrupt controller). Implement this behaviour for the
ICV_ registers which are simple accessors to the underlying
register state.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: df313f481f4167bf0af0a0d362b77aa22574ff56
https://github.com/qemu/qemu/commit/df313f481f4167bf0af0a0d362b77aa22574ff56
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/trace-events
Log Message:
-----------
hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers
Implement the the ICV_ registers HPPIR, DIR and RPR.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: b3b48f529fe8dad6c28bd25ec4a4a7ee7a0b0dcd
https://github.com/qemu/qemu/commit/b3b48f529fe8dad6c28bd25ec4a4a7ee7a0b0dcd
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/trace-events
Log Message:
-----------
hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR
Implement the two remaining ICV_ registers: EOIR and IAR.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: c5fc89b36c0a167548ae7af40dc085707a7756d2
https://github.com/qemu/qemu/commit/c5fc89b36c0a167548ae7af40dc085707a7756d2
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/trace-events
M include/hw/intc/arm_gicv3_common.h
Log Message:
-----------
hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()
Implement the function which signals virtual interrupts to the
CPU as appropriate following CPU interface state changes.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 86830554dbf5620dab50ba2aa91f86c247e99958
https://github.com/qemu/qemu/commit/86830554dbf5620dab50ba2aa91f86c247e99958
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs
Implement the architecturally required traps from NS EL1
to EL2 for the CPU interface registers. These fall into
several different groups:
* group-0-only registers all trap if ICH_HRC_EL2.TALL0 is set
(exactly the registers covered by gicv3_fiq_access())
* group-1-only registers all trap if ICH_HRC_EL2.TALL1 is set
(exactly the registers covered by gicv3_irq_access())
* DIR traps if ICH_HCR_EL2.TC or ICH_HCR_EL2.TDIR are set
* PMR, RPR, CTLR trap if ICH_HCR_EL2.TC is set
* SGI0R, SGI1R, ASGI1R trap if ICH_HCR_EL2.TC is set or
if HCR_EL2.IMO or HCR_EL2.FMO are set
We split DIR and the SGI registers out into their own access
functions, leaving the existing gicv3_irqfiq_access() just
handling PMR, RPR and CTLR.
This commit doesn't implement support for trapping on
HSTR_EL2.T12 for the 32-bit registers, as we don't implement
any of those per-coprocessor trap bits currently and
probably will want to do those in some more centralized way.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 2013c5665cf001f4929e791c9f2262fdb508cf60
https://github.com/qemu/qemu/commit/2013c5665cf001f4929e791c9f2262fdb508cf60
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
hw/arm/virt: Support using SMC for PSCI
If we are giving the guest a CPU with EL2, it is likely to
want to use the HVC instruction itself, for instance for
providing PSCI to inner guest VMs. This makes using HVC
as the PSCI conduit for the outer QEMU a bad idea. We will
want to use SMC instead is this case: this makes sense
because QEMU's PSCI implementation is effectively an
emulation of functionality provided by EL3 firmware.
Add code to support selecting the PSCI conduit to use,
rather than hardcoding use of HVC.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Commit: 79e993a0a804783f6196eaea9eab28ea8440528b
https://github.com/qemu/qemu/commit/79e993a0a804783f6196eaea9eab28ea8440528b
Author: Andrew Jones <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/arm/virt-acpi-build.c
Log Message:
-----------
hw/arm/virt-acpi-build: use SMC if booting in EL2
Signed-off-by: Andrew Jones <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: look at vms->psci_conduit rather than vms->virt
to decide whether to use HVC or SMC, and report no
PSCI support at all for the 'PSCI disabled' case]
Signed-off-by: Peter Maydell <address@hidden>
Commit: 3f591a20221511c639cc7959755e570801a21cd2
https://github.com/qemu/qemu/commit/3f591a20221511c639cc7959755e570801a21cd2
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M target/arm/psci.c
Log Message:
-----------
target/arm/psci.c: If EL2 implemented, start CPUs in EL2
The PSCI spec states that a CPU_ON call should cause the new
CPU to be started in the highest implemented Non-secure
exception level. We were incorrectly starting it at the
exception level of the caller, which happens to be correct
if EL2 is not implemented. Implement the correct logic
as described in the PSCI 1.0 spec section 6.4:
* if EL2 exists and SCR_EL3.HCE is set: start in EL2
* otherwise start in EL1
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Tested-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Commit: c25bd18a04c8bd0f19556d719864b7b08528222d
https://github.com/qemu/qemu/commit/c25bd18a04c8bd0f19556d719864b7b08528222d
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/arm/virt.c
M hw/arm/xlnx-zynqmp.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
Log Message:
-----------
target-arm: Enable EL2 feature bit on A53 and A57
Enable the ARM_FEATURE_EL2 bit on Cortex-A52 and
Cortex-A57, since this is all now sufficiently implemented
to work with the GICv3. We provide the usual CPU property
to disable it for backwards compatibility with the older
virt boards.
In this commit, we disable the EL2 feature on the
virt and ZynpMP boards, so there is no overall effect.
Another commit will expose a board-level property to
allow the user to enable EL2.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Commit: f29cacfb5fc0a6e93efc3f6d2900d82d625f143e
https://github.com/qemu/qemu/commit/f29cacfb5fc0a6e93efc3f6d2900d82d625f143e
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
hw/arm/virt: Add board property to enable EL2
Add a board level property to the virt board which will
enable EL2 on the CPU if the user asks for it. The
default is not to provide EL2. If EL2 is enabled then
we will use SMC as our PSCI conduit, and report the
virtualization support in the GICv3 device tree node
and the ACPI tables.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Commit: 28f5e970a69f0be05d08eb81bdc72ab35b591dd7
https://github.com/qemu/qemu/commit/28f5e970a69f0be05d08eb81bdc72ab35b591dd7
Author: Peter Maydell <address@hidden>
Date: 2017-01-20 (Fri, 20 Jan 2017)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/imx25_pdk.c
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M hw/arm/xlnx-zynqmp.c
M hw/block/m25p80.c
M hw/i2c/imx_i2c.c
M hw/intc/arm_gic_common.c
M hw/intc/arm_gicv3_common.c
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/gicv3_internal.h
M hw/intc/trace-events
M hw/ssi/aspeed_smc.c
M include/hw/arm/virt.h
M include/hw/intc/arm_gic_common.h
M include/hw/intc/arm_gicv3_common.h
M include/hw/ssi/aspeed_smc.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/psci.c
M tests/m25p80-test.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170120'
into staging
target-arm queue:
* support virtualization in GICv3
* enable EL2 in AArch64 CPU models
* allow EL2 to be enabled on 'virt' board via -machine virtualization=on
* aspeed: SMC improvements
* m25p80: support die erase command
* m25p80: Add Quad Page Program 4byte
* m25p80: Improve 1GiB Micron flash definition
* arm: Uniquely name imx25 I2C buses
# gpg: Signature made Fri 20 Jan 2017 11:31:53 GMT
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20170120: (36 commits)
hw/arm/virt: Add board property to enable EL2
target-arm: Enable EL2 feature bit on A53 and A57
target/arm/psci.c: If EL2 implemented, start CPUs in EL2
hw/arm/virt-acpi-build: use SMC if booting in EL2
hw/arm/virt: Support using SMC for PSCI
hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs
hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()
hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR
hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers
hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors
hw/intc/arm_gicv3: Add accessors for ICH_ system registers
hw/intc/gicv3: Add data fields for virtualization support
hw/intc/gicv3: Add defines for ICH system register fields
target-arm: Add ARMCPU fields for GIC CPU i/f config
hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU
target-arm: Expose output GPIO line for VCPU maintenance interrupt
hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQ
hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ
hw/arm/virt-acpi - reserve ECAM space as PNP0C02 device
arm: virt: Fix segmentation fault when specifying an unsupported CPU
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/0f6bcf68a99e...28f5e970a69f
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