[Qemu-commits] [qemu/qemu] 450aaa: cadence_uart: Check baud rate generat

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[Qemu-commits] [qemu/qemu] 450aaa: cadence_uart: Check baud rate generat

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 450aaa: cadence_uart: Check baud rate generator and divide...
Date:	Tue, 27 Dec 2016 09:30:07 -0800
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 450aaae8638e4c75ac6547ce6e09d63281a5a925
      
https://github.com/qemu/qemu/commit/450aaae8638e4c75ac6547ce6e09d63281a5a925
  Author: Alistair Francis <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/char/cadence_uart.c

  Log Message:
  -----------
  cadence_uart: Check baud rate generator and divider values on migration

The Cadence UART device emulator calculates speed by dividing the
baud rate by a 'baud rate generator' & 'baud rate divider' value.
The device specification defines these register values to be
non-zero and within certain limits. Checks were recently added when
writing to these registers but not when restoring from migration.

This patch adds checks when restoring from migration to avoid divide by
zero errors.

Reported-by: Huawei PSIRT <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2494c9f6405a1979319f12d1bb4e9a6eb28a529d
      
https://github.com/qemu/qemu/commit/2494c9f6405a1979319f12d1bb4e9a6eb28a529d
  Author: Andrew Gacek <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/char/cadence_uart.c

  Log Message:
  -----------
  cadence_uart: Check if receiver timeout counter is disabled

When register Rcvr_timeout_reg0 (R_RTOR in cadence_uart.c) is set to
0, the receiver timeout counter should be disabled. See page 1801 of
"Zynq-7000 AP SoC Technical Reference Manual". This commit adds a
such a check before setting the receive timeout interrupt.

Signed-off-by: Andrew Gacek <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0f1944735b6bac810b067e8a7a5154744536fd59
      
https://github.com/qemu/qemu/commit/0f1944735b6bac810b067e8a7a5154744536fd59
  Author: Julian Brown <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  Correct value of ARM Cortex-A8 MVFR1 register.

The value of the MVFR1 (Media and VFP Feature Register 1) register for
the Cortex-A8 appears to be incorrect (according to the TRM, DDI0344K),
with the "full denormal arithmetic" and "propagation of NaN" fields
holding both 0 instead of both 1.

I had a go tracing the history of the use of this value, and it seems
it's always just been wrong in QEMU: maybe it was derived from early
documentation, or guessed based on the use of a "VFP Lite" implementation
in the Cortex-A8.

Depending on the startup/early-boot code in use, this can manifest as
failure to perform denormal arithmetic properly: in our case, selecting
a Cortex-A8 CPU when using QEMU as an instruction-set simulator for
bare-metal GCC testing caused tests using denormal arithmetic to
fail. Problems might be masked (or not occur) when using a full OS kernel
with suitable trap handlers (I'm not sure).

Signed-off-by: Julian Brown <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 416d72b97b01d6cb769ad0fd0e10614583354a45
      
https://github.com/qemu/qemu/commit/416d72b97b01d6cb769ad0fd0e10614583354a45
  Author: Richard Henderson <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target-arm: Fix aarch64 vec_reg_offset

Since CPUARMState.vfp.regs is not 16 byte aligned, the ^ 8 fixup used
for a big-endian host doesn't do what's intended.  Fix this by adding
in the vfp.regs offset after computing the inter-register offset.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0a97c40f8e7172ac3d8db97fb22d0ef3025de307
      
https://github.com/qemu/qemu/commit/0a97c40f8e7172ac3d8db97fb22d0ef3025de307
  Author: Richard Henderson <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target-arm: Fix aarch64 disas_ldst_single_struct

We add s->be_data within do_vec_ld/st.  Adding it here means that
we have the wrong bits set in SIZE for a big-endian host, leading
to g_assert_not_reached in write_vec_element and read_vec_element.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 92204403ef939a1baa1b31bd76716f4566c2a6f1
      
https://github.com/qemu/qemu/commit/92204403ef939a1baa1b31bd76716f4566c2a6f1
  Author: Andrew Jones <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/intc/arm_gicv3_common.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_common: fix aff3 in typer

Signed-off-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c9b61d9aa1ad234b0961f8add023cdc999cda3da
      
https://github.com/qemu/qemu/commit/c9b61d9aa1ad234b0961f8add023cdc999cda3da
  Author: Peter Maydell <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M target/arm/op_helper.c

  Log Message:
  -----------
  target-arm: Log AArch64 exception returns

We already log exception entry; add logging of the AArch64 exception
return path as well.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: e971fa042253ed36e602a2c1bc01144da3e8832f
      
https://github.com/qemu/qemu/commit/e971fa042253ed36e602a2c1bc01144da3e8832f
  Author: Peter Maydell <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/intc/arm_gicv3_cpuif.c

  Log Message:
  -----------
  hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset

In the ARMCPRegInfo definitions for the GICv3 CPU interface
registers, we were trying to use .fieldoffset to specify
the locations of data fields within the GICv3CPUState struct.
This is completely broken, because .fieldoffset is for offsets
into the CPUARMState struct. We didn't notice because we
were only using this for reads to BPR0, AP0R<n>, IGRPEN0
and CTLR_EL3, and Linux doesn't use these registers.

Replace the .fieldoffset uses with explicit read functions.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 0bfa02595aa2b887d1e7f56600a5aec7067c71b0
      
https://github.com/qemu/qemu/commit/0bfa02595aa2b887d1e7f56600a5aec7067c71b0
  Author: Peter Maydell <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/intc/arm_gicv3.c

  Log Message:
  -----------
  hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU

The GICv3 requires that we only signal Pending interrupts to
the CPU. This category does not include Pending+Active interrupts,
which means we need to check whether the interrupt is Active in
the gicr_int_pending() and gicd_int_pending() functions.

Interrupts are rarely in the Active+Pending state, but KVM
uses this as part of its handling of the virtual timer, so
this bug was causing KVM to go into an infinite loop of
taking the vtimer interrupt when the guest first triggered it.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: e353aac51b944de9cfce5c6cee6b5c28eddbbd77
      
https://github.com/qemu/qemu/commit/e353aac51b944de9cfce5c6cee6b5c28eddbbd77
  Author: Peter Maydell <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/arm/virt.c
    M include/hw/compat.h

  Log Message:
  -----------
  hw/arm/virt: add 2.9 machine type

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>


  Commit: e03192fd62d9d673b42e010f6fab3ef4cf44903e
      
https://github.com/qemu/qemu/commit/e03192fd62d9d673b42e010f6fab3ef4cf44903e
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  m25p80: add support for the mx66l1g45g

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Marcin Krzeminski <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2d105bd6b58d83295310915f5503ef14d97f4c0f
      
https://github.com/qemu/qemu/commit/2d105bd6b58d83295310915f5503ef14d97f4c0f
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/arm/aspeed_soc.c
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  aspeed: QOMify the CPU object and attach it to the SoC

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4c3386f42102652f2b75e135cf09c9ea31cdec88
      
https://github.com/qemu/qemu/commit/4c3386f42102652f2b75e135cf09c9ea31cdec88
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/arm/aspeed_soc.c

  Log Message:
  -----------
  aspeed: remove cannot_destroy_with_object_finalize_yet

With commit ce5b1bbf624b ("exec: move cpu_exec_init() calls to realize
functions"), we can now remove cannot_destroy_with_object_finalize_yet.

Suggested-by: Andrew Jeffery <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bd673bd8aba8b9f316c3c95f7be872087bb55695
      
https://github.com/qemu/qemu/commit/bd673bd8aba8b9f316c3c95f7be872087bb55695
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/arm/aspeed_soc.c

  Log Message:
  -----------
  aspeed: attach the second SPI controller object to the SoC

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6a0e947b125f5727d3e59f13cb15a5284404c27e
      
https://github.com/qemu/qemu/commit/6a0e947b125f5727d3e59f13cb15a5284404c27e
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: extend the board configuration with flash models

Future machine will use different flash models for the FMC and the SPI
controllers.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ef17f8366173aa28e3b32469725b221ab03fc421
      
https://github.com/qemu/qemu/commit/ef17f8366173aa28e3b32469725b221ab03fc421
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: add support for the romulus-bmc board

The Romulus machine is an OpenPOWER system with an AST2500 SoC for
the BMC and a POWER9 chip for the host. It does not make much
difference for qemu a part from the fact that the FMC controller has
two SPI flash module.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 74af4eec29f828b8ddf51d9f071264866c868ccb
      
https://github.com/qemu/qemu/commit/74af4eec29f828b8ddf51d9f071264866c868ccb
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/arm/aspeed_soc.c
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  aspeed: add a memory region for SRAM

The size of the SRAM depends on the SoC model, so use a per-soc
definition when creating the region.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6efbac908f3052a88eb466e2afd75f333de3b17d
      
https://github.com/qemu/qemu/commit/6efbac908f3052a88eb466e2afd75f333de3b17d
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/arm/aspeed_soc.c
    M hw/misc/aspeed_scu.c
    M hw/misc/aspeed_sdmc.c
    M include/hw/misc/aspeed_scu.h

  Log Message:
  -----------
  aspeed: add the definitions for the AST2400 A1 SoC

There is not much differences with the A0 revision apart from the DDR
calibration.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bd407a21a9927acf2c02a2c44923af52f279e2ac
      
https://github.com/qemu/qemu/commit/bd407a21a9927acf2c02a2c44923af52f279e2ac
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: change SoC revision of the palmetto-bmc machine

The palmetto BMC machine uses a AST2400 revision A1 SoC.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c491e1521f20a44517c68ea920f10c03b864c140
      
https://github.com/qemu/qemu/commit/c491e1521f20a44517c68ea920f10c03b864c140
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/misc/aspeed_scu.c

  Log Message:
  -----------
  aspeed/scu: fix SCU region size

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0584d3c33f70445085d3f223015c67dfcea97ba3
      
https://github.com/qemu/qemu/commit/0584d3c33f70445085d3f223015c67dfcea97ba3
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: improve segment register support

The HW does not enforce all the rules in the specs and allows a few
"curious" setups like zero size segments and overlaps. So change the
model to be in sync but keep the warnings which are always interesting
for debug.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 26d5df9578927fce97a83975feecf1a3c2511610
      
https://github.com/qemu/qemu/commit/26d5df9578927fce97a83975feecf1a3c2511610
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/arm/aspeed.c
    M hw/arm/aspeed_soc.c

  Log Message:
  -----------
  aspeed/smc: set the number of flash modules for the FMC controller

Add a new configuration field at the board level and propagate the
value using the "num-cs" property of the FMC controller model.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8e953a658fa13b05bea67899a91d8b65f2b89f11
      
https://github.com/qemu/qemu/commit/8e953a658fa13b05bea67899a91d8b65f2b89f11
  Author: Alastair D'Silva <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/arm/pxa2xx.c

  Log Message:
  -----------
  hw/arm: remove trailing whitespace

Remove trailing whitespace in hw/arm/pxa2xx.c

Signed-off-by: Alastair D'Silva <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9e41bade85ef338afd983c109368d1bbbe931f80
      
https://github.com/qemu/qemu/commit/9e41bade85ef338afd983c109368d1bbbe931f80
  Author: Alastair D'Silva <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/arm/pxa2xx.c
    M hw/arm/tosa.c
    M hw/arm/z2.c
    M hw/i2c/core.c
    M hw/timer/ds1338.c

  Log Message:
  -----------
  hw/i2c: Add a NULL check for i2c slave init callbacks

Add a NULL check for i2c slave init callbacks, so that we no longer
need to implement empty init functions.

Signed-off-by: Alastair D'Silva <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: squashed in later tweak from Alistair to if() phrasing]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 91db4642f868cf2e591b62d31a19d35b02ea791e
      
https://github.com/qemu/qemu/commit/91db4642f868cf2e591b62d31a19d35b02ea791e
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target-arm: Add VBAR support to ARM1176 CPUs

ARM1176 CPUs have TrustZone support and can use the Vector Base
Address Register, but currently, qemu only adds VBAR support to ARMv7
CPUs. Fix this by adding a new feature ARM_FEATURE_VBAR which can used
for ARMv7 and ARM1176 CPUs.

The VBAR feature is always set for ARMv7 because some legacy boards
require it even if this is not architecturally correct.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0f72559fbc9e1ae45aa8ebeed0443fe3a7a388a8
      
https://github.com/qemu/qemu/commit/0f72559fbc9e1ae45aa8ebeed0443fe3a7a388a8
  Author: Peter Maydell <address@hidden>
  Date:   2016-12-27 (Tue, 27 Dec 2016)

  Changed paths:
    M hw/arm/aspeed.c
    M hw/arm/aspeed_soc.c
    M hw/arm/pxa2xx.c
    M hw/arm/tosa.c
    M hw/arm/virt.c
    M hw/arm/z2.c
    M hw/block/m25p80.c
    M hw/char/cadence_uart.c
    M hw/i2c/core.c
    M hw/intc/arm_gicv3.c
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_cpuif.c
    M hw/misc/aspeed_scu.c
    M hw/misc/aspeed_sdmc.c
    M hw/ssi/aspeed_smc.c
    M hw/timer/ds1338.c
    M include/hw/arm/aspeed_soc.h
    M include/hw/compat.h
    M include/hw/misc/aspeed_scu.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/op_helper.c
    M target/arm/translate-a64.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20161227' 
into staging

target-arm queue:
 * add VBAR support to ARM1176 CPUs
 * hw/i2c: add NULL check to i2c slave init callbacks
 * pxa2xx.c: fix trailing whitespace
 * aspeed: various cleanups
 * aspeed: add romulus-bmc board
 * virt: add 2.9 machine type
 * gicv3: don't signal Pending+Active interrupts to CPU
 * gicv3: fix incorrect usage of fieldoffset
 * arm: log AArch64 exception returns
 * gicv3: fix aff3 field in typer register
 * aarch64: fix ldst_single_struct on BE hosts
 * aarch64: fix vec_reg_offset on BE hosts
 * arm: fix Cortex-A8 MVFR1 register value
 * cadence_uart: check if receiver timeout counter disabled
 * cadence_uart: check register values on migration

# gpg: Signature made Tue 27 Dec 2016 15:19:26 GMT
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20161227: (25 commits)
  target-arm: Add VBAR support to ARM1176 CPUs
  hw/i2c: Add a NULL check for i2c slave init callbacks
  hw/arm: remove trailing whitespace
  aspeed/smc: set the number of flash modules for the FMC controller
  aspeed/smc: improve segment register support
  aspeed/scu: fix SCU region size
  aspeed: change SoC revision of the palmetto-bmc machine
  aspeed: add the definitions for the AST2400 A1 SoC
  aspeed: add a memory region for SRAM
  aspeed: add support for the romulus-bmc board
  aspeed: extend the board configuration with flash models
  aspeed: attach the second SPI controller object to the SoC
  aspeed: remove cannot_destroy_with_object_finalize_yet
  aspeed: QOMify the CPU object and attach it to the SoC
  m25p80: add support for the mx66l1g45g
  hw/arm/virt: add 2.9 machine type
  hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU
  hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset
  target-arm: Log AArch64 exception returns
  hw/intc/arm_gicv3_common: fix aff3 in typer
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/e5fdf663cf01...0f72559fbc9e
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