[Qemu-commits] [qemu/qemu] 808832: target-sparc: Use overalignment flags

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[Qemu-commits] [qemu/qemu] 808832: target-sparc: Use overalignment flags

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 808832: target-sparc: Use overalignment flags for twinx an...
Date:	Tue, 01 Nov 2016 05:00:05 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 808832277af11dafee5a55da2b9e41d019b879ca
      
https://github.com/qemu/qemu/commit/808832277af11dafee5a55da2b9e41d019b879ca
  Author: Richard Henderson <address@hidden>
  Date:   2016-10-31 (Mon, 31 Oct 2016)

  Changed paths:
    M target-sparc/translate.c

  Log Message:
  -----------
  target-sparc: Use overalignment flags for twinx and block asis

This allows us to enforce 16 and 64-byte alignment
without any extra overhead.

Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>


  Commit: 2f9d35fc4006122bad33f9ae3e2e51d2263e98ee
      
https://github.com/qemu/qemu/commit/2f9d35fc4006122bad33f9ae3e2e51d2263e98ee
  Author: Richard Henderson <address@hidden>
  Date:   2016-10-31 (Mon, 31 Oct 2016)

  Changed paths:
    M target-sparc/cpu.h
    M target-sparc/helper.c
    M target-sparc/ldst_helper.c
    M target-sparc/translate.c
    M target-sparc/win_helper.c

  Log Message:
  -----------
  target-sparc: Introduce cpu_raise_exception_ra

Several helpers call helper_raise_exception directly, which requires
in turn that their callers have performed save_state.  The new function
allows a TCG return address to be passed in so that we can restore
PC + NPC + flags data from that.

This fixes a bug in the usage of helper_check_align, whose callers had
not been calling save_state.  It fixes another bug in which the divide
helpers used GETPC at a level other than the direct callee from TCG.

This allows the translator to avoid save_state prior to SAVE, RESTORE,
and FLUSHW instructions.

Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: af7a06bac7d3abb2da48ef3277d2a415772d2ae8
      
https://github.com/qemu/qemu/commit/af7a06bac7d3abb2da48ef3277d2a415772d2ae8
  Author: Richard Henderson <address@hidden>
  Date:   2016-10-31 (Mon, 31 Oct 2016)

  Changed paths:
    M target-sparc/cpu.h
    M target-sparc/ldst_helper.c
    M target-sparc/mmu_helper.c

  Log Message:
  -----------
  target-sparc: Add MMU_PHYS_IDX

It's handy to have a mmu idx for physical addresses, so
that mmu disabled and physical access asis can use the
same path as normal accesses.

Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 7f87c90527d7363e8cecf1c6b5ad3d4cc85d3d28
      
https://github.com/qemu/qemu/commit/7f87c90527d7363e8cecf1c6b5ad3d4cc85d3d28
  Author: Richard Henderson <address@hidden>
  Date:   2016-10-31 (Mon, 31 Oct 2016)

  Changed paths:
    M target-sparc/translate.c

  Log Message:
  -----------
  target-sparc: Use MMU_PHYS_IDX for bypass asis

Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 34a6e13da70b2c798630a8dbd03d09f201c0198f
      
https://github.com/qemu/qemu/commit/34a6e13da70b2c798630a8dbd03d09f201c0198f
  Author: Richard Henderson <address@hidden>
  Date:   2016-10-31 (Mon, 31 Oct 2016)

  Changed paths:
    M target-sparc/translate.c

  Log Message:
  -----------
  target-sparc: Handle more twinx asis

As used by HelenOS, presumably for ultra 2 and 3,
prior to the sun4v platform and the current twinx names.

Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 4fb554bc6c88eb45270a3ad3cf6e6e2ad476aede
      
https://github.com/qemu/qemu/commit/4fb554bc6c88eb45270a3ad3cf6e6e2ad476aede
  Author: Richard Henderson <address@hidden>
  Date:   2016-10-31 (Mon, 31 Oct 2016)

  Changed paths:
    M target-sparc/translate.c

  Log Message:
  -----------
  target-sparc: Implement swap_asi inline

Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: fbb4bbb62e5603c991b880e25dc4bb30d342b944
      
https://github.com/qemu/qemu/commit/fbb4bbb62e5603c991b880e25dc4bb30d342b944
  Author: Richard Henderson <address@hidden>
  Date:   2016-10-31 (Mon, 31 Oct 2016)

  Changed paths:
    M target-sparc/translate.c

  Log Message:
  -----------
  target-sparc: Implement ldstub_asi inline

Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 7268adebfda6548b8ae6865dc8337f116a5d266d
      
https://github.com/qemu/qemu/commit/7268adebfda6548b8ae6865dc8337f116a5d266d
  Author: Richard Henderson <address@hidden>
  Date:   2016-10-31 (Mon, 31 Oct 2016)

  Changed paths:
    M target-sparc/helper.h
    M target-sparc/ldst_helper.c
    M target-sparc/translate.c

  Log Message:
  -----------
  target-sparc: Implement cas_asi/casx_asi inline

Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 34810610acbde7a0745be3a88e99f2ef9282260f
      
https://github.com/qemu/qemu/commit/34810610acbde7a0745be3a88e99f2ef9282260f
  Author: Richard Henderson <address@hidden>
  Date:   2016-10-31 (Mon, 31 Oct 2016)

  Changed paths:
    M target-sparc/translate.c

  Log Message:
  -----------
  target-sparc: Implement BCOPY/BFILL inline

Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 918d9a2c9d36378a3cf6636018900a4731c83b9d
      
https://github.com/qemu/qemu/commit/918d9a2c9d36378a3cf6636018900a4731c83b9d
  Author: Richard Henderson <address@hidden>
  Date:   2016-10-31 (Mon, 31 Oct 2016)

  Changed paths:
    M target-sparc/helper.h
    M target-sparc/ldst_helper.c
    M target-sparc/translate.c

  Log Message:
  -----------
  target-sparc: Remove asi helper code handled inline

Now that we never call out to helpers when direct accesses can
handle an asi, remove the corresponding code in those helpers.
For ldda, this removes the entire helper.

Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: f939ffe5a022a8798824e2720ed5a14186fca6b6
      
https://github.com/qemu/qemu/commit/f939ffe5a022a8798824e2720ed5a14186fca6b6
  Author: Richard Henderson <address@hidden>
  Date:   2016-10-31 (Mon, 31 Oct 2016)

  Changed paths:
    M target-sparc/helper.h
    M target-sparc/ldst_helper.c
    M target-sparc/translate.c

  Log Message:
  -----------
  target-sparc: Implement ldqf and stqf inline

At the same time, fix a problem with stqf_asi, when
a write might access two pages.

Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: cb21b4da6cca1bb4e3f5fefb698fb9e4d00c8f66
      
https://github.com/qemu/qemu/commit/cb21b4da6cca1bb4e3f5fefb698fb9e4d00c8f66
  Author: Richard Henderson <address@hidden>
  Date:   2016-10-31 (Mon, 31 Oct 2016)

  Changed paths:
    M target-sparc/translate.c

  Log Message:
  -----------
  target-sparc: Allow 4-byte alignment on fp mem ops

The cpu is allowed to require stricter alignment on these 8- and 16-byte
operations, and the OS is required to fix up the accesses as necessary,
so the previous code was not wrong.

However, we can easily handle this misalignment for all direct 8-byte
operations and for direct 16-byte loads.

We must retain 16-byte alignment for 16-byte stores, so that we don't have
to probe for writability of a second page before performing the first of
two 8-byte stores.  We also retain 8-byte alignment for no-fault loads,
since they are rare and it's not worth extending the helpers for this.

Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 47b2696b975b794c6fa7b9fa8ae4699e749d662c
      
https://github.com/qemu/qemu/commit/47b2696b975b794c6fa7b9fa8ae4699e749d662c
  Author: Richard Henderson <address@hidden>
  Date:   2016-10-31 (Mon, 31 Oct 2016)

  Changed paths:
    M target-sparc/cpu.h

  Log Message:
  -----------
  target-sparc: Remove MMU_MODE*_SUFFIX

The functions that these generate are no longer used.

Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: da1bcae65288bdd51e0a7203d1e6c9cde1be5b3d
      
https://github.com/qemu/qemu/commit/da1bcae65288bdd51e0a7203d1e6c9cde1be5b3d
  Author: Richard Henderson <address@hidden>
  Date:   2016-10-31 (Mon, 31 Oct 2016)

  Changed paths:
    M target-sparc/translate.c

  Log Message:
  -----------
  target-sparc: Use tcg_gen_atomic_xchg_tl

Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 5a7267b6a9e94c264ca77a7ca5a239e70dac81da
      
https://github.com/qemu/qemu/commit/5a7267b6a9e94c264ca77a7ca5a239e70dac81da
  Author: Richard Henderson <address@hidden>
  Date:   2016-10-31 (Mon, 31 Oct 2016)

  Changed paths:
    M target-sparc/translate.c

  Log Message:
  -----------
  target-sparc: Use tcg_gen_atomic_cmpxchg_tl

Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: bf99fd3983d7185178a0f65ce29bb94b1aecaed1
      
https://github.com/qemu/qemu/commit/bf99fd3983d7185178a0f65ce29bb94b1aecaed1
  Author: Peter Maydell <address@hidden>
  Date:   2016-11-01 (Tue, 01 Nov 2016)

  Changed paths:
    M target-sparc/cpu.h
    M target-sparc/helper.c
    M target-sparc/helper.h
    M target-sparc/ldst_helper.c
    M target-sparc/mmu_helper.c
    M target-sparc/translate.c
    M target-sparc/win_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-sparc-20161031-2' into 
staging

target-sparc updates for atomics and alignment

# gpg: Signature made Mon 31 Oct 2016 20:47:57 GMT
# gpg:                using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <address@hidden>"
# gpg:                 aka "Richard Henderson <address@hidden>"
# gpg:                 aka "Richard Henderson <address@hidden>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC  16A4 AD12 70CC 4DD0 279B

* remotes/rth/tags/pull-sparc-20161031-2:
  target-sparc: Use tcg_gen_atomic_cmpxchg_tl
  target-sparc: Use tcg_gen_atomic_xchg_tl
  target-sparc: Remove MMU_MODE*_SUFFIX
  target-sparc: Allow 4-byte alignment on fp mem ops
  target-sparc: Implement ldqf and stqf inline
  target-sparc: Remove asi helper code handled inline
  target-sparc: Implement BCOPY/BFILL inline
  target-sparc: Implement cas_asi/casx_asi inline
  target-sparc: Implement ldstub_asi inline
  target-sparc: Implement swap_asi inline
  target-sparc: Handle more twinx asis
  target-sparc: Use MMU_PHYS_IDX for bypass asis
  target-sparc: Add MMU_PHYS_IDX
  target-sparc: Introduce cpu_raise_exception_ra
  target-sparc: Use overalignment flags for twinx and block asis

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/0e356366516b...bf99fd3983d7
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