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[Qemu-commits] [qemu/qemu] f77d4f: pseries: Update SLOF firmware image t
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[Qemu-commits] [qemu/qemu] f77d4f: pseries: Update SLOF firmware image to 20161019 |
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Date: |
Fri, 28 Oct 2016 09:30:06 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: f77d4ff8506ca4f608052486d87f8a3ed03d5202
https://github.com/qemu/qemu/commit/f77d4ff8506ca4f608052486d87f8a3ed03d5202
Author: Alexey Kardashevskiy <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
Log Message:
-----------
pseries: Update SLOF firmware image to 20161019
The main changes are:
* virtio-serial
* booting speed imrovement
* better PCI bridge support
The complete changelog is:
> virtio-serial: Fix compile error
> scsi: Remove debug functions from scsi-loader.fs
> scsi: Remove unused read-6 command
> obp-tftp: Remove the ciregs-buffer
> libnet: Simplify the net-load arguments passing
> libnet: Simplify the Forth-to-C wrapper of ping()
> Do not link libnet to net-snk anymore, and remove net-snk from board-qemu
> Add a Forth-to-C wrapper for the ping command, too
> Link libnet code to Paflof and add a wrapper for netboot()
> Remember execution tokens of "write" and "read" for socket operations
> Add virtio-serial device support
> Generalize output banner write routine
> Improve indentation in OF.fs
> scsi: implement READ (16) command
> rtas: Improve rtas-do-config-@ and rtas-do-config-! a little bit
> libnet: Make netapps.h includable from .code files
> libnet: Remove unused prototypes from netapps.h
> libnet: Fix the printout of the ping command
> libnet: Make sure to close sockets when we're done
> scsi: implement read-capacity-16
> pci: Fix secondary and subordinate PCI bus enumeration with board-qemu
> pci-phb: Fix stack underflow in phb-pci-walk-bridge
> paflof: Add a read() function to read keyboard input
> paflof: Add socket(), send() and recv() functions to paflof
> paflof: Provide get_timer() and set_timer() helper functions
> paflof: Add a write_mm_log helper function
> paflof: Copy sbrk code from net-snk
> paflof: Use CFLAGS from make.rules instead of completely redefining them
> Do not include the FCode evaluator by default anymore
> Source code beautification of board-qemu/slof/pci-interrupts.fs
> Allow PCI devices in PCI bridge slots greater than 4
> Fix bad interrupt pin numbering in interrupt-map property of PCI bridges
> Improve SLOF_alloc_mem_aligned()
> instance: Fix set-my-args for empty arguments
> Fix remaining compiler warnings in sloffs.c
> Remove misleading padding fields from ROM header definition
> Improve indentation in calculatecrc.h
> Do not include calculatecrc.h from assembler files
> Remove unused defines in calculatecrc.h
> libnet: Re-initialize global variables at the beginning of tftp()
> Remove dependency on cpu/@0 for booting
> usb: Set XHCI slot speed according to port status
> usb: Build correct route string for USB3 devices behind a hub
> usb: Initialize USB3 devices on a hub and keep track of hub topology
> usb: Increase amount of maximum slot IDs and add a sanity check
> usb: Move XHCI port state arrays from header to .c file
> tools: add copy functionality
> tools: added support to sloffs to read from /dev/slof_flash
> tools: added file append functionality
> tools: use crc checking code from romfs/tools
> tools: added initial version of sloffs
> romfs: factored out crc code, to make it usable from other locations
> tools: remove unused parts from the Makefile
> usb-hid: Fix non-working comma key
> fat-files: Fix access to FAT32 dir/files when cluster > 16-bits
> virtio-net: fix ring handling in receive
> net: Remove remainders of the MTFTP code
> net: Move also files from clients/net-snk/app/netapps/ to lib/libnet/
> net: Move files from clients/net-snk/app/netlib/ to lib/libnet/
> net-snk: Get rid of netlib and netapps prefixes in include statements
> usb-xhci: assign field4 before conditional
> Improve F12 key handling in boot menu
> Fix stack underflow that occurs with duplicated ESC in input
> rtas-nvram: optimize erase
> ipv6: Replace magic number 1500 with ETH_MTU_SIZE (i.e. 1518)
> ipv6: Fix NULL pointer dereference in ip6addr_add()
> ipv6: Fix memory leak in set_ipv6_address() / ip6_create_ll_address()
> ipv6: Clear memory after malloc if necessary
> ipv6: Fix possible NULL-pointer dereference in send_ipv6()
> ping: use gateway address for routing
> ping: add netmask in the ping argument
> xhci: fix missing keys from keyboard
> xhci: add memory barrier after filling the trb
> loaders: Remove netflash command
> boot: Remove legacy Forth words for network loading
> base: Move cnt-bits and bcd-to-bin to board-js2x folder
> base: Move huge-tftp-load variable to obp-tftp package
> base: Remove unused IP address conversion functions
> virtio: White space cleanup in virtio-9p.c
> virtio: Add modern version 1.0 support to 9p driver
> virtio: Set a proper name for virtio-9p device tree nodes
> pci: Fix mistype in "unkown-bridge"
> ipv6: Indent code with tabs, not with spaces
> ipv6: send_ipv6() has to return after doing NDP
> ipv6: Do not use unitialized MAC address array
> ipv6: Add support for sending packets through a router
> Remove unused sms code.
> virtio-net: initialize to populate mac address
> libbootmsg: Do not use '\b' characters when printing checkpoints
> dev-null: The "read" function has to return 0 if nothing has been read
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b1fc72f0fb0aeae4194ff89c454aabe019983d0d
https://github.com/qemu/qemu/commit/b1fc72f0fb0aeae4194ff89c454aabe019983d0d
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/intc/xics.c
Log Message:
-----------
ppc/xics: Add xics to the monitor "info pic" command
Useful to debug interrupt problems.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: - updated for qemu-2.7
- added a test on ->irqs as it is not necessarily allocated
(PHB3_MSI)
- removed static variable g_xics and replace with a loop on all
children to find the xics objects.
- rebased on InterruptStatsProvider interface ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f62e0bbb39eec088ff4fbe6a7ec38af51fac5e94
https://github.com/qemu/qemu/commit/f62e0bbb39eec088ff4fbe6a7ec38af51fac5e94
Author: Laurent Vivier <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/virtio-scsi-test.c
Log Message:
-----------
tests: fix memory leak in virtio-scsi-test
vs is allocated in qvirtio_scsi_pci_init() and never freed.
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 458f3b2c953bdc7110896cb3691251023652523f
https://github.com/qemu/qemu/commit/458f3b2c953bdc7110896cb3691251023652523f
Author: Laurent Vivier <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/libqos/libqos.c
M tests/rtas-test.c
Log Message:
-----------
tests: don't check if qtest_spapr_boot() returns NULL
qtest_spapr_boot()/qtest_pc_boot()/qtest_boot() call qtest_vboot()
and qtest_vboot() calls g_malloc(),
and g_malloc() never fails:
if memory allocation fails, the application is terminated.
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 6b9cdf4cf1fd52c1a59a7640a02a718176bfd217
https://github.com/qemu/qemu/commit/6b9cdf4cf1fd52c1a59a7640a02a718176bfd217
Author: Laurent Vivier <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/libqos/virtio-mmio.c
M tests/libqos/virtio-pci.c
M tests/libqos/virtio.c
M tests/libqos/virtio.h
M tests/vhost-user-test.c
M tests/virtio-9p-test.c
M tests/virtio-blk-test.c
M tests/virtio-net-test.c
M tests/virtio-scsi-test.c
Log Message:
-----------
tests: move QVirtioBus pointer into QVirtioDevice
This allows to not have to pass bus and device for every virtio functions.
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
[dwg: Fix style nit]
Signed-off-by: David Gibson <address@hidden>
Commit: 8b4b80c37630e976f2dd02a7d42bd9bea1ce676e
https://github.com/qemu/qemu/commit/8b4b80c37630e976f2dd02a7d42bd9bea1ce676e
Author: Laurent Vivier <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/libqos/virtio-pci.c
M tests/libqos/virtio.h
M tests/libqtest.h
M tests/virtio-blk-test.c
Log Message:
-----------
tests: rename target_big_endian() as qvirtio_is_big_endian()
Move the definition to libqos/virtio.h as it must be used
only with virtio functions.
Add a QVirtioDevice parameter as it will be needed to
know if the virtio device is using virtio 1.0 specification
and thus is always little-endian (to do)
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a980f7f2c2f4d7e9a1eba4f804cd66dbd458b6d4
https://github.com/qemu/qemu/commit/a980f7f2c2f4d7e9a1eba4f804cd66dbd458b6d4
Author: Laurent Vivier <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/virtio-9p-test.c
M tests/virtio-blk-test.c
M tests/virtio-net-test.c
M tests/virtio-scsi-test.c
Log Message:
-----------
tests: use qtest_pc_boot()/qtest_shutdown() in virtio tests
This patch replaces calls to qtest_start() and qtest_end() by
calls to qtest_pc_boot() and qtest_shutdown().
This allows to initialize memory allocator and PCI interface
functions. This will ease to enable virtio tests on other
architectures by only adding a specific qtest_XXX_boot() (like
qtest_spapr_boot()).
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 30ca440eec9fe1d7eec5a48addac656438778278
https://github.com/qemu/qemu/commit/30ca440eec9fe1d7eec5a48addac656438778278
Author: Laurent Vivier <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/Makefile.include
M tests/libqos/virtio-pci.c
M tests/virtio-9p-test.c
M tests/virtio-blk-test.c
M tests/virtio-net-test.c
M tests/virtio-rng-test.c
M tests/virtio-scsi-test.c
Log Message:
-----------
tests: enable virtio tests on SPAPR
but disable MSI-X tests on SPAPR as we can't check the result
(the memory region used on PC is not readable on SPAPR).
Signed-off-by: Laurent Vivier <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 4bcfa56ca9f6970974255dd5621b08e5aa9e5af5
https://github.com/qemu/qemu/commit/4bcfa56ca9f6970974255dd5621b08e5aa9e5af5
Author: Michael Roth <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr_pci.c
Log Message:
-----------
spapr_pci: advertise explicit numa IDs even when there's 1 node
With the addition of "numa_node" properties for PHBs we began
advertising NUMA affinity in cases where nb_numa_nodes > 1.
Since the default on the guest side is to make no assumptions about
PHB NUMA affinity (defaulting to -1), there is still a valid use-case
for explicitly defining a PHB's NUMA affinity even when there's just
one node. In particular, some workloads make faulty assumptions about
/sys/bus/pci/<devid>/numa_node being >= 0, warranting the use of
this property as a workaround even if there's just 1 PHB or NUMA
node.
Enable this use-case by always advertising the PHB's NUMA affinity
if "numa_node" has been explicitly set.
We could achieve this by relaxing the check to simply be
nb_numa_nodes > 0, but even safer would be to check
numa_info[nodeid].present explicitly, and to fail at start time
for cases where it does not exist.
This has an additional affect of no longer advertising PHB NUMA
affinity unconditionally if nb_numa_nodes > 1 and "numa_node"
property is unset/-1, but since the default value on the guest
side for each PHB is also -1, the behavior should be the same for
that situation. We could still retain the old behavior if desired,
but the decision seems arbitrary, so we take the simpler route.
Cc: Alexey Kardashevskiy <address@hidden>
Cc: Shivaprasad G. Bhat <address@hidden>
Signed-off-by: Michael Roth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 55d9950aaa8e87372cfae2a7efc810f078f36818
https://github.com/qemu/qemu/commit/55d9950aaa8e87372cfae2a7efc810f078f36818
Author: Thomas Huth <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/nvram/Makefile.objs
A hw/nvram/chrp_nvram.c
M hw/nvram/mac_nvram.c
A include/hw/nvram/chrp_nvram.h
Log Message:
-----------
nvram: Introduce helper functions for CHRP "system" and "free space"
partitions
The "system partition" and "free space" partition layouts are
defined by the CHRP and LoPAPR specification, and used by
OpenBIOS and SLOF. We can re-use this code for other machines
that use OpenBIOS and SLOF, too. So let's make this code independent
from the MAC NVRAM environment and put it into two proper helper
functions.
Signed-off-by: Thomas Huth <address@hidden>
Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2024c01421eb990e7043afa0e0e4d67f4477596f
https://github.com/qemu/qemu/commit/2024c01421eb990e7043afa0e0e4d67f4477596f
Author: Thomas Huth <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/sparc/sun4m.c
M hw/sparc64/sun4u.c
Log Message:
-----------
sparc: Use the new common NVRAM functions for system and free space partition
The system and free space NVRAM partitions (for OpenBIOS) are created
in exactly the same way as the Mac-style CHRP NVRAM partitions, so we
can use the new common helper functions to do this job here, too.
Signed-off-by: Thomas Huth <address@hidden>
Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ad723fe5a050b685e496f2202a919f9e32c45c43
https://github.com/qemu/qemu/commit/ad723fe5a050b685e496f2202a919f9e32c45c43
Author: Thomas Huth <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/nvram/chrp_nvram.c
M hw/nvram/mac_nvram.c
M include/hw/nvram/chrp_nvram.h
M include/hw/nvram/openbios_firmware_abi.h
M tests/postcopy-test.c
Log Message:
-----------
nvram: Move the remaining CHRP NVRAM related code to chrp_nvram.[ch]
Everything that is related to CHRP NVRAM should rather reside in
chrp_nvram.c / chrp_nvram.h instead of openbios_firmware_abi.h.
Signed-off-by: Thomas Huth <address@hidden>
Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c6363bae1731754a7153bf8b08c616f52c635304
https://github.com/qemu/qemu/commit/c6363bae1731754a7153bf8b08c616f52c635304
Author: Thomas Huth <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/sparc/sun4m.c
M hw/sparc64/sun4u.c
R include/hw/nvram/openbios_firmware_abi.h
A include/hw/nvram/sun_nvram.h
Log Message:
-----------
nvram: Rename openbios_firmware_abi.h into sun_nvram.h
The header now only contains inline functions related to the
Sun NVRAM, so the a name like sun_nvram.h seems to be more
appropriate now.
Signed-off-by: Thomas Huth <address@hidden>
Tested-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: cc8b6e76e3d924de7a4413706a3749e413ccf6fb
https://github.com/qemu/qemu/commit/cc8b6e76e3d924de7a4413706a3749e413ccf6fb
Author: Nikunj A Dadhania <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M target-ppc/helper.h
M target-ppc/int_helper.c
M target-ppc/translate/vmx-impl.inc.c
M target-ppc/translate/vmx-ops.inc.c
Log Message:
-----------
target-ppc: implement vnegw/d instructions
Vector Integer Negate Instructions:
vnegw: Vector Negate Word
vnegd: Vector Negate Doubleword
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 14fd8ab26752c725b16766c823952e3138924293
https://github.com/qemu/qemu/commit/14fd8ab26752c725b16766c823952e3138924293
Author: Nikunj A Dadhania <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M target-ppc/translate.c
M target-ppc/translate/vsx-impl.inc.c
M target-ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: implement xxbr[qdwh] instruction
Add required helpers (GEN_XX2FORM_EO) for supporting this instruction.
xxbrh: VSX Vector Byte-Reverse Halfword
xxbrw: VSX Vector Byte-Reverse Word
xxbrd: VSX Vector Byte-Reverse Doubleword
xxbrq: VSX Vector Byte-Reverse Quadword
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2bb0d10aebf2018d98b9413ab960dc8d728b2f5a
https://github.com/qemu/qemu/commit/2bb0d10aebf2018d98b9413ab960dc8d728b2f5a
Author: Cédric Le Goater <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/intc/xics.c
M hw/intc/xics_kvm.c
M hw/intc/xics_spapr.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: add a xics_set_nr_servers common routine
xics_spapr and xics_kvm nearly define the same 'set_nr_servers'
handler. Only the type of the ICP differs. So let's make a common one
to remove some duplicated code.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d49c603b37e6c9d025f58c09f55d0c7cefe88987
https://github.com/qemu/qemu/commit/d49c603b37e6c9d025f58c09f55d0c7cefe88987
Author: Cédric Le Goater <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/intc/xics.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: add a XICSState backlink in ICPState
The link will be used to change the API of the icp_* routines which
are still using an XICSState as an argument.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e3403258a20c61859ca1917bb86bc206e5846784
https://github.com/qemu/qemu/commit/e3403258a20c61859ca1917bb86bc206e5846784
Author: Cédric Le Goater <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/intc/xics.c
M hw/intc/xics_spapr.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: change the icp_ routines API to use an 'ICPState *' argument
The routines :
void icp_set_cppr(ICPState *icp, uint8_t cppr);
void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
void icp_eoi(ICPState *icp, uint32_t xirr);
now use one 'ICPState *icp' argument instead of a 'XICSState *' and a
server arguments. The backlink on XICSState* is used whenever needed.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f85bcec31ee578eccf6182be158d6ac6d9b90a4c
https://github.com/qemu/qemu/commit/f85bcec31ee578eccf6182be158d6ac6d9b90a4c
Author: Nicholas Piggin <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M target-ppc/excp_helper.c
Log Message:
-----------
ppc: fix MSR_ME handling for system reset interrupt
Power ISA specifies ME bit handling for system reset interrupt:
if the interrupt occurred while the thread was in power-saving
mode, set to 1; otherwise not altered
Power ISA 3.0, section 6.5 "Interrupt Definitions", Figure 64.
Signed-off-by: Nicholas Piggin <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e763da234454c2bcdf065e360f69ca1d11d81224
https://github.com/qemu/qemu/commit/e763da234454c2bcdf065e360f69ca1d11d81224
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M include/hw/ppc/spapr_vio.h
Log Message:
-----------
pseries: Remove unused callbacks from sPAPR VIO bus state
The original QOMification of the spapr VIO devices in 3954d33 "spapr:
convert to QEMU Object Model (v2)" moved some callbacks from the
VIOsPAPRBus structure to the VIOsPAPRDeviceClass. Except, that it
forgot to actually remove them from the VIOsPAPRBus structure (which
still exists, though it doesn't fulfill quite the same function as it
did pre-QOM).
This patch removes those now unused callback fields.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Commit: 1f0e657d3f108c4cbd0ae16cf18de8dcb801cc1a
https://github.com/qemu/qemu/commit/1f0e657d3f108c4cbd0ae16cf18de8dcb801cc1a
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
ppc: Fix single step with gdb stub
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: bcad45de6a0b5bf10a274872d2e45da3403232da
https://github.com/qemu/qemu/commit/bcad45de6a0b5bf10a274872d2e45da3403232da
Author: Cédric Le Goater <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M .gitmodules
M MAINTAINERS
M Makefile
M pc-bios/README
A pc-bios/skiboot.lid
M roms/Makefile
A roms/skiboot
Log Message:
-----------
ppc: add skiboot firmware for the pnv platform
This is the initial image of skiboot 5.3.7 (commit 762d0082) for
the PowerPC PowerNV (Non-Virtualized) platform. Built from
submodule.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 225a9ab8833e5191d180e23a23b8fb381fbaf9c3
https://github.com/qemu/qemu/commit/225a9ab8833e5191d180e23a23b8fb381fbaf9c3
Author: Alexey Kardashevskiy <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M configure
Log Message:
-----------
configure, ppc64: Copy skiboot.lid to build directory when configuring
When configured to compile out of tree, the configure script
copies BIOS blobs to the build directory. However since the PPC64 powernv
machine ROM has .lid extension, it is ignored and "make check" fails
when trying the powernv machine.
This adds *.lid to the list of copied blobs.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 9e933f4a620ca485356205f5cac8a6c3db0b861d
https://github.com/qemu/qemu/commit/9e933f4a620ca485356205f5cac8a6c3db0b861d
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M default-configs/ppc64-softmmu.mak
M hw/ppc/Makefile.objs
A hw/ppc/pnv.c
A include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: add skeleton PowerNV platform
The goal is to emulate a PowerNV system at the level of the skiboot
firmware, which loads the OS and provides some runtime services. Power
Systems have a lower firmware (HostBoot) that does low level system
initialization, like DRAM training. This is beyond the scope of what
qemu will address in a PowerNV guest.
No devices yet, not even an interrupt controller. Just to get started,
some RAM to load the skiboot firmware, the kernel and initrd. The
device tree is fully created in the machine reset op.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: - updated for qemu-2.7
- replaced fprintf by error_report
- used a common definition of _FDT macro
- removed VMStateDescription as migration is not yet supported
- added IBM Copyright statements
- reworked kernel_filename handling
- merged PnvSystem and sPowerNVMachineState
- removed PHANDLE_XICP
- added ppc_create_page_sizes_prop helper
- removed nmi support
- removed kvm support
- updated powernv machine to version 2.8
- removed chips and cpus, They will be provided in another patches
- added a machine reset routine to initialize the device tree (also)
- french has a squelette and english a skeleton.
- improved commit log.
- reworked prototypes parameters
- added a check on the ram size (thanks to Michael Ellerman)
- fixed chip-id cell
- changed MAX_CPUS to 2048
- simplified memory node creation to one node only
- removed machine version
- rewrote the device tree creation with the fdt "rw" routines
- s/sPowerNVMachineState/PnvMachineState/
- etc.]
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e997040e3f02f6d1c6ab76e569f3593f5e3670fe
https://github.com/qemu/qemu/commit/e997040e3f02f6d1c6ab76e569f3593f5e3670fe
Author: Cédric Le Goater <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: add a PnvChip object
This is is an abstraction of a POWER8 chip which is a set of cores
plus other 'units', like the pervasive unit, the interrupt controller,
the memory controller, the on-chip microcontroller, etc. The whole can
be seen as a socket. It depends on a cpu model and its characteristics:
max cores and specific inits are defined in a PnvChipClass.
We start with an near empty PnvChip with only a few cpu constants
which we will grow in the subsequent patches with the controllers
required to run the system.
The Chip CFAM (Common FRU Access Module) ID gives the model of the
chip and its version number. It is generally the first thing firmwares
fetch, available at XSCOM PCB address 0xf000f, to start initialization.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 397a79e7575c4ea98507ff9d1d2629b58725d484
https://github.com/qemu/qemu/commit/397a79e7575c4ea98507ff9d1d2629b58725d484
Author: Cédric Le Goater <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: add a core mask to PnvChip
This will be used to build real HW ids for the cores and enforce some
limits on the available cores per chip.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 631adaff31d9e127fecccb4a811c20ae13cd7194
https://github.com/qemu/qemu/commit/631adaff31d9e127fecccb4a811c20ae13cd7194
Author: Cédric Le Goater <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: add a PIR handler to PnvChip
The Processor Identification Register (PIR) is a register that holds a
processor identifier which is used for bus transactions (XSCOM) and
for processor differentiation in multiprocessor systems. It also used
in the interrupt vector entries (IVE) to identify the thread serving
the interrupts.
P9 and P8 have some differences in the CPU PIR encoding.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d2fd9612eedfbfda8461d1a5f897546e3c457abb
https://github.com/qemu/qemu/commit/d2fd9612eedfbfda8461d1a5f897546e3c457abb
Author: Cédric Le Goater <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/Makefile.objs
M hw/ppc/pnv.c
A hw/ppc/pnv_core.c
M include/hw/ppc/pnv.h
A include/hw/ppc/pnv_core.h
Log Message:
-----------
ppc/pnv: add a PnvCore object
This is largy inspired by sPAPRCPUCore with some simplification, no
hotplug for instance. A set of PnvCore objects is added to the PnvChip
and the device tree is populated looping on these cores.
Real HW cpu ids are now generated depending on the chip cpu model, the
chip id and a core mask. The id is propagated to the CPU object, using
properties, to set the SPR_PIR (Processor Identification Register)
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 967b75230b9720ea2b3ae49f38f8287026125f9f
https://github.com/qemu/qemu/commit/967b75230b9720ea2b3ae49f38f8287026125f9f
Author: Cédric Le Goater <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/Makefile.objs
M hw/ppc/pnv.c
A hw/ppc/pnv_xscom.c
M include/hw/ppc/pnv.h
A include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: add XSCOM infrastructure
On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves
as a backbone to connect different units of the system. The host
firmware connects to the PIB through a bridge unit, the
Alter-Display-Unit (ADU), which gives him access to all the chiplets
on the PCB network (Pervasive Connect Bus), the PIB acting as the root
of this network.
XSCOM (serial communication) is the interface to the sideband bus
provided by the POWER8 pervasive unit to read and write to chiplets
resources. This is needed by the host firmware, OPAL and to a lesser
extent, Linux. This is among others how the PCI Host bridges get
configured at boot or how the LPC bus is accessed.
To represent the ADU of a real system, we introduce a specific
AddressSpace to dispatch XSCOM accesses to the targeted chiplets. The
translation of an XSCOM address into a PCB register address is
slightly different between the P9 and the P8. This is handled before
the dispatch using a 8byte alignment for all.
To customize the device tree, a QOM InterfaceClass, PnvXScomInterface,
is provided with a populate() handler. The chip populates the device
tree by simply looping on its children. Therefore, each model needing
custom nodes should not forget to declare itself as a child at
instantiation time.
Based on previous work done by :
Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
[dwg: Added cpu parameter to xscom_complete()]
Signed-off-by: David Gibson <address@hidden>
Commit: 24ece072504b8c8b03861168d601d174a7948099
https://github.com/qemu/qemu/commit/24ece072504b8c8b03861168d601d174a7948099
Author: Cédric Le Goater <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
M include/hw/ppc/pnv_core.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: add XSCOM handlers to PnvCore
Now that we are using real HW ids for the cores in PowerNV chips, we
can route the XSCOM accesses to them. We just need to attach a
specific XSCOM memory region to each core in the appropriate window
for the core number.
To start with, let's install the DTS (Digital Thermal Sensor) handlers
which should return 38°C for each core.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a3980bf51702d05690f07db2f6f07ab0f55d49b9
https://github.com/qemu/qemu/commit/a3980bf51702d05690f07db2f6f07ab0f55d49b9
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/Makefile.objs
M hw/ppc/pnv.c
A hw/ppc/pnv_lpc.c
M include/hw/ppc/pnv.h
A include/hw/ppc/pnv_lpc.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: add a LPC controller
The LPC (Low Pin Count) interface on a POWER8 is made accessible to
the system through the ADU (XSCOM interface). This interface is part
of set of units connected together via a local OPB (On-Chip Peripheral
Bus) which act as a bridge between the ADU and the off chip LPC
endpoints, like external flash modules.
The most important units of this OPB are :
- OPB Master: contains the ADU slave logic, a set of internal
registers and the logic to control the OPB.
- LPCHC (LPC HOST Controller): which implements a OPB Slave, a set of
internal registers and the LPC HOST Controller to control the LPC
interface.
Four address spaces are provided to the ADU :
- LPC Bus Firmware Memory
- LPC Bus Memory
- LPC Bus I/O (ISA bus)
- and the registers for the OPB Master and the LPC Host Controller
On POWER8, an intermediate hop is necessary to reach the OPB, through
a unit called the ECCB. OPB commands are simply mangled in ECCB write
commands.
On POWER9, the OPB master address space can be accessed via MMIO. The
logic is same but the code will be simpler as the XSCOM and ECCB hops
are not necessary anymore.
This version of the LPC controller model doesn't yet implement support
for the SerIRQ deserializer present in the Naples version of the chip
though some preliminary work is there.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: - updated for qemu-2.7
- ported on latest PowerNV patchset
- changed the XSCOM interface to fit new model
- QOMified the model
- moved the ISA hunks in another patch
- removed printf logging
- added a couple of UNIMP logging
- rewrote commit log ]
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3495b6b6101e680b6a7b27674f5d3e446b1cf013
https://github.com/qemu/qemu/commit/3495b6b6101e680b6a7b27674f5d3e446b1cf013
Author: Cédric Le Goater <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: add a ISA bus
As Qemu only supports a single instance of the ISA bus, we use the LPC
controller of chip 0 to create one and plug in a couple of useful
devices, like an UART and RTC. An IPMI BT device, which is also an ISA
device, can be defined on the command line to connect an external BMC.
That is for later.
The PowerNV machine now has a console. Skiboot should load a kernel
and jump into it but execution will stop quite early because we lack a
model for the native XICS controller for the moment :
[ 0.000000] NR_IRQS:512 nr_irqs:512 16
[ 0.000000] XICS: Cannot find a Presentation Controller !
[ 0.000000] ------------[ cut here ]------------
[ 0.000000] WARNING: at arch/powerpc/platforms/powernv/setup.c:81
...
[ 0.000000] NIP [c00000000079d65c] pnv_init_IRQ+0x30/0x44
You can still do a few things under xmon.
Based on previous work from :
Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[dwg: Trivial fix for a change in the serial_hds_isa_init() interface]
Signed-off-by: David Gibson <address@hidden>
Commit: 37ad52ba7ae415e7a78676aa7bb5e9f4fc6c8030
https://github.com/qemu/qemu/commit/37ad52ba7ae415e7a78676aa7bb5e9f4fc6c8030
Author: Vasant Hegde <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M target-ppc/translate/vmx-impl.inc.c
M target-ppc/translate/vmx-ops.inc.c
Log Message:
-----------
target-ppc: add vmul10[u,eu,cu,ecu]q instructions
vmul10uq : Vector Multiply-by-10 Unsigned Quadword VX-form
vmul10euq : Vector Multiply-by-10 Extended Unsigned Quadword VX-form
vmul10cuq : Vector Multiply-by-10 & write Carry Unsigned Quadword VX-form
vmul10ecuq: Vector Multiply-by-10 Extended & write Carry Unsigned Quadword
VX-form
Signed-off-by: Vasant Hegde <address@hidden>
[ Add GEN_VXFORM_DUAL_EXT with invalid bit mask ]
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 997b6cfc3d13aa145fcdbf294521e581d6617bde
https://github.com/qemu/qemu/commit/997b6cfc3d13aa145fcdbf294521e581d6617bde
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
Log Message:
-----------
pseries: Split device tree construction from device tree load
spapr_finalize_fdt() both finishes building the device tree for the guest
and loads it into guest memory. For future cleanups, it's going to be
more convenient to do these two things separately. The loading portion is
pretty trivial, so we move it inline into the caller, ppc_spapr_reset().
We also rename spapr_finalize_fdt(), because the current name is going to
become inaccurate.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Michael Roth <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Commit: cae172ab6daa18e1edc789c237a11d6dbc858ee0
https://github.com/qemu/qemu/commit/cae172ab6daa18e1edc789c237a11d6dbc858ee0
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
Log Message:
-----------
pseries: Remove rtas_addr and fdt_addr fields from machinestate
These values are used only within ppc_spapr_reset(), so just change them
to local variables.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Michael Roth <address@hidden>
Commit: a19f7fb0456b3d1329a2086d81418a49c1eae9b9
https://github.com/qemu/qemu/commit/a19f7fb0456b3d1329a2086d81418a49c1eae9b9
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
Log Message:
-----------
pseries: Make spapr_create_fdt_skel() get information from machine state
Currently spapr_create_fdt_skel() takes a bunch of individual parameters
for various things it will put in the device tree. Some of these can
already be taken directly from sPAPRMachineState. This patch alters it so
that all of them can be taken from there, which will allow this code to
be moved away from its current caller in future.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Michael Roth <address@hidden>
Commit: cf6e522390126bdd20406481f3df79c194a431bd
https://github.com/qemu/qemu/commit/cf6e522390126bdd20406481f3df79c194a431bd
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
pseries: Move adding of fdt reserve map entries
The flattened device tree passed to pseries guests contains a list of
reserved memory areas. Currently we construct this list early in
spapr_create_fdt_skel() as we sequentially write the fdt.
This will be inconvenient for upcoming cleanups, so this patch moves
the reserve map changes to the end of fdt construction. This changes
fdt_add_reservemap_entry() calls - which work when writing the fdt
sequentially to fdt_add_mem_rsv() calls used when altering the fdt in
random access mode.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Michael Roth <address@hidden>
Commit: 2cac78c12ade9a87b6251f8d854c2e43a30f41bf
https://github.com/qemu/qemu/commit/2cac78c12ade9a87b6251f8d854c2e43a30f41bf
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_rtas.c
M include/hw/ppc/spapr.h
Log Message:
-----------
pseries: Consolidate RTAS loading
At each system reset, the pseries machine needs to load RTAS (the runtime
portion of the guest firmware) into the VM. This means copying
the actual RTAS code into guest memory, and also updating the device
tree so that the guest OS and boot firmware can locate it.
For historical reasons the copy and update to the device tree were in
different parts of the code. This cleanup brings them both together in
an spapr_load_rtas() function.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Michael Roth <address@hidden>
Commit: 9b9a19080a6e548b91420ce7925f2ac81ef63ae8
https://github.com/qemu/qemu/commit/9b9a19080a6e548b91420ce7925f2ac81ef63ae8
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/intc/xics_spapr.c
M hw/ppc/spapr.c
M include/hw/ppc/xics.h
Log Message:
-----------
pseries: Move construction of /interrupt-controller fdt node
Currently the device tree node for the XICS interrupt controller is in
spapr_create_fdt_skel(). As part of consolidating device tree construction
to reset time, this moves it to a function called from spapr_build_fdt().
In addition we move the actual code into hw/intc/xics_spapr.c with the
rest of the PAPR specific interrupt controller code.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Michael Roth <address@hidden>
Commit: 7c866c6a600e435cf92f764b831d9cb3234ca0b4
https://github.com/qemu/qemu/commit/7c866c6a600e435cf92f764b831d9cb3234ca0b4
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_vio.c
M include/hw/ppc/spapr_vio.h
Log Message:
-----------
pseries: Consolidate construction of /chosen device tree node
For historical reasons, building the /chosen node in the guest device tree
is split across several places and includes both parts which write the DT
sequentially and others which use random access functions.
This patch consolidates construction of the node into one place, using
random access functions throughout.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Michael Roth <address@hidden>
Commit: 3f5dabceba246e502555a9046b98174d7548e696
https://github.com/qemu/qemu/commit/3f5dabceba246e502555a9046b98174d7548e696
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_rtas.c
M include/hw/ppc/spapr.h
Log Message:
-----------
pseries: Consolidate construction of /rtas device tree node
For historical reasons construction of the /rtas node in the device
tree (amongst others) is split into several places. In particular
it's split between spapr_create_fdt_skel(), spapr_build_fdt() and
spapr_rtas_device_tree_setup().
In fact, as well as adding the actual RTAS tokens to the device tree,
spapr_rtas_device_tree_setup() just adds the ibm,lrdr-capacity
property, which despite going in the /rtas node, doesn't have a lot to
do with RTAS.
This patch consolidates the code constructing /rtas together into a new
spapr_dt_rtas() function. spapr_rtas_device_tree_setup() is renamed to
spapr_dt_rtas_tokens() and now only adds the token properties.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Michael Roth <address@hidden>
Commit: ffb1e275a67cfeb957d0d0df2ec1f0999e321f69
https://github.com/qemu/qemu/commit/ffb1e275a67cfeb957d0d0df2ec1f0999e321f69
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_events.c
M include/hw/ppc/spapr.h
Log Message:
-----------
pseries: Move /event-sources construction to spapr_build_fdt()
The /event-sources device tree node is built from spapr_create_fdt_skel().
As part of consolidating device tree construction to reset time, this moves
it to spapr_build_fdt().
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Michael Roth <address@hidden>
Commit: fca5f2dc6ca03afa78a11835a9a6b6d223fa4575
https://github.com/qemu/qemu/commit/fca5f2dc6ca03afa78a11835a9a6b6d223fa4575
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
pseries: Move /hypervisor node construction to fdt_build_fdt()
Currently the /hypervisor device tree node is constructed in
spapr_create_fdt_skel(). As part of consolidating device tree construction
to reset time, move it to a function called from spapr_build_fdt().
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Michael Roth <address@hidden>
Commit: bf5a6696ba95ee6efa29489dd7d53b6fbcf18469
https://github.com/qemu/qemu/commit/bf5a6696ba95ee6efa29489dd7d53b6fbcf18469
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_vio.c
M include/hw/ppc/spapr_vio.h
Log Message:
-----------
pseries: Consolidate construction of /vdevice device tree node
Construction of the /vdevice node (and its children) is divided between
spapr_create_fdt_skel() (at init time), which creates the base node, and
spapr_populate_vdevice() (at reset time) which creates the nodes for each
individual virtual device.
This consolidates both into a single function called from
spapr_build_fdt().
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Michael Roth <address@hidden>
Commit: 398a0bd5ae7e03b5b9bdde1dc76451ff57471a55
https://github.com/qemu/qemu/commit/398a0bd5ae7e03b5b9bdde1dc76451ff57471a55
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
Log Message:
-----------
pseries: Remove spapr_create_fdt_skel()
For historical reasons construction of the guest device tree in spapr is
divided between spapr_create_fdt_skel() which is called at init time, and
spapr_build_fdt() which runs at reset time. Over time, more and more
things have needed to be moved to reset time.
Previous cleanups mean the only things left in spapr_create_fdt_skel() are
the properties of the root node itself. Finish consolidating these two
parts of device tree construction, by moving this to the start of
spapr_build_fdt(), and removing spapr_create_fdt_skel() entirely.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Michael Roth <address@hidden>
Commit: b20b7b7adda4e2228892670a94e0a4af41c065b9
https://github.com/qemu/qemu/commit/b20b7b7adda4e2228892670a94e0a4af41c065b9
Author: Michael Roth <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/Makefile.objs
A hw/ppc/spapr_ovec.c
A include/hw/ppc/spapr_ovec.h
Log Message:
-----------
spapr_ovec: initial implementation of option vector helpers
PAPR guests advertise their capabilities to the platform by passing
an ibm,architecture-vec structure via an
ibm,client-architecture-support hcall as described by LoPAPR v11,
B.6.2.3. during early boot.
Using this information, the platform enables the capabilities it
supports, then encodes a subset of those enabled capabilities (the
5th option vector of the ibm,architecture-vec structure passed to
ibm,client-architecture-support) into the guest device tree via
"/chosen/ibm,architecture-vec-5".
The logical format of these these option vectors is a bit-vector,
where individual bits are addressed/documented based on the byte-wise
offset from the beginning of the bit-vector, followed by the bit-wise
index starting from the byte-wise offset. Thus the bits of each of
these bytes are stored in reverse order. Additionally, the first
byte of each option vector is encodes the length of the option vector,
so byte offsets begin at 1, and bit offset at 0.
This is not very intuitive for the purposes of mapping these bits to
a particular documented capability, so this patch introduces a set
of abstractions that encapsulate the work of parsing/encoding these
options vectors and testing for individual capabilities.
Cc: Bharata B Rao <address@hidden>
Signed-off-by: Michael Roth <address@hidden>
[dwg: Tweaked double-include protection to not trigger a checkpatch
false positive]
Signed-off-by: David Gibson <address@hidden>
Commit: facdb8b63baf56bc7c0ce2f16a32900866889f03
https://github.com/qemu/qemu/commit/facdb8b63baf56bc7c0ce2f16a32900866889f03
Author: Michael Roth <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_ovec.h
Log Message:
-----------
spapr_hcall: use spapr_ovec_* interfaces for CAS options
Currently we access individual bytes of an option vector via
ldub_phys() to test for the presence of a particular capability
within that byte. Currently this is only done for the "dynamic
reconfiguration memory" capability bit. If that bit is present,
we pass a boolean value to spapr_h_cas_compose_response()
to generate a modified device tree segment with the additional
properties required to enable this functionality.
As more capability bits are added, will would need to modify the
code to add additional option vector accesses and extend the
param list for spapr_h_cas_compose_response() to include similar
boolean values for these parameters.
Avoid this by switching to spapr_ovec_* helpers so we can do all
the parsing in one shot and then test for these additional bits
within spapr_h_cas_compose_response() directly.
Cc: Bharata B Rao <address@hidden>
Signed-off-by: Michael Roth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Reviewed-by: Bharata B Rao <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 6787d27b04a79524c547c60701400eb0418e3533
https://github.com/qemu/qemu/commit/6787d27b04a79524c547c60701400eb0418e3533
Author: Michael Roth <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr: add option vector handling in CAS-generated resets
In some cases, ibm,client-architecture-support calls can fail. This
could happen in the current code for situations where the modified
device tree segment exceeds the buffer size provided by the guest
via the call parameters. In these cases, QEMU will reset, allowing
an opportunity to regenerate the device tree from scratch via
boot-time handling. There are potentially other scenarios as well,
not currently reachable in the current code, but possible in theory,
such as cases where device-tree properties or nodes need to be removed.
We currently don't handle either of these properly for option vector
capabilities however. Instead of carrying the negotiated capability
beyond the reset and creating the boot-time device tree accordingly,
we start from scratch, generating the same boot-time device tree as we
did prior to the CAS-generated and the same device tree updates as we
did before. This could (in theory) cause us to get stuck in a reset
loop. This hasn't been observed, but depending on the extensiveness
of CAS-induced device tree updates in the future, could eventually
become an issue.
Address this by pulling capability-related device tree
updates resulting from CAS calls into a common routine,
spapr_dt_cas_updates(), and adding an sPAPROptionVector*
parameter that allows us to test for newly-negotiated capabilities.
We invoke it as follows:
1) When ibm,client-architecture-support gets called, we
call spapr_dt_cas_updates() with the set of capabilities
added since the previous call to ibm,client-architecture-support.
For the initial boot, or a system reset generated by something
other than the CAS call itself, this set will consist of *all*
options supported both the platform and the guest. For calls
to ibm,client-architecture-support immediately after a CAS-induced
reset, we call spapr_dt_cas_updates() with only the set
of capabilities added since the previous call, since the other
capabilities will have already been addressed by the boot-time
device-tree this time around. In the unlikely event that
capabilities are *removed* since the previous CAS, we will
generate a CAS-induced reset. In the unlikely event that we
cannot fit the device-tree updates into the buffer provided
by the guest, well generate a CAS-induced reset.
2) When a CAS update results in the need to reset the machine and
include the updates in the boot-time device tree, we call the
spapr_dt_cas_updates() using the full set of negotiated
capabilities as part of the reset path. At initial boot, or after
a reset generated by something other than the CAS call itself,
this set will be empty, resulting in what should be the same
boot-time device-tree as we generated prior to this patch. For
CAS-induced reset, this routine will be called with the full set of
capabilities negotiated by the platform/guest in the previous
CAS call, which should result in CAS updates from previous call
being accounted for in the initial boot-time device tree.
Signed-off-by: Michael Roth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[dwg: Changed an int -> bool conversion to be more explicit]
Signed-off-by: David Gibson <address@hidden>
Commit: 417ece33fc1095f8acfa31208a5502bb8957f000
https://github.com/qemu/qemu/commit/417ece33fc1095f8acfa31208a5502bb8957f000
Author: Michael Roth <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
M include/hw/ppc/spapr_ovec.h
Log Message:
-----------
spapr: improve ibm,architecture-vec-5 property handling
ibm,architecture-vec-5 is supposed to encode all option vector 5 bits
negotiated between platform/guest. Currently we hardcode this property
in the boot-time device tree to advertise a single negotiated
capability, "Form 1" NUMA Affinity, regardless of whether or not CAS
has been invoked or that capability has actually been negotiated.
Improve this by generating ibm,architecture-vec-5 based on the full
set of option vector 5 capabilities negotiated via CAS.
Signed-off-by: Michael Roth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a37eb9fccdd423e4f430b0261ee78c1692b7c252
https://github.com/qemu/qemu/commit/a37eb9fccdd423e4f430b0261ee78c1692b7c252
Author: Hervé Poussineau <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/input/adb.c
Log Message:
-----------
adb: change handler only when recognized
ADB devices must take new handler into account only when they recognize it.
This lets operating systems probe for valid/invalid handles, to know device
capabilities.
Add a FIXME in keyboard handler, which should use a different translation
table depending of the selected handler.
Signed-off-by: Hervé Poussineau <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 246fc0fb66cbf861b0e76320626b059e2d49ea12
https://github.com/qemu/qemu/commit/246fc0fb66cbf861b0e76320626b059e2d49ea12
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/libqos/virtio-mmio.c
M tests/libqos/virtio-pci.c
M tests/virtio-9p-test.c
M tests/virtio-blk-test.c
M tests/virtio-scsi-test.c
Log Message:
-----------
libqos: Give qvirtio_config_read*() consistent semantics
The 'addr' parameter to qvirtio_config_read*() doesn't have a consistent
meaning: when using the virtio-pci versions, it's a full PCI space address,
but for virtio-mmio, it's an offset from the device's base mmio address.
This means that the callers need to do different things to calculate the
addresses in the two cases, which rather defeats the purpose of function
pointer backends.
All the current users of these functions are using them to retrieve
variables from the device specific portion of the virtio config space.
So, this patch alters the semantics to always be an offset into that
device specific config area.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: a795fc08f2636013fe097e51bdac62d089ac505a
https://github.com/qemu/qemu/commit/a795fc08f2636013fe097e51bdac62d089ac505a
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/libqos/pci-pc.c
M tests/libqos/pci-spapr.c
M tests/libqos/pci.c
M tests/libqos/pci.h
Log Message:
-----------
libqos: Handle PCI IO de-multiplexing in common code
The PCI IO space (aka PIO, aka legacy IO) and PCI memory space (aka MMIO)
are distinct address spaces by the PCI spec (although parts of one might be
aliased to parts of the other in some cases).
However, qpci_io_read*() and qpci_io_write*() can perform accesses to
either space depending on parameter. That's convenient for test case
drivers, since there are a fair few devices which can be controlled via
either a PIO or MMIO BAR but with an otherwise identical driver.
This is implemented by having addresses below 64kiB treated as PIO, and
those above treated as MMIO. This works because low addresses in memory
space are generally reserved for DMA rather than MMIO.
At the moment, this demultiplexing must be handled by each PCI backend
(pc and spapr, so far). There's no real reason for this - the current
encoding is likely to work for all platforms, and even if it doesn't we
can still use a more complex common encoding since the value returned from
iomap are semi-opaque.
This patch moves the demultiplexing into the common part of the libqos PCI
code, with the backends having simpler, separate accessors for PIO and
MMIO space. This also means we have a way of explicitly accessing either
space if it's necessary for some special case.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: b8cc4d0231b97c3dd7930d91ab91657b5a105b78
https://github.com/qemu/qemu/commit/b8cc4d0231b97c3dd7930d91ab91657b5a105b78
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/libqos/pci-pc.c
M tests/libqos/pci-spapr.c
M tests/libqos/pci.c
M tests/libqos/pci.h
Log Message:
-----------
libqos: Move BAR assignment to common code
The PCI backends in libqos each supply an iomap() and iounmap() function
which is used to set up a specified PCI BAR. But PCI BAR allocation takes
place entirely within PCI space, so doesn't really need per-backend
versions. For example, Linux includes generic BAR allocation code used on
platforms where that isn't done by firmware.
This patch merges the BAR allocation from the two existing backends into a
single simplified copy. The back ends just need to set up some parameters
describing the window of PCI IO and PCI memory addresses which are
available for allocation. Like both the existing versions the new one uses
a simple bump allocator.
Note that (again like the existing versions) this doesn't really handle
64-bit memory BARs properly. It is actually used for such a BAR by the
ivshmem test, and apparently the 32-bit MMIO BAR logic is close enough to
work, as long as the BAR isn't too big. Fixing that to properly handle
64-bit BAR allocation is a problem for another time.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: a7b85b60623a862e2c55d5a6cd2e17f5fc26b256
https://github.com/qemu/qemu/commit/a7b85b60623a862e2c55d5a6cd2e17f5fc26b256
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/libqos/pci.c
M tests/libqos/pci.h
Log Message:
-----------
libqos: Better handling of PCI legacy IO
The usual model for PCI IO with libqos is to use qpci_iomap() to map a
specific BAR for a PCI device, then perform IOs within that BAR using
qpci_io_{read,write}*().
However, certain devices also have legacy PCI IO. In this case, instead of
(or as well as) being accessed via PCI BARs, the device can be accessed
via certain well-known, fixed addresses in PCI IO space.
Two existing tests use legacy PCI IO, and take different flawed approaches
to it:
* tco-test manually constructs a tco_io_base value instead of calling
qpci_iomap(), which assumes internal knowledge of the structure of
the value it shouldn't have
* ide-test uses direct in*() and out*() calls instead of using
qpci_io_*() accessors, meaning it's not portable to non-x86 machine
types.
This patch implements a new qpci_iomap_legacy() interface which gets a
handle in the same format as qpci_iomap() but refers to a region in
the legacy PIO space. For a device which has the same registers
available both in a BAR and in legacy space (quite common), this
allows the same test code to test both options with just a different
iomap() at the beginning.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: 9ff50be2ffb3c116811cfc63dd1fa0ef8c4a9c75
https://github.com/qemu/qemu/commit/9ff50be2ffb3c116811cfc63dd1fa0ef8c4a9c75
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/tco-test.c
Log Message:
-----------
tests: Adjust tco-test to use qpci_legacy_iomap()
Avoid tco-test making assumptions about the internal format of the address
tokens passed to PCI IO accessors, by using the new qpci_legacy_iomap()
function.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: 9a84f889471de50144632100109f93aabea68ff6
https://github.com/qemu/qemu/commit/9a84f889471de50144632100109f93aabea68ff6
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/libqos/pci-pc.c
M tests/libqos/pci-spapr.c
M tests/libqos/pci.c
M tests/libqos/pci.h
Log Message:
-----------
libqos: Add streaming accessors for PCI MMIO
Currently PCI memory (aka MMIO) space is accessed via a set of readb/writeb
style accessors. This is what we want for accessing discrete registers of
a certain size. However, there are a few cases where we instead need a
"bag of bytes" style streaming interface to PCI MMIO space. This can be
either for streaming data style registers or when there's actual memory
rather than registers in PCI space, for example frame buffers or ivshmem.
This patch adds backend callbacks, and libqos wrappers for this type of
byte address order preserving accesses.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: 352d664cce514a94228fbf6e05d03920b2d6bd69
https://github.com/qemu/qemu/commit/352d664cce514a94228fbf6e05d03920b2d6bd69
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/libqos/pci-pc.c
M tests/libqos/pci-spapr.c
M tests/libqos/pci.c
M tests/libqos/pci.h
Log Message:
-----------
libqos: Implement mmio accessors in terms of mem{read,write}
In the libqos PCI code we now have accessors both for registers (byte
significance preserving) and for streaming data (byte address order
preserving). These exist in both the interface for qtest drivers and in
the machine specific backends.
However, the register-style accessors aren't actually necessary in the
backend. They can be implemented in terms of the byte address order
preserving accessors by the libqos wrappers. This works because PCI is
always little endian.
This does assume that the back end byte address order preserving accessors
will perform the equivalent of a single bus transaction for short lengths.
This is the case, and in fact they currently end up using the same
cpu_physical_memory_rw() implementation within the qtest accelerator.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: 9c268f8ae84ae18679ba2c3b16394e1828e9a006
https://github.com/qemu/qemu/commit/9c268f8ae84ae18679ba2c3b16394e1828e9a006
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/ide-test.c
Log Message:
-----------
tests: Clean up IO handling in ide-test
ide-test uses many explicit inb() / outb() operations for its IO, which
means it's not portable to non-x86 platforms. This cleans it up to use
the libqos PCI accessors instead.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: f775f45ab866f8e2d26720de9cb3c8f0ba5684d3
https://github.com/qemu/qemu/commit/f775f45ab866f8e2d26720de9cb3c8f0ba5684d3
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/libqos/pci-pc.c
M tests/libqos/pci-spapr.c
M tests/libqos/pci.c
M tests/libqos/pci.h
M tests/libqos/virtio-pci.c
Log Message:
-----------
libqos: Add 64-bit PCI IO accessors
Currently the libqos PCI layer includes accessor helpers for 8, 16 and 32
bit reads and writes. It's likely that we'll want 64-bit accesses in the
future (plenty of modern peripherals will have 64-bit reigsters). This
adds them.
For PIO (not MMIO) accesses on the PC backend, this is implemented as two
32-bit ins or outs. That's not ideal but AFAICT x86 doesn't have 64-bit
versions of in and out.
This patch also converts the single current user of 64-bit accesses -
virtio-pci.c to use the new mechanism, rather than a sequence of 8 byte
reads.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: 204e54b86d123d091f0b2d14541c491ece7b864f
https://github.com/qemu/qemu/commit/204e54b86d123d091f0b2d14541c491ece7b864f
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/ivshmem-test.c
Log Message:
-----------
tests: Use qpci_mem{read,write} in ivshmem-test
ivshmem implements a block of shared memory in a PCI BAR. Currently our
test case accesses this using qtest_mem{read,write}. However, deducing
the correct addresses for these requires making assumptions about the
internel format returned by qpci_iomap(), along with some ugly casts.
This patch changes the test to use the new qpci_mem{read,write} interfaces
which is neater.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: e7c8526b2a1482a9b14319fda9f8ad4bfda5b958
https://github.com/qemu/qemu/commit/e7c8526b2a1482a9b14319fda9f8ad4bfda5b958
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/ahci-test.c
M tests/libqos/ahci.c
M tests/libqos/ahci.h
Log Message:
-----------
tests: Don't assume structure of PCI IO base in ahci-test
In a couple of places ahci-test makes assumptions about how the tokens
returned from qpci_iomap() are formatted in ways it probably shouldn't.
First in verify_state() it uses a non-NULL token to indicate that the AHCI
device has been enabled (part of enabling is to iomap()). This changes it
to use an explicit 'enabled' flag instead.
Second, it uses the fact that the token contains a PCI address, stored when
the BAR is mapped during initialization to check that the BAR has the same
value after a migration. This changes it to explicitly read the BAR
register before and after the migration and compare.
Together, these changes will make the test more robust against changes to
the internals of the libqos PCI layer.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: John Snow <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: b4ba67d9a702507793c2724e56f98e9b0f7be02b
https://github.com/qemu/qemu/commit/b4ba67d9a702507793c2724e56f98e9b0f7be02b
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/e1000e-test.c
M tests/ide-test.c
M tests/ivshmem-test.c
M tests/libqos/ahci.c
M tests/libqos/ahci.h
M tests/libqos/pci.c
M tests/libqos/pci.h
M tests/libqos/usb.c
M tests/libqos/usb.h
M tests/libqos/virtio-pci.c
M tests/libqos/virtio-pci.h
M tests/rtl8139-test.c
M tests/tco-test.c
M tests/usb-hcd-ehci-test.c
Log Message:
-----------
libqos: Change PCI accessors to take opaque BAR handle
The usual use model for the libqos PCI functions is to map a specific PCI
BAR using qpci_iomap() then pass the returned token into IO accessor
functions. This, and the fact that iomap() returns a (void *) which
actually contains a PCI space address, kind of suggests that the return
value from iomap is supposed to be an opaque token.
..except that the callers expect to be able to add offsets to it. Which
also assumes the compiler will support pointer arithmetic on a (void *),
and treat it as working with byte offsets.
To clarify this situation change iomap() and the IO accessors to take
a definitely opaque BAR handle (enforced with a wrapper struct) along with
an offset within the BAR. This changes both the functions and all the
callers.
There were a number of places that checked if iomap() returned non-NULL,
and or initialized it to NULL before hand. Since iomap() already assert()s
if it fails to map the BAR, these tests were mostly pointless and are
removed.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: 61f20b9dc5b78c603354a4ec170079479dcb6657
https://github.com/qemu/qemu/commit/61f20b9dc5b78c603354a4ec170079479dcb6657
Author: Thomas Huth <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/nvram/spapr_nvram.c
Log Message:
-----------
spapr_nvram: Pre-initialize the NVRAM to support the -prom-env parameter
In case we do not load the NVRAM contents from a file and the user
specified the "-prom-env" parameter, use the new CHRP NVRAM helper
functions to pre-initialize the NVRAM partitions, so that the SLOF
firmware now can pick up the environment variables from the -prom-env
parameter, too.
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 53687348813196551874409fecb49c94d20b1ae6
https://github.com/qemu/qemu/commit/53687348813196551874409fecb49c94d20b1ae6
Author: David Gibson <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M tests/prom-env-test.c
Log Message:
-----------
tests: Add pseries machine to the prom-env-test, too
Now that we also support the "-prom-env" parameter for the pseries
machine, we can enable this test for this machine, too. Since booting
with TCG is rather slow with the pseries machine, we also enable
the "-nodefaults" parameter for this test now, so that SLOF does not
have to check that much devices during boot and thus runs a little
bit faster.
Signed-off-by: Thomas Huth <address@hidden>
[dwg: Don't add -nodefaults to the command line, it causes extra warnings
for the sparc testcases]
Signed-off-by: David Gibson <address@hidden>
Commit: 6d1ff9a7b396b3193eaea1983b3d7283a743e60a
https://github.com/qemu/qemu/commit/6d1ff9a7b396b3193eaea1983b3d7283a743e60a
Author: Sandipan Das <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M target-ppc/fpu_helper.c
M target-ppc/helper.h
M target-ppc/translate/vsx-impl.inc.c
M target-ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: add xscmp[eq,gt,ge,ne]dp instructions
xscmpeqdp: VSX Scalar Compare Equal Double-Precision
xscmpgedp: VSX Scalar Compare Greater Than or Equal Double-Precision
xscmpgtdp: VSX Scalar Compare Greater Than Double-Precision
xscmpnedp: VSX Scalar Compare Not Equal Double-Precision
Signed-off-by: Sandipan Das <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 6db246f93a7e308ff1d5aecf89d5772e83cafe61
https://github.com/qemu/qemu/commit/6db246f93a7e308ff1d5aecf89d5772e83cafe61
Author: Swapnil Bokade <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M target-ppc/fpu_helper.c
M target-ppc/helper.h
M target-ppc/translate/vsx-impl.inc.c
M target-ppc/translate/vsx-ops.inc.c
Log Message:
-----------
target-ppc: Add xvcmpnesp, xvcmpnedp instructions
xvcmpnedp[.]: VSX Vector Compare Not Equal Double-Precision
xvcmpnesp[.]: VSX Vector Compare Not Equal Single-Precision
Signed-off-by: Swapnil Bokade <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 9f992cca93de808bccbd02e14ce9200e8f25b8eb
https://github.com/qemu/qemu/commit/9f992cca93de808bccbd02e14ce9200e8f25b8eb
Author: Michael Roth <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M docs/specs/ppc-spapr-hotplug.txt
Log Message:
-----------
spapr: update spapr hotplug documentation
This updates the existing documentation to reflect recent updates to
the hotplug event structure, which are in draft form but slated
for inclusion in PAPR/LoPAPR.
Signed-off-by: Michael Roth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ffbb1705a33df8e2fb12b24d96663d63b22eaf8b
https://github.com/qemu/qemu/commit/ffbb1705a33df8e2fb12b24d96663d63b22eaf8b
Author: Michael Roth <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_events.c
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_ovec.h
Log Message:
-----------
spapr_events: add support for dedicated hotplug event source
Hotplug events were previously delivered using an EPOW interrupt
and were queued by linux guests into a circular buffer. For traditional
EPOW events like shutdown/resets, this isn't an issue, but for hotplug
events there are cases where this buffer can be exhausted, resulting
in the loss of hotplug events, resets, etc.
Newer-style hotplug event are delivered using a dedicated event source.
We enable this in supported guests by adding standard an additional
event source in the guest device-tree via /event-sources, and, if
the guest advertises support for the newer-style hotplug events,
using the corresponding interrupt to signal the available of
hotplug/unplug events.
Signed-off-by: Michael Roth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f622921430adbb4ac5aa641534e13e2cafae099a
https://github.com/qemu/qemu/commit/f622921430adbb4ac5aa641534e13e2cafae099a
Author: Michael Roth <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: add hotplug interrupt machine options
This adds machine options of the form:
-machine pseries,modern-hotplug-events=true
-machine pseries,modern-hotplug-events=false
If false, QEMU will force the use of "legacy" style hotplug events,
which are surfaced through EPOW events instead of a dedicated
hot plug event source, and lack certain features necessary, mainly,
for memory unplug support.
If true, QEMU will enable support for "modern" dedicated hot plug
event source. Note that we will still default to "legacy" style unless
the guest advertises support for the "modern" hotplug events via
ibm,client-architecture-support hcall during early boot.
For pseries-2.7 and earlier we default to false, for newer machine
types we default to true.
Signed-off-by: Michael Roth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: afdbd403563fe91bccc9c8ddce84838817f06a66
https://github.com/qemu/qemu/commit/afdbd403563fe91bccc9c8ddce84838817f06a66
Author: Bharata B Rao <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr_events.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr: Add DRC count indexed hotplug identifier type
Add support for DRC count indexed hotplug ID type which is primarily
needed for memory hot unplug. This type allows for specifying the
number of DRs that should be plugged/unplugged starting from a given
DRC index.
Signed-off-by: Bharata B Rao <address@hidden>
* updated rtas_event_log_v6_hp to reflect count/index field ordering
used in PAPR hotplug ACR
Signed-off-by: Michael Roth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 79b78a6bd47722ce23bc74287cd6322756698f09
https://github.com/qemu/qemu/commit/79b78a6bd47722ce23bc74287cd6322756698f09
Author: Michael Roth <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: use count+index for memory hotplug
Commit 0a417869:
spapr: Move memory hotplug to RTAS_LOG_V6_HP_ID_DRC_COUNT type
dropped per-DRC/per-LMB hotplugs event in favor of a bulk add via a
single LMB count value. This was to avoid overrunning the guest EPOW
event queue with hotplug events. This works fine, but relies on the
guest exhaustively scanning for pluggable LMBs to satisfy the
requested count by issuing rtas-get-sensor(DR_ENTITY_SENSE, ...) calls
until all the LMBs associated with the DIMM are identified.
With newer support for dedicated hotplug event source, this queue
exhaustion is no longer as much of an issue due to implementation
details on the guest side, but we still try to avoid excessive hotplug
events by now supporting both a count and a starting index to avoid
unecessary work. This patch makes use of that approach when the
capability is available.
Cc: address@hidden
Signed-off-by: Michael Roth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: cf63246319019c330a214c1ca9284c9405a6eb7a
https://github.com/qemu/qemu/commit/cf63246319019c330a214c1ca9284c9405a6eb7a
Author: Bharata B Rao <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_drc.c
Log Message:
-----------
spapr: Memory hot-unplug support
Add support to hot remove pc-dimm memory devices.
Since we're introducing a machine-level unplug_request hook, we also
had handling for CPU unplug there as well to ensure CPU unplug
continues to work as it did before.
Signed-off-by: Bharata B Rao <address@hidden>
* add hooks to CAS/cmdline enablement of hotplug ACR support
* add hook for CPU unplug
Signed-off-by: Michael Roth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 10c21b5c20bf3d20b7b0ad279db37ae89cc7937d
https://github.com/qemu/qemu/commit/10c21b5c20bf3d20b7b0ad279db37ae89cc7937d
Author: Nicholas Piggin <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M target-ppc/excp_helper.c
Log Message:
-----------
ppc: allow certain HV interrupts to be delivered to guests
ppc hypervisors have delivered system reset and machine check exception
interrupts to guests in some situations (e.g., see FWNMI feature of LoPAPR,
or NMI injection in QEMU).
These exceptions are architected to set the HV bit in hardware, however
when injected into a guest, the HV bit should be cleared. Current code
masks off the HV bit before setting the new MSR, however this happens after
the interrupt delivery model has calculated delivery mode for the exception.
This can result in the guest's MSR LE bit being lost.
Account for this in the exception handler and don't set HV bit for guest
delivery.
Also add another sanity check to ensure similar bugs get caught.
Signed-off-by: Nicholas Piggin <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 66a77ea676aea48092500bcddb015aa0aee42388
https://github.com/qemu/qemu/commit/66a77ea676aea48092500bcddb015aa0aee42388
Author: Peter Maydell <address@hidden>
Date: 2016-10-28 (Fri, 28 Oct 2016)
Changed paths:
M .gitmodules
M MAINTAINERS
M Makefile
M configure
M default-configs/ppc64-softmmu.mak
M docs/specs/ppc-spapr-hotplug.txt
M hw/input/adb.c
M hw/intc/xics.c
M hw/intc/xics_kvm.c
M hw/intc/xics_spapr.c
M hw/nvram/Makefile.objs
A hw/nvram/chrp_nvram.c
M hw/nvram/mac_nvram.c
M hw/nvram/spapr_nvram.c
M hw/ppc/Makefile.objs
A hw/ppc/pnv.c
A hw/ppc/pnv_core.c
A hw/ppc/pnv_lpc.c
A hw/ppc/pnv_xscom.c
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_drc.c
M hw/ppc/spapr_events.c
M hw/ppc/spapr_hcall.c
A hw/ppc/spapr_ovec.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_rtas.c
M hw/ppc/spapr_vio.c
M hw/sparc/sun4m.c
M hw/sparc64/sun4u.c
A include/hw/nvram/chrp_nvram.h
R include/hw/nvram/openbios_firmware_abi.h
A include/hw/nvram/sun_nvram.h
A include/hw/ppc/pnv.h
A include/hw/ppc/pnv_core.h
A include/hw/ppc/pnv_lpc.h
A include/hw/ppc/pnv_xscom.h
M include/hw/ppc/spapr.h
A include/hw/ppc/spapr_ovec.h
M include/hw/ppc/spapr_vio.h
M include/hw/ppc/xics.h
M pc-bios/README
A pc-bios/skiboot.lid
M pc-bios/slof.bin
M roms/Makefile
M roms/SLOF
A roms/skiboot
M target-ppc/excp_helper.c
M target-ppc/fpu_helper.c
M target-ppc/helper.h
M target-ppc/int_helper.c
M target-ppc/translate.c
M target-ppc/translate/vmx-impl.inc.c
M target-ppc/translate/vmx-ops.inc.c
M target-ppc/translate/vsx-impl.inc.c
M target-ppc/translate/vsx-ops.inc.c
M tests/Makefile.include
M tests/ahci-test.c
M tests/e1000e-test.c
M tests/ide-test.c
M tests/ivshmem-test.c
M tests/libqos/ahci.c
M tests/libqos/ahci.h
M tests/libqos/libqos.c
M tests/libqos/pci-pc.c
M tests/libqos/pci-spapr.c
M tests/libqos/pci.c
M tests/libqos/pci.h
M tests/libqos/usb.c
M tests/libqos/usb.h
M tests/libqos/virtio-mmio.c
M tests/libqos/virtio-pci.c
M tests/libqos/virtio-pci.h
M tests/libqos/virtio.c
M tests/libqos/virtio.h
M tests/libqtest.h
M tests/postcopy-test.c
M tests/prom-env-test.c
M tests/rtas-test.c
M tests/rtl8139-test.c
M tests/tco-test.c
M tests/usb-hcd-ehci-test.c
M tests/vhost-user-test.c
M tests/virtio-9p-test.c
M tests/virtio-blk-test.c
M tests/virtio-net-test.c
M tests/virtio-rng-test.c
M tests/virtio-scsi-test.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.8-20161028' into
staging
ppc patch queue 2016-10-28
This pull request supersedes and extends the one from 2016-10-26
(which had a build bug).
Highlights:
* SLOF (pseries guest firmware) update
* Enable a number of extra testcases on ppc / pseries
* Added the 'powernv' machine type
- Almost enough to be minimally usable
- But still missing necessary interrupt controller updates
* Cleanup and consolidation of NVRAM handling on several platforms
with related firmware
* Substantial cleanup to device tree construction
* Some more POWER9 instruction emulation
* Cleanup to handling of pseries option vectors and CAS reboot
handling (host/guest feature negotiation mechanism)
* Significant cleanups to handling of PCI devices in test cases
* New hotplug event infrastructure
* Memory hot unplug support for pseries
* Several bug fixes
The NVRAM cleanup affects some Sun sparc platforms as well as ppc
ones, but have been tested by the sparc maintainer (Mark Cave-Ayland).
The test additions also include substantial general changes to the
test framework that aren't strictly ppc related. They don't seem to
break tests on other platforms, they're for the benefit of enabling
tests on ppc and there isn't a specific maintainer for them, so
they're included in this tree.
# gpg: Signature made Fri 28 Oct 2016 02:37:19 BST
# gpg: using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg: aka "David Gibson (Red Hat) <address@hidden>"
# gpg: aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg: aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.8-20161028: (73 commits)
ppc: allow certain HV interrupts to be delivered to guests
spapr: Memory hot-unplug support
spapr: use count+index for memory hotplug
spapr: Add DRC count indexed hotplug identifier type
spapr: add hotplug interrupt machine options
spapr_events: add support for dedicated hotplug event source
spapr: update spapr hotplug documentation
target-ppc: Add xvcmpnesp, xvcmpnedp instructions
target-ppc: add xscmp[eq,gt,ge,ne]dp instructions
tests: Add pseries machine to the prom-env-test, too
spapr_nvram: Pre-initialize the NVRAM to support the -prom-env parameter
libqos: Change PCI accessors to take opaque BAR handle
tests: Don't assume structure of PCI IO base in ahci-test
tests: Use qpci_mem{read,write} in ivshmem-test
libqos: Add 64-bit PCI IO accessors
tests: Clean up IO handling in ide-test
libqos: Implement mmio accessors in terms of mem{read,write}
libqos: Add streaming accessors for PCI MMIO
tests: Adjust tco-test to use qpci_legacy_iomap()
libqos: Better handling of PCI legacy IO
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/01b601f06154...66a77ea676ae
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