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[Qemu-commits] [qemu/qemu] adb65d: migration: Remove static allocation o
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[Qemu-commits] [qemu/qemu] adb65d: migration: Remove static allocation of xzblre cach... |
Date: |
Tue, 25 Oct 2016 02:30:06 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: adb65dec4ba80ac6440aa45ca9bf409392c6da63
https://github.com/qemu/qemu/commit/adb65dec4ba80ac6440aa45ca9bf409392c6da63
Author: Vijaya Kumar K <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M migration/ram.c
Log Message:
-----------
migration: Remove static allocation of xzblre cache buffer
Allocate xzblre zero page cache buffer dynamically.
Remove dependency on TARGET_PAGE_SIZE to make run-time
page size detection for arm platforms.
Signed-off-by: Vijaya Kumar K <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 2615fabd42ea0078dd9e659bdb21a5b7a1f87a9a
https://github.com/qemu/qemu/commit/2615fabd42ea0078dd9e659bdb21a5b7a1f87a9a
Author: Vijaya Kumar K <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M exec.c
Log Message:
-----------
exec.c: Remove static allocation of sub_section of sub_page
Allocate sub_section dynamically. Remove dependency
on TARGET_PAGE_SIZE to make run-time page size detection
for arm platforms.
Signed-off-by: Vijaya Kumar K <address@hidden>
Message-id: address@hidden
[PMM: use flexible array member rather than separate malloc
so we don't need an extra pointer deref when using it]
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 66ec9f49399f0a9fa13ee77c472caba0de2773fc
https://github.com/qemu/qemu/commit/66ec9f49399f0a9fa13ee77c472caba0de2773fc
Author: Vijaya Kumar K <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M translate-all.c
Log Message:
-----------
translate-all.c: Compute L1 page table properties at runtime
Remove L1 page mapping table properties computing
statically using macros which is dependent on
TARGET_PAGE_BITS. Drop macros V_L1_SIZE, V_L1_SHIFT,
V_L1_BITS macros and replace with variables which are
computed at early stage of VM boot.
Removing dependency can help to make TARGET_PAGE_BITS
dynamic.
Signed-off-by: Vijaya Kumar K <address@hidden>
Message-id: address@hidden
[PMM:
assert(v_l1_shift % V_L2_BITS == 0)
cache v_l2_levels
initialize from page_init() rather than vl.c
minor code style fixes
put v_l1_size into a local where used as a loop limit]
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 20bccb82ff3ea09bcb7c4ee226d3160cab15f7da
https://github.com/qemu/qemu/commit/20bccb82ff3ea09bcb7c4ee226d3160cab15f7da
Author: Peter Maydell <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M exec.c
M include/exec/cpu-all.h
M include/hw/boards.h
M include/qemu-common.h
M vl.c
Log Message:
-----------
cpu: Support a target CPU having a variable page size
Support target CPUs having a page size which isn't knownn
at compile time. To use this, the CPU implementation should:
* define TARGET_PAGE_BITS_VARY
* not define TARGET_PAGE_BITS
* define TARGET_PAGE_BITS_MIN to the smallest value it
might possibly want for TARGET_PAGE_BITS
* call set_preferred_target_page_bits() in its realize
function to indicate the actual preferred target page
size for the CPU (and report any error from it)
In CONFIG_USER_ONLY, the CPU implementation should continue
to define TARGET_PAGE_BITS appropriately for the guest
OS page size.
Machines which want to take advantage of having the page
size something larger than TARGET_PAGE_BITS_MIN must
set the MachineClass minimum_page_bits field to a value
which they guarantee will be no greater than the preferred
page size for any CPU they create.
Note that changing the target page size by setting
minimum_page_bits is a migration compatibility break
for that machine.
For debugging purposes, attempts to use TARGET_PAGE_SIZE
before it has been finally confirmed will assert.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 59811a320d6b2a6db2646f908bb016dd8553df27
https://github.com/qemu/qemu/commit/59811a320d6b2a6db2646f908bb016dd8553df27
Author: Peter Maydell <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M migration/savevm.c
Log Message:
-----------
migration/savevm.c: migrate non-default page size
Add a subsection to vmstate_configuration which is present
only if the guest is using a target page size which is
different from the default. This allows us to helpfully
diagnose attempts to migrate between machines which
are using different target page sizes.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: e97da98f1173c764e8fd8d2c84f84ec3bdc87488
https://github.com/qemu/qemu/commit/e97da98f1173c764e8fd8d2c84f84ec3bdc87488
Author: Peter Maydell <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M target-arm/cpu.c
M target-arm/cpu.h
Log Message:
-----------
target-arm: Make page size a runtime setting
Rather than defining TARGET_PAGE_BITS to always be 10,
switch to using a value picked at runtime. This allows us
to use 4K pages for modern ARM CPUs (and in particular all
64-bit CPUs) without having to drop support for the old
ARMv5 CPUs which had 1K pages.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: a2519ad1828dd443af9f9c293db18db6d6123762
https://github.com/qemu/qemu/commit/a2519ad1828dd443af9f9c293db18db6d6123762
Author: Peter Maydell <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Set minimum_page_bits to 12
Since the virt board model will never create a CPU which is
pre-ARMv7, we know that our minimum page size is 4K and can
set minimum_page_bits accordingly, for improved performance.
Note that this is a migration compatibility break, so
we introduce it only for the virt-2.8 machine and onward;
virt-2.7 continues using the old 1K pages.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 2b5c0322b7d9d2032578bd1efccf72f4ab1b7074
https://github.com/qemu/qemu/commit/2b5c0322b7d9d2032578bd1efccf72f4ab1b7074
Author: Dmitry Osipenko <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M hw/core/ptimer.c
M include/hw/ptimer.h
Log Message:
-----------
hw/ptimer: Add "wraparound after one period" policy
Currently, periodic counter wraps around immediately once counter reaches
"0", this is wrong behaviour for some of the timers, resulting in one period
being lost. Add new ptimer policy that provides correct behaviour for such
timers, so that counter stays with "0" for a one period before wrapping
around.
Signed-off-by: Dmitry Osipenko <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 293130aa91e9fc319beca1d8b1a9ac8c0cb33f75
https://github.com/qemu/qemu/commit/293130aa91e9fc319beca1d8b1a9ac8c0cb33f75
Author: Dmitry Osipenko <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M tests/ptimer-test.c
Log Message:
-----------
tests: ptimer: Add tests for "wraparound after one period" policy
PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD changes ptimer behaviour in a such way,
that it would wrap around after one period instead of doing it immediately.
Signed-off-by: Dmitry Osipenko <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: ef0a9984aa0c3c8f440bbf488f2c14ccddd241ea
https://github.com/qemu/qemu/commit/ef0a9984aa0c3c8f440bbf488f2c14ccddd241ea
Author: Dmitry Osipenko <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M hw/core/ptimer.c
M include/hw/ptimer.h
Log Message:
-----------
hw/ptimer: Add "continuous trigger" policy
Currently, periodic timer that has load = delta = 0 performs trigger
on timer reload and stops, printing a "period zero" error message.
Introduce new policy that makes periodic timer to continuously trigger
with a period interval in case of load = 0.
Signed-off-by: Dmitry Osipenko <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 2e74583b29fff8e0e543898a9c61508a213ad83e
https://github.com/qemu/qemu/commit/2e74583b29fff8e0e543898a9c61508a213ad83e
Author: Dmitry Osipenko <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M tests/ptimer-test.c
Log Message:
-----------
tests: ptimer: Add tests for "continuous trigger" policy
PTIMER_POLICY_CONTINUOUS_TRIGGER makes periodic ptimer to re-trigger every
period in case of load = delta = 0.
Signed-off-by: Dmitry Osipenko <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 22471b8a0f1262192fb3698bd2ea1080d9176e6a
https://github.com/qemu/qemu/commit/22471b8a0f1262192fb3698bd2ea1080d9176e6a
Author: Dmitry Osipenko <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M hw/core/ptimer.c
M include/hw/ptimer.h
Log Message:
-----------
hw/ptimer: Add "no immediate trigger" policy
Performing trigger on setting (or starting to run with) counter = 0 could
be a wrong behaviour for some of the timers, provide "no immediate trigger"
policy to maintain correct behaviour for such timers.
Signed-off-by: Dmitry Osipenko <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 516deb421afc6e4f6073d0de3f33867235eef3fd
https://github.com/qemu/qemu/commit/516deb421afc6e4f6073d0de3f33867235eef3fd
Author: Dmitry Osipenko <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M tests/ptimer-test.c
Log Message:
-----------
tests: ptimer: Add tests for "no immediate trigger" policy
PTIMER_POLICY_NO_IMMEDIATE_TRIGGER makes ptimer to not to trigger on starting
to run with / setting counter to "0".
Signed-off-by: Dmitry Osipenko <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 3f6e6a13c1a059d44b9a55ec7af8c01ef096ff7e
https://github.com/qemu/qemu/commit/3f6e6a13c1a059d44b9a55ec7af8c01ef096ff7e
Author: Dmitry Osipenko <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M hw/core/ptimer.c
M include/hw/ptimer.h
Log Message:
-----------
hw/ptimer: Add "no immediate reload" policy
Immediate counter re-load on setting (or on starting to run with)
counter = 0 is a wrong behaviour for some of the timers. Add "no
immediate reload" policy that provides correct behaviour for such timers.
Signed-off-by: Dmitry Osipenko <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 56700e1aa6959c082a839285022fa4e48d5cf512
https://github.com/qemu/qemu/commit/56700e1aa6959c082a839285022fa4e48d5cf512
Author: Dmitry Osipenko <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M tests/ptimer-test.c
Log Message:
-----------
tests: ptimer: Add tests for "no immediate reload" policy
PTIMER_POLICY_NO_IMMEDIATE_RELOAD makes ptimer to not to re-load
counter on setting counter value to "0" or starting to run with "0".
Signed-off-by: Dmitry Osipenko <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 5580ea4576b60a4fa615c85e254fab1401149b45
https://github.com/qemu/qemu/commit/5580ea4576b60a4fa615c85e254fab1401149b45
Author: Dmitry Osipenko <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M hw/core/ptimer.c
M include/hw/ptimer.h
Log Message:
-----------
hw/ptimer: Add "no counter round down" policy
For most of the timers counter starts to decrement after first period
expires. Due to rounding down performed by the ptimer_get_count, it returns
counter - 1 for the running timer, so that for the ptimer user it looks
like counter gets decremented immediately after running the timer. Add "no
counter round down" policy that provides correct behaviour for those timers.
Signed-off-by: Dmitry Osipenko <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 057516fe2cd6bcc71fd66564d108d708a6b395b6
https://github.com/qemu/qemu/commit/057516fe2cd6bcc71fd66564d108d708a6b395b6
Author: Dmitry Osipenko <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M tests/ptimer-test.c
Log Message:
-----------
tests: ptimer: Add tests for "no counter round down" policy
PTIMER_POLICY_NO_COUNTER_ROUND_DOWN makes ptimer_get_count() return the
actual counter value and not the one less.
Signed-off-by: Dmitry Osipenko <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 673c7e8968771dd3ecde8ee50c704d2cb42a71fa
https://github.com/qemu/qemu/commit/673c7e8968771dd3ecde8ee50c704d2cb42a71fa
Author: Dmitry Osipenko <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M tests/ptimer-test-stubs.c
M tests/ptimer-test.c
M tests/ptimer-test.h
Log Message:
-----------
tests: ptimer: Change the copyright comment
Eric Blake suggested that use of "Author:" in the copyright text of the
files created by individuals is incorrect, replace it with "Copyright".
Signed-off-by: Dmitry Osipenko <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 33d44cdf00f5e2520c2ff3ece162a317f408cefb
https://github.com/qemu/qemu/commit/33d44cdf00f5e2520c2ff3ece162a317f408cefb
Author: Dmitry Osipenko <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M tests/ptimer-test.c
Log Message:
-----------
tests: ptimer: Replace 10000 with 1
The 10000 is an arbitrarily chosen value used for advancing the QEMU
time, so that ptimer's now != last. Change it to 1 to make code a bit
more readable.
Signed-off-by: Dmitry Osipenko <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 226fb5aaff8157472f97c63193660732a215d87f
https://github.com/qemu/qemu/commit/226fb5aaff8157472f97c63193660732a215d87f
Author: Dmitry Osipenko <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M hw/timer/arm_mptimer.c
M include/hw/timer/arm_mptimer.h
Log Message:
-----------
arm_mptimer: Convert to use ptimer
Current ARM MPTimer implementation uses QEMUTimer for the actual timer,
this implementation isn't complete and mostly tries to duplicate of what
generic ptimer is already doing fine.
Conversion to ptimer brings the following benefits and fixes:
- Simple timer pausing implementation
- Fixes counter value preservation after stopping the timer
- Properly handles prescaler != 0 / counter = 0 / load = 0 cases
- Code simplification and reduction
Bump VMSD to version 3, since VMState is changed and is not compatible
with the previous implementation.
Signed-off-by: Dmitry Osipenko <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 882fac37296bf05f0c29bd39e9da7b69431935e6
https://github.com/qemu/qemu/commit/882fac37296bf05f0c29bd39e9da7b69431935e6
Author: Dmitry Osipenko <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M tests/Makefile.include
A tests/test-arm-mptimer.c
Log Message:
-----------
tests: Add tests for the ARM MPTimer
ARM MPTimer is a per-CPU core timer, essential part of the ARM Cortex-A9
MPCore. Add QTests for it.
Signed-off-by: Dmitry Osipenko <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 16fc326a55aa867b90837ce14f0cc622ca6be840
https://github.com/qemu/qemu/commit/16fc326a55aa867b90837ce14f0cc622ca6be840
Author: Prem Mallappa <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M include/hw/acpi/acpi-defs.h
Log Message:
-----------
ACPI: Add IORT Structure definition
ACPI Spec 6.0 introduces IO Remapping Table Structure. This patch
introduces the definitions required to describe the IO relationship
between the PCIe root complex and the ITS.
This conforms to:
"IO Remapping Table System Software on ARM Platforms",
Document number: ARM DEN 0049B, October 2015.
Signed-off-by: Prem Mallappa <address@hidden>
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: e78f12221447af1af47a8ebbdabd35ff37e6d1dd
https://github.com/qemu/qemu/commit/e78f12221447af1af47a8ebbdabd35ff37e6d1dd
Author: Prem Mallappa <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M hw/arm/virt-acpi-build.c
Log Message:
-----------
ARM: Virt: ACPI: Build an IORT table with RC and ITS nodes
This patch builds an IORT table that features a root complex node and
an ITS node. This complements the ITS description in the ACPI MADT
table and allows vhost-net on ACPI guest.
Signed-off-by: Prem Mallappa <address@hidden>
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 6be8f5e2626e102433e569d9cece2120baf0c879
https://github.com/qemu/qemu/commit/6be8f5e2626e102433e569d9cece2120baf0c879
Author: Prasad J Pandit <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M hw/timer/a9gtimer.c
Log Message:
-----------
timer: a9gtimer: remove loop to auto-increment comparator
ARM A9MP processor has a peripheral timer with an auto-increment
register, which holds an increment step value. A user could set
this value to zero. When auto-increment control bit is enabled,
it leads to an infinite loop in 'a9_gtimer_update' while
updating comparator value. Remove this loop incrementing the
comparator value.
Reported-by: Li Qiang <address@hidden>
Signed-off-by: Prasad J Pandit <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 0fa758c3a069bc59a0d903d69028971c46d1a119
https://github.com/qemu/qemu/commit/0fa758c3a069bc59a0d903d69028971c46d1a119
Author: Corey Minyard <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M hw/i2c/core.c
Log Message:
-----------
i2c: Fix SMBus read transactions to avoid double events
Change 2293c27faddf (i2c: implement broadcast write) added broadcast
capability to the I2C bus, but it broke SMBus read transactions.
An SMBus read transaction does two i2c_start_transaction() calls
without an intervening i2c_end_transfer() call. This will
result in i2c_start_transfer() adding the same device to the
current_devs list twice, and then the ->event() for the same
device gets called twice in the second call to i2c_start_transfer(),
resulting in the smbus code getting confused.
Note that this happens even with pure I2C devices when simulating
SMBus over I2C.
This fix only scans the bus if the current set of devices is empty.
This means that the current set of devices stays fixed until
i2c_end_transfer() is called, which is really what you want.
This also deletes the empty check from the top of i2c_end_transfer().
It's unnecessary, and it prevents the broadcast variable from being
set to false at the end of the transaction if no devices were on
the bus.
Cc: KONRAD Frederic <address@hidden>
Cc: Alistair Francis <address@hidden>
Cc: Peter Crosthwaite <address@hidden>
Cc: Kwon <address@hidden>
Cc: Peter Maydell <address@hidden>
Signed-off-by: Corey Minyard <address@hidden>
Reviewed-by: KONRAD Frederic <address@hidden>
Tested-by: KONRAD Frederic <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 84da15169b45f7080e4b1b32f70e68e726e02740
https://github.com/qemu/qemu/commit/84da15169b45f7080e4b1b32f70e68e726e02740
Author: Prasad J Pandit <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M hw/timer/stm32f2xx_timer.c
Log Message:
-----------
timer: stm32f2xx_timer: add check for prescaler value
The STM32F2XX Timer emulator uses a 16 bit prescaler value to
limit the timer clock rate. It does that by dividing the timer
frequency. If the prescaler 's->tim_psc' was set to be UINT_MAX,
it'd lead to divide by zero error. Limit prescaler value to 16
bits to avoid it.
Reported-by: Huawei PSIRT <address@hidden>
Signed-off-by: Prasad J Pandit <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: ece71994aa54a3388945b6402250cbd41bb7f3ed
https://github.com/qemu/qemu/commit/ece71994aa54a3388945b6402250cbd41bb7f3ed
Author: xiaoqiang zhao <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M hw/arm/musicpal.c
Log Message:
-----------
hw/arm: QOM'ify musicpal.c
Drop the old Sysbus init and use instance_init and
DeviceClass::realize instead
Signed-off-by: xiaoqiang zhao <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: f79a7ff108c87034c3398f7851b0a278d1362d47
https://github.com/qemu/qemu/commit/f79a7ff108c87034c3398f7851b0a278d1362d47
Author: xiaoqiang zhao <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M hw/arm/pxa2xx_gpio.c
Log Message:
-----------
hw/arm: QOM'ify pxa2xx_gpio.c
Drop the old Sysbus init and use instance_init and
DeviceClass::realize instead
Signed-off-by: xiaoqiang zhao <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 8934515aff3701d40e972b621d67066ff40997e9
https://github.com/qemu/qemu/commit/8934515aff3701d40e972b621d67066ff40997e9
Author: xiaoqiang zhao <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M hw/arm/strongarm.c
Log Message:
-----------
hw/arm: QOM'ify strongarm.c
Drop the old Sysbus init and use instance_init and
DeviceClass::realize instead
Signed-off-by: xiaoqiang zhao <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: caae8032d3bd0a54f09abdae7624f52dece5ffd6
https://github.com/qemu/qemu/commit/caae8032d3bd0a54f09abdae7624f52dece5ffd6
Author: xiaoqiang zhao <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M hw/display/pl110.c
Log Message:
-----------
hw/display: QOM'ify pl110.c
Drop the old Sysbus init and use instance_init and
DeviceClass::realize instead
Signed-off-by: xiaoqiang zhao <address@hidden>
Message-id: address@hidden
[PMM: added accidentally dropped blank line]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e
https://github.com/qemu/qemu/commit/19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e
Author: Peter Maydell <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M linux-user/main.c
M target-arm/cpu.h
M target-arm/helper.c
M target-arm/translate.c
Log Message:
-----------
target-arm: Implement new HLT trap for semihosting
Version 2.0 of the semihosting specification introduces new trap
instructions for AArch32: HLT 0xF000 for A32 and HLT 0x3C for T32.
Implement these (in the same way we implement the existing HLT
semihosting trap for A64).
The old traps via SVC and BKPT are unaffected.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: cc083d8a25e0a886c3cd4bea0bf57ac4e896fa3f
https://github.com/qemu/qemu/commit/cc083d8a25e0a886c3cd4bea0bf57ac4e896fa3f
Author: Corey Minyard <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M hw/i2c/core.c
M hw/i2c/smbus.c
Log Message:
-----------
i2c: Add asserts for second smbus i2c_start_transfer()
Some SMBus operations restart the transfer to convert from
write to read mode without an intervening i2c_end_transfer().
The second call cannot fail, so the return code is unchecked,
but this causes Coverity to complain. So add some asserts
and documentation about this.
Signed-off-by: Corey Minyard <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: fe4c04071f702e008da7db06d0a220b27e1ab3ac
https://github.com/qemu/qemu/commit/fe4c04071f702e008da7db06d0a220b27e1ab3ac
Author: Peter Maydell <address@hidden>
Date: 2016-10-24 (Mon, 24 Oct 2016)
Changed paths:
M exec.c
M hw/arm/musicpal.c
M hw/arm/pxa2xx_gpio.c
M hw/arm/strongarm.c
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M hw/core/ptimer.c
M hw/display/pl110.c
M hw/i2c/core.c
M hw/i2c/smbus.c
M hw/timer/a9gtimer.c
M hw/timer/arm_mptimer.c
M hw/timer/stm32f2xx_timer.c
M include/exec/cpu-all.h
M include/hw/acpi/acpi-defs.h
M include/hw/boards.h
M include/hw/ptimer.h
M include/hw/timer/arm_mptimer.h
M include/qemu-common.h
M linux-user/main.c
M migration/ram.c
M migration/savevm.c
M target-arm/cpu.c
M target-arm/cpu.h
M target-arm/helper.c
M target-arm/translate.c
M tests/Makefile.include
M tests/ptimer-test-stubs.c
M tests/ptimer-test.c
M tests/ptimer-test.h
A tests/test-arm-mptimer.c
M translate-all.c
M vl.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20161024'
into staging
target-arm queue:
* support variable (runtime-determined) page sizes, for a
nearly-20% speedup of TCG for ARMv7 and v8 CPUs with 4K pages
* ptimer: add tests, support more flexible behaviour around
what happens on the "zero" tick, use ptimer for a9gtimer
* virt: ACPI: Add IORT Structure definition
* i2c: Fix SMBus read transactions to avoid double events
* timer: stm32f2xx_timer: add check for prescaler value
* QOMify musicpal, pxa2xx_gpio, strongarm, pl110
* target-arm: Implement new HLT trap for semihosting
* i2c: Add asserts for second smbus i2c_start_transfer()
# gpg: Signature made Mon 24 Oct 2016 18:24:17 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20161024: (32 commits)
i2c: Add asserts for second smbus i2c_start_transfer()
target-arm: Implement new HLT trap for semihosting
hw/display: QOM'ify pl110.c
hw/arm: QOM'ify strongarm.c
hw/arm: QOM'ify pxa2xx_gpio.c
hw/arm: QOM'ify musicpal.c
timer: stm32f2xx_timer: add check for prescaler value
i2c: Fix SMBus read transactions to avoid double events
timer: a9gtimer: remove loop to auto-increment comparator
ARM: Virt: ACPI: Build an IORT table with RC and ITS nodes
ACPI: Add IORT Structure definition
tests: Add tests for the ARM MPTimer
arm_mptimer: Convert to use ptimer
tests: ptimer: Replace 10000 with 1
tests: ptimer: Change the copyright comment
tests: ptimer: Add tests for "no counter round down" policy
hw/ptimer: Add "no counter round down" policy
tests: ptimer: Add tests for "no immediate reload" policy
hw/ptimer: Add "no immediate reload" policy
tests: ptimer: Add tests for "no immediate trigger" policy
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/45b567d645c2...fe4c04071f70
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