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[Qemu-commits] [qemu/qemu] bcf482: docs/generic-loader: Update the docum
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[Qemu-commits] [qemu/qemu] bcf482: docs/generic-loader: Update the document |
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Date: |
Tue, 18 Oct 2016 01:30:06 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: bcf48274ba6fbe6158beccd9d4be4c22931f33b9
https://github.com/qemu/qemu/commit/bcf48274ba6fbe6158beccd9d4be4c22931f33b9
Author: Alistair Francis <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M docs/generic-loader.txt
Log Message:
-----------
docs/generic-loader: Update the document
This patch does three things:
- It adds a list of restrictions and ToDos
- It corrects the header --- lines to match the length of the header
- It clarifies the force-raw option
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: cabbcca0375a96f2e0ccae660ca9dc1510adafbd
https://github.com/qemu/qemu/commit/cabbcca0375a96f2e0ccae660ca9dc1510adafbd
Author: Rutuja Shah <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M hw/dma/xilinx_axidma.c
Log Message:
-----------
Reducing stack frame size in stream_process_mem2s()
This patch allocates memory for txbuf in struct Stream rather than the stack.
As a result, the stack frame size is reduced of stream_process_mem2s().
Signed-off-by: Rutuja Shah <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 4344af65e7448b3d03b060d0844d92e0cc6bcc2b
https://github.com/qemu/qemu/commit/4344af65e7448b3d03b060d0844d92e0cc6bcc2b
Author: Paolo Bonzini <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M target-arm/kvm.c
Log Message:
-----------
target-arm: kvm: use AddressSpace-specific listener
The only address space where the GIC devices are added is
address_space_memory. There is no need to use a global
MemoryListener.
This removes the only user of global MemoryListeners.
Signed-off-by: Paolo Bonzini <address@hidden>
[PMM: added missing #include "exec/address-spaces.h"]
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 0e5803dfbce6cf056fe15b3b5cb31fe8519a6f6e
https://github.com/qemu/qemu/commit/0e5803dfbce6cf056fe15b3b5cb31fe8519a6f6e
Author: Cédric Le Goater <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed: rename the smc object to fmc
The Aspeed SoC has three different types of SMC (Static Memory
Controller) controllers: the SMC (legacy), the FMC (the new one) and
the SPI for the host PNOR. The FMC and the SPI models are now
converging on the AST2500 SoC and the SMC, which was still available
on the AST2400 SoC, was removed.
The Aspeed SoC does not provide support for the legacy SMC
controller. So, let's rename the 'smc' object to 'fmc' to clarify its
nature.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: dcb834447f7b22b08a918e2266e5751035fbfc83
https://github.com/qemu/qemu/commit/dcb834447f7b22b08a918e2266e5751035fbfc83
Author: Cédric Le Goater <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M hw/arm/aspeed_soc.c
M hw/ssi/aspeed_smc.c
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
aspeed: move the flash module mapping address under the controller definition
This will ease the definition of the new controllers for the AST2500
SoC and also ease the support of the segment registers, which provide
a way to reconfigure the mapping window of each slave.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: dbcabeeb54e9101307cf6225b9311a3ceaab7d1a
https://github.com/qemu/qemu/commit/dbcabeeb54e9101307cf6225b9311a3ceaab7d1a
Author: Cédric Le Goater <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed: extend the number of host SPI controllers
The AST2500 SoC has two. Let's prepare ground for the next changes
which will add the required definitions for the second host SPI
controller.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 6dc52326ccbb826c3b61aa1429001a79d34be1e3
https://github.com/qemu/qemu/commit/6dc52326ccbb826c3b61aa1429001a79d34be1e3
Author: Cédric Le Goater <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M hw/arm/aspeed_soc.c
M hw/ssi/aspeed_smc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed: add support for the AST2500 SoC SMC controllers
The SMC controllers on the Aspeed AST2500 SoC are very similar to the
ones found on the AST2400. The differences are on the number of
supported flash modules and their default mappings in the SoC address
space.
The Aspeed AST2500 has one SPI controller for the BMC firmware and two
for the host firmware. All controllers have now the same set of
registers compatible with the AST2400 FMC controller and the legacy
'SMC' controller is fully gone.
We keep the FMC object to act as the BMC SPI controller and add a new
SPI controller for the host. We also have to introduce new type names
to handle the differences in the flash modules memory mappping.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 2da95fd88b87bd90e39caeaf94943023b85dbe93
https://github.com/qemu/qemu/commit/2da95fd88b87bd90e39caeaf94943023b85dbe93
Author: Cédric Le Goater <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M hw/ssi/aspeed_smc.c
Log Message:
-----------
aspeed: create mapping regions for the maximum number of slaves
The SMC controller on the Aspeed SoC has a set of registers to
configure the mapping of each flash module in the SoC address
space. These mapping windows are configurable even though no SPI slave
is attached to the controller.
Also rewrite a bit the comments in the code on this topic.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: a03cb1daf1a4e6ccce8632e13373eef8c4f9cba4
https://github.com/qemu/qemu/commit/a03cb1daf1a4e6ccce8632e13373eef8c4f9cba4
Author: Cédric Le Goater <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M hw/ssi/aspeed_smc.c
Log Message:
-----------
aspeed: add support for the SMC segment registers
The SMC controller on the Aspeed SoC has a set of registers to
configure the mapping of each flash module in the SoC address
space. Writing to these registers triggers a remap of the memory
region and the spec requires a certain number of checks before doing
so.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 4c8afda7d2864023047d466eddd1e8f73a6b072c
https://github.com/qemu/qemu/commit/4c8afda7d2864023047d466eddd1e8f73a6b072c
Author: Michael Olbrich <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M hw/arm/boot.c
M vl.c
Log Message:
-----------
hw/arm/boot: allow using a command line specified dtb without a kernel
When kernel and device tree are specified in the QEMU commandline, then
this device tree may be modified e.g. to add virtio_mmio devices.
With a bootloader e.g. on a flash device these extra devices are not
available.
With this change, the device tree can be specified at the QEMU commandline.
The modified device tree made available to the bootloader with the same
mechanism already supported by device trees fully generated by QEMU.
Signed-off-by: Michael Olbrich <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 04bb79d1f519ae190acf836ff9e07bef5086fad0
https://github.com/qemu/qemu/commit/04bb79d1f519ae190acf836ff9e07bef5086fad0
Author: Thomas Huth <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M hw/dma/pl080.c
Log Message:
-----------
hw/dma/pl080: Fix bad bit mask (PL080_CONF_M1 | PL080_CONF_M1)
The M1 and M2 bits are both used for configuring the endianness
of the AHB master interfaces, so the second PL080_CONF_M1 should
be PL080_CONF_M2 instead.
Buglink: https://bugs.launchpad.net/qemu/+bug/1631773
Signed-off-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: bad07da21c5da7ab3c64817d163c4e9b7b7fa5f2
https://github.com/qemu/qemu/commit/bad07da21c5da7ab3c64817d163c4e9b7b7fa5f2
Author: Christopher Covington <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M hw/intc/arm_gic_kvm.c
Log Message:
-----------
hw/intc/arm_gic_kvm: Fix build on aarch64
Remove unused debugging code to fix native building on aarch64. Without
this change, the following -Werr output inhibits make from completing.
qemu/hw/intc/arm_gic_kvm.c:38:18: error: debug_gic_kvm defined but not used
[-Werror=unused-const-variable=]
static const int debug_gic_kvm = 0;
^~~~~~~~~~~~~
cc1: all warnings being treated as errors
qemu/rules.mak:60: recipe for target 'hw/intc/arm_gic_kvm.o' failed
make[1]: *** [hw/intc/arm_gic_kvm.o] Error 1
Makefile:205: recipe for target 'subdir-aarch64-softmmu' failed
Signed-off-by: Christopher Covington <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 13cda487126fd2079fc67473bee3d2d119052ff1
https://github.com/qemu/qemu/commit/13cda487126fd2079fc67473bee3d2d119052ff1
Author: Andrew Jones <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M hw/arm/virt-acpi-build.c
Log Message:
-----------
hw/arm/virt-acpi-build: fix MADT generation
We can't return early from build_* functions, as build_header is
only called at the end.
Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 2231f69b4e4523c43aa459cab18ab77c0e29b4d1
https://github.com/qemu/qemu/commit/2231f69b4e4523c43aa459cab18ab77c0e29b4d1
Author: Andrew Jones <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M include/hw/arm/virt-acpi-build.h
Log Message:
-----------
hw/arm/virt: no ITS on older machine types
We should avoid exposing new hardware (through DT and ACPI) on older
machine types. This patch keeps 2.7 and older from changing, despite
the introduction of ITS support for 2.8.
Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7a2334f7205ca7604dc09b77e74511e96d35686a
https://github.com/qemu/qemu/commit/7a2334f7205ca7604dc09b77e74511e96d35686a
Author: Cédric Le Goater <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M tests/Makefile.include
A tests/m25p80-test.c
Log Message:
-----------
tests: add a m25p80 test
This test uses the palmetto platform and the Aspeed SPI controller to
test the m25p80 flash module device model. The flash model is defined
by the platform (n25q256a) and it would be nice to find way to control
it, using a property probably.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Brainstormed-with: Greg Kurz <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 24b9462544eeb64e1f10feb460b0c704e972ad4e
https://github.com/qemu/qemu/commit/24b9462544eeb64e1f10feb460b0c704e972ad4e
Author: Paolo Bonzini <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M stubs/vmstate.c
M tests/Makefile.include
M tests/ptimer-test-stubs.c
M tests/ptimer-test.c
Log Message:
-----------
tests: cleanup ptimer-test
1) ptimer-test is not a qtest---it runs the ptimer.c code directly in the
ptimer-test process
2) ptimer-test has its own stubs file, so there is no need to add more
stubs to stubs/vmstate.c
Signed-off-by: Paolo Bonzini <address@hidden>
Reviewed-by: Dmitry Osipenko <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 08426da7dd0a63835dcf3003e9a022c0d5678be7
https://github.com/qemu/qemu/commit/08426da7dd0a63835dcf3003e9a022c0d5678be7
Author: Vijay Kumar B <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M hw/arm/pxa2xx.c
Log Message:
-----------
pxa2xx: Auto-assign name for i2c bus in i2c_init_bus.
If a name is provided, the same name is assigned to both the I2C
controllers. Leaving it NULL, causes names to be automatically
assigned with an ID suffix, giving unique names to each
controller. This helps us to uniquely identify each controller in the
device tree, for example when adding an I2C device.
Signed-off-by: Vijay Kumar B. <address@hidden>
Reviewed-by: Deepak S. <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 86fb3fa4ed5873b021a362ea26a021f4aeab1bb4
https://github.com/qemu/qemu/commit/86fb3fa4ed5873b021a362ea26a021f4aeab1bb4
Author: Thomas Hanson <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M target-arm/cpu.h
M target-arm/helper.c
M target-arm/translate-a64.c
M target-arm/translate.h
Log Message:
-----------
target-arm: Infrastucture changes to enable handling of tagged address
loading into PC
When capturing the current CPU state for the TB, extract the TBI0 and TBI1
values from the correct TCR for the current EL and then add them to the TB
flags field.
Then, at the start of code generation for the block, copy the TBI fields
into the DisasContext structure.
Signed-off-by: Thomas Hanson <address@hidden>
Message-id: address@hidden
[PMM: drop useless 'extern' keyword on function prototypes;
provide CONFIG_USER_ONLY trivial versions of arm_regime_tbi[01]()]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 6feecb8b941f2d21e5645d0b6e0cdb776998121b
https://github.com/qemu/qemu/commit/6feecb8b941f2d21e5645d0b6e0cdb776998121b
Author: Thomas Hanson <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: Code changes to implement overwrite of tag field on PC load
For BR, BLR and RET instructions, if tagged addresses are enabled, the
tag field in the address must be cleared out prior to loading the
address into the PC. Depending on the current EL, it will be set to
either all 0's or all 1's.
Signed-off-by: Thomas Hanson <address@hidden>
Message-id: address@hidden
[PMM: remove unnecessary gen_a64_set_pc_reg() wrapper,
rename gen_a64_set_pc_var() to gen_a64_set_pc(), fix stray
misindentation]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 957956b3013c8122a749dfe61a41aef8b4100e31
https://github.com/qemu/qemu/commit/957956b3013c8122a749dfe61a41aef8b4100e31
Author: Thomas Hanson <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: Comments added to identify cases in a switch
3 cases in a switch in disas_exc() require reference to the
ARM ARM spec in order to determine what case they're handling.
Signed-off-by: Thomas Hanson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: fb0e8e79a9d77ee240dbca036fa8698ce654e5d1
https://github.com/qemu/qemu/commit/fb0e8e79a9d77ee240dbca036fa8698ce654e5d1
Author: Peter Maydell <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M target-arm/op_helper.c
M target-arm/translate.c
Log Message:
-----------
Fix masking of PC lower bits when doing exception returns
In commit 9b6a3ea7a699594 store_reg() was changed to mask
both bits 0 and 1 of the new PC value when in ARM mode.
Unfortunately this broke the exception return code paths
when doing a return from ARM mode to Thumb mode: in some
of these we write a new CPSR including new Thumb mode
bit via gen_helper_cpsr_write_eret(), and then use store_reg()
to write the new PC. In this case if the new CPSR specified
Thumb mode then masking bit 1 of the PC is incorrect
(these code paths correspond to the v8 ARM ARM pseudocode
function AArch32.ExceptionReturn(), which always aligns the
new PC appropriately for the new instruction set state).
Instead of using store_reg() in exception-return code paths,
call a new store_pc_exc_ret() which stores the raw new PC
value to env->regs[15], and then mask it appropriately in
the subsequent helper_cpsr_write_eret() where the new
env->thumb state is available.
This fixes a bug introduced by 9b6a3ea7a699594 which caused
crashes/hangs or otherwise bad behaviour for Linux when
userspace was using Thumb.
Reported-by: Jerome Forissier <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 5dbdc4342f479d799a1970dd5fd22e64c9dcd50d
https://github.com/qemu/qemu/commit/5dbdc4342f479d799a1970dd5fd22e64c9dcd50d
Author: Peter Maydell <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M target-arm/helper.c
Log Message:
-----------
target-arm: Implement dummy MDCCINT_EL1
MDCCINT_EL1 is part of the DCC debugger communication
channel between the CPU and an attached external debugger.
QEMU doesn't implement this, but since Linux may try
to access this register we need to provide at least
a dummy implementation.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Commit: 194cbc492bcc8f3f1868ec97a35146bc99c3c71c
https://github.com/qemu/qemu/commit/194cbc492bcc8f3f1868ec97a35146bc99c3c71c
Author: Peter Maydell <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M Makefile.objs
M target-arm/helper.c
A target-arm/trace-events
Log Message:
-----------
target-arm: Add trace events for the generic timers
Add some useful trace events for the ARM generic timers (notably
the various register writes and the resulting IRQ line state).
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Commit: 081b1b98b7ca8734b4582942024a70ae3268238e
https://github.com/qemu/qemu/commit/081b1b98b7ca8734b4582942024a70ae3268238e
Author: Peter Maydell <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/trace-events
Log Message:
-----------
hw/intc/arm_gicv3: Fix ICC register tracepoints
Fix some problems with the tracepoints for ICC register reads
and writes:
* tracepoints for ICC_BPR<n>, ICC_AP<n>R<x>, ICC_IGRPEN<n>,
ICC_EIOR<n> were not printing the <n> that indicated whether
the access was to the group 0 or 1 register
* the ICC_IGREPEN1_EL3 read function was not actually calling
the associated tracepoint
* the ICC_BPR<n> write function was incorrectly calling the
tracepoint for ICC_PMR writes
Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Commit: 041ac05672993ff33a15f8017c0f729ca6dfad73
https://github.com/qemu/qemu/commit/041ac05672993ff33a15f8017c0f729ca6dfad73
Author: Peter Maydell <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M hw/char/pl011.c
M hw/char/trace-events
Log Message:
-----------
hw/char/pl011: Add trace events
Add some trace events for the pl011 UART model.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 2d02ac10b6644d71c88cc7943e74d7ad6674fff1
https://github.com/qemu/qemu/commit/2d02ac10b6644d71c88cc7943e74d7ad6674fff1
Author: Peter Maydell <address@hidden>
Date: 2016-10-17 (Mon, 17 Oct 2016)
Changed paths:
M Makefile.objs
M docs/generic-loader.txt
M hw/arm/aspeed.c
M hw/arm/aspeed_soc.c
M hw/arm/boot.c
M hw/arm/pxa2xx.c
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M hw/char/pl011.c
M hw/char/trace-events
M hw/dma/pl080.c
M hw/dma/xilinx_axidma.c
M hw/intc/arm_gic_kvm.c
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/trace-events
M hw/ssi/aspeed_smc.c
M include/hw/arm/aspeed_soc.h
M include/hw/arm/virt-acpi-build.h
M include/hw/ssi/aspeed_smc.h
M stubs/vmstate.c
M target-arm/cpu.h
M target-arm/helper.c
M target-arm/kvm.c
M target-arm/op_helper.c
A target-arm/trace-events
M target-arm/translate-a64.c
M target-arm/translate.c
M target-arm/translate.h
M tests/Makefile.include
A tests/m25p80-test.c
M tests/ptimer-test-stubs.c
M tests/ptimer-test.c
M vl.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20161017'
into staging
target-arm:
* target-arm: kvm: use AddressSpace-specific listener
* aspeed: add SMC controllers
* hw/arm/boot: allow using a command line specified dtb without a kernel
* hw/dma/pl080: Fix bad bit mask
* hw/intc/arm_gic_kvm: Fix build on aarch64 with some compilers
* hw/arm/virt: fix ACPI tables for ITS
* tests: add a m25p80 test
* tests: cleanup ptimer-test
* pxa2xx: Auto-assign name for i2c bus in i2c_init_bus
* target-arm: handle tagged addresses in A64 code
* target-arm: Fix masking of PC lower bits when doing exception returns
* target-arm: Implement dummy MDCCINT_EL1
* target-arm: Add trace events for the generic timers
* hw/intc/arm_gicv3: Fix ICC register tracepoints
* hw/char/pl011: Add trace events
# gpg: Signature made Mon 17 Oct 2016 19:39:42 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20161017: (25 commits)
hw/char/pl011: Add trace events
hw/intc/arm_gicv3: Fix ICC register tracepoints
target-arm: Add trace events for the generic timers
target-arm: Implement dummy MDCCINT_EL1
Fix masking of PC lower bits when doing exception returns
target-arm: Comments added to identify cases in a switch
target-arm: Code changes to implement overwrite of tag field on PC load
target-arm: Infrastucture changes to enable handling of tagged address
loading into PC
pxa2xx: Auto-assign name for i2c bus in i2c_init_bus.
tests: cleanup ptimer-test
tests: add a m25p80 test
hw/arm/virt: no ITS on older machine types
hw/arm/virt-acpi-build: fix MADT generation
hw/intc/arm_gic_kvm: Fix build on aarch64
hw/dma/pl080: Fix bad bit mask (PL080_CONF_M1 | PL080_CONF_M1)
hw/arm/boot: allow using a command line specified dtb without a kernel
aspeed: add support for the SMC segment registers
aspeed: create mapping regions for the maximum number of slaves
aspeed: add support for the AST2500 SoC SMC controllers
aspeed: extend the number of host SPI controllers
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/0975b8b823a8...2d02ac10b664
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