[Qemu-commits] [qemu/qemu] b5d550: MAINTAINERS: Add some missing ppc-rel

qemu-commits
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] b5d550: MAINTAINERS: Add some missing ppc-rel

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] b5d550: MAINTAINERS: Add some missing ppc-related files
Date:	Fri, 23 Sep 2016 07:30:04 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: b5d55020471aa426701938eb826193e95c43b515
      
https://github.com/qemu/qemu/commit/b5d55020471aa426701938eb826193e95c43b515
  Author: Thomas Huth <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add some missing ppc-related files

There are some powerpc related files in the QEMU source tree
which are currently not covered by the MAINTAINERS file and
thus not properly classified by the get_maintainer.pl script.
So let's add them to the proper sections.

Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 6ca038c292d9274dc224d401a1ba16eb5a1dd501
      
https://github.com/qemu/qemu/commit/6ca038c292d9274dc224d401a1ba16eb5a1dd501
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: restrict the use of the rfi instruction

Power ISA 2.x has deleted the rfi instruction and rfid shoud be used
instead on cpus following this instruction set or later.

This will raise an invalid exception when rfi is used on such
processors: Book3S 64-bit processors.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[clg: the required fix in openbios, commit b747b6acc272 ('ppc: use
      rfid when running under a CPU from the 970 family.'), is now
      merged in qemu under commit 5cebd885d0d2 ('Update OpenBIOS
      images to b747b6a built from submodule.') ]
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: e7b1e06fbcb81ac66e2586214a6c42fdf15fadf3
      
https://github.com/qemu/qemu/commit/e7b1e06fbcb81ac66e2586214a6c42fdf15fadf3
  Author: Rajalakshmi Srinivasaraghavan <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c
    M target-ppc/translate/vmx-impl.inc.c
    M target-ppc/translate/vmx-ops.inc.c

  Log Message:
  -----------
  target-ppc: add vector insert instructions

The following vector insert instructions are added from ISA 3.0.

vinsertb - Vector Insert Byte
vinserth - Vector Insert Halfword
vinsertw - Vector Insert Word
vinsertd - Vector Insert Doubleword

Signed-off-by: Rajalakshmi Srinivasaraghavan <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b5d569a1bb033354847c34d2e011fed812ff7428
      
https://github.com/qemu/qemu/commit/b5d569a1bb033354847c34d2e011fed812ff7428
  Author: Rajalakshmi Srinivasaraghavan <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate/vmx-impl.inc.c
    M target-ppc/translate/vmx-ops.inc.c

  Log Message:
  -----------
  target-ppc: add vector extract instructions

The following vector extract instructions are added from ISA 3.0.

vextractub - Vector Extract Unsigned Byte
vextractuh - Vector Extract Unsigned Halfword
vextractuw - Vector Extract Unsigned Word
vextractd - Vector Extract Unsigned Doubleword

Signed-off-by: Rajalakshmi Srinivasaraghavan <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a5ad8fbf9d771d2accb583fc1eb58faf9931cfce
      
https://github.com/qemu/qemu/commit/a5ad8fbf9d771d2accb583fc1eb58faf9931cfce
  Author: Rajalakshmi Srinivasaraghavan <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate/vmx-impl.inc.c
    M target-ppc/translate/vmx-ops.inc.c

  Log Message:
  -----------
  target-ppc: add vector count trailing zeros instructions

The following vector count trailing zeros instructions are
added from ISA 3.0.

vctzb - Vector Count Trailing Zeros Byte
vctzh - Vector Count Trailing Zeros Halfword
vctzw - Vector Count Trailing Zeros Word
vctzd - Vector Count Trailing Zeros Doubleword

Signed-off-by: Rajalakshmi Srinivasaraghavan <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 01fe9a470c4c49a18c386f411278780dedb65ad6
      
https://github.com/qemu/qemu/commit/01fe9a470c4c49a18c386f411278780dedb65ad6
  Author: Rajalakshmi Srinivasaraghavan <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate/vmx-impl.inc.c
    M target-ppc/translate/vmx-ops.inc.c

  Log Message:
  -----------
  target-ppc: add vector bit permute doubleword instruction

Add vbpermd instruction from ISA 3.0.

Signed-off-by: Rajalakshmi Srinivasaraghavan <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: ab04543602b7fa8fbc33401c66f071ae4570da04
      
https://github.com/qemu/qemu/commit/ab04543602b7fa8fbc33401c66f071ae4570da04
  Author: Rajalakshmi Srinivasaraghavan <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate/vmx-impl.inc.c
    M target-ppc/translate/vmx-ops.inc.c

  Log Message:
  -----------
  target-ppc: add vector permute right indexed instruction

Add vpermr instruction from ISA 3.0.

Signed-off-by: Rajalakshmi Srinivasaraghavan <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 95cda4c44ee2ae8616b2f9d8a2d68882cf437859
      
https://github.com/qemu/qemu/commit/95cda4c44ee2ae8616b2f9d8a2d68882cf437859
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M linux-user/main.c
    M linux-user/ppc/syscall_nr.h
    M linux-user/signal.c

  Log Message:
  -----------
  ppc: Fix signal delivery in ppc-user and ppc64-user

There were a number of bugs in the implementation:

 - The structure alignment was wrong for 64-bit.

 - Also 64-bit only does RT signals.

 - On 64-bit, we need to put a pointer to the (aligned) vector registers
   in the frame and use it for restoring

 - We had endian bugs when saving/restoring vector registers

 - My recent fixes for exception NIP broke sigreturn in user mode
   causing us to resume one instruction too far.

 - Add VSR second halves

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: aa15f497178a8a3d489bf410171c3b6dfa0d9f49
      
https://github.com/qemu/qemu/commit/aa15f497178a8a3d489bf410171c3b6dfa0d9f49
  Author: Laurent Vivier <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M qtest.c

  Log Message:
  -----------
  qtest: replace strtoXX() by qemu_strtoXX()

Check the result of qemu_strtoXX() and assert
if the string cannot be converted.

Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 8d6ef7c9fe880c710dd55cfe7a0f076be475bede
      
https://github.com/qemu/qemu/commit/8d6ef7c9fe880c710dd55cfe7a0f076be475bede
  Author: Laurent Vivier <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M tests/Makefile.include
    M tests/libqos/libqos-pc.c
    A tests/libqos/libqos-spapr.c
    A tests/libqos/libqos-spapr.h
    M tests/libqos/libqos.c
    A tests/libqos/malloc-spapr.c
    A tests/libqos/malloc-spapr.h

  Log Message:
  -----------
  libqos: define SPAPR libqos functions

Define spapr_alloc_init()/spapr_alloc_init_flags()/spapr_alloc_uninit()

  to allocate and use SPAPR guest memory

Define qtest_spapr_vboot()/qtest_spapr_boot()/qtest_spapr_shutdown()

  to start SPAPR guest with QOSState initialized for it (memory management)

Move qtest_irq_intercept_in() from generic part to PC part.

Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: eeddd59f59626302cdb7db2602140ac9a076dec9
      
https://github.com/qemu/qemu/commit/eeddd59f59626302cdb7db2602140ac9a076dec9
  Author: Laurent Vivier <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M hw/ppc/spapr_rtas.c
    A include/hw/ppc/spapr_rtas.h
    M qtest.c
    M tests/Makefile.include
    A tests/libqos/rtas.c
    A tests/libqos/rtas.h
    M tests/libqtest.c
    M tests/libqtest.h
    A tests/rtas-test.c

  Log Message:
  -----------
  tests: add RTAS command in the protocol

Add a first test to validate the protocol:

- rtas/get-time-of-day compares the time
  from the guest with the time from the host.

Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a70ab357cd0b36c34f77803bd6710480cb2910d9
      
https://github.com/qemu/qemu/commit/a70ab357cd0b36c34f77803bd6710480cb2910d9
  Author: Greg Kurz <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: add sPAPR tests

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 5375c83b1e0e76972cfa0c78ce5b14e525e79104
      
https://github.com/qemu/qemu/commit/5375c83b1e0e76972cfa0c78ce5b14e525e79104
  Author: John Arbuckle <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    A include/hw/input/adb-keys.h

  Log Message:
  -----------
  adb-keys.h: initial commit

Add the adb-keys.h file. It maps ADB transition key codes with values.

Signed-off-by: John Arbuckle <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 5a1f4971863705f588ec79fce2ac8a3392e2a57e
      
https://github.com/qemu/qemu/commit/5a1f4971863705f588ec79fce2ac8a3392e2a57e
  Author: John Arbuckle <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M hw/input/adb.c

  Log Message:
  -----------
  adb.c: add support for QKeyCode

The old pc scancode translation is replaced with QEMU's QKeyCode. This is just
a mechanical substitution, which a number of broken mappings left in.

Signed-off-by: John Arbuckle <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 25c01db74b58d62cc4a2239ffe9badd5227c3538
      
https://github.com/qemu/qemu/commit/25c01db74b58d62cc4a2239ffe9badd5227c3538
  Author: John Arbuckle <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M hw/input/adb.c

  Log Message:
  -----------
  adb.c: correct several key assignments

The original pc_to_adb_keycode mapping did have several keys that were
incorrectly mapped. This patch fixes these mappings.

Signed-off-by: John Arbuckle <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f366e729f9231e7176e96dba16ddfb6b4b3ab1a8
      
https://github.com/qemu/qemu/commit/f366e729f9231e7176e96dba16ddfb6b4b3ab1a8
  Author: John Arbuckle <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M hw/input/adb.c

  Log Message:
  -----------
  adb.c: prevent NO_KEY value from going to guest

The NO_KEY value should not be sent to the guest. This patch drops that value.

Signed-off-by: John Arbuckle <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 24ac7755d751ed01ae53f7537b2ec90fe016d599
      
https://github.com/qemu/qemu/commit/24ac7755d751ed01ae53f7537b2ec90fe016d599
  Author: Laurent Vivier <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M hw/ppc/spapr_drc.c
    M hw/ppc/trace-events

  Log Message:
  -----------
  spapr_drc: convert to trace framework instead of DPRINTF

Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Eric Blake <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 028ec3cee3872fca661a5339b5b75b965f593597
      
https://github.com/qemu/qemu/commit/028ec3cee3872fca661a5339b5b75b965f593597
  Author: Laurent Vivier <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M hw/ppc/spapr_rtas.c
    M hw/ppc/trace-events

  Log Message:
  -----------
  spapr_rtas: convert to trace framework instead of DPRINTF

Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Eric Blake <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 7ab6a501c6c14c608043f918a680af9faaa38939
      
https://github.com/qemu/qemu/commit/7ab6a501c6c14c608043f918a680af9faaa38939
  Author: Laurent Vivier <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M hw/ppc/spapr_vio.c
    M hw/ppc/trace-events

  Log Message:
  -----------
  spapr_vio: convert to trace framework instead of DPRINTF

Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Eric Blake <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: e8bb33de42bdb17447a46e1b8448032b88b2cd54
      
https://github.com/qemu/qemu/commit/e8bb33de42bdb17447a46e1b8448032b88b2cd54
  Author: Laurent Vivier <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M hw/net/spapr_llan.c
    M hw/net/trace-events

  Log Message:
  -----------
  spapr_llan: convert to trace framework instead of DPRINTF

Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Eric Blake <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f19661c8b1f7f460c47ca7306a05eca22c6c5c68
      
https://github.com/qemu/qemu/commit/f19661c8b1f7f460c47ca7306a05eca22c6c5c68
  Author: Laurent Vivier <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M hw/scsi/spapr_vscsi.c
    M hw/scsi/trace-events

  Log Message:
  -----------
  spapr_vscsi: convert to trace framework instead of DPRINTF

Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Eric Blake <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 09bfe50d57d1986f8b3d0fd01ce32e303204c283
      
https://github.com/qemu/qemu/commit/09bfe50d57d1986f8b3d0fd01ce32e303204c283
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: consolidate load operations

Implement macro to consolidate load operations using newer
tcg_gen_qemu_ld functions.

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4f364fe76f9288bd30b418ecfd007a08412c4456
      
https://github.com/qemu/qemu/commit/4f364fe76f9288bd30b418ecfd007a08412c4456
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/translate.c
    M target-ppc/translate/fp-impl.inc.c
    M target-ppc/translate/spe-impl.inc.c
    M target-ppc/translate/vmx-impl.inc.c
    M target-ppc/translate/vsx-impl.inc.c

  Log Message:
  -----------
  target-ppc: convert ld64 to use new macro

Use macro for ld64 as well, this changes the function signature from
gen_qemu_ld64 => gen_qemu_ld64_i64. Replace this at all the call sites.

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: ff5f3981a291bdf37ba78bedb499af45cf04253b
      
https://github.com/qemu/qemu/commit/ff5f3981a291bdf37ba78bedb499af45cf04253b
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: convert ld[16,32,64]ur to use new macro

Make byte-swap routines use the common GEN_QEMU_LOAD macro

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 761a89c6419132e612f7c9f773ea42872134bb88
      
https://github.com/qemu/qemu/commit/761a89c6419132e612f7c9f773ea42872134bb88
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: consolidate store operations

Implement macro to consolidate store operations using newer
tcg_gen_qemu_st function.

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 2468f23dcb5b74ef882f3a3a5dd0a00bf0a71bb7
      
https://github.com/qemu/qemu/commit/2468f23dcb5b74ef882f3a3a5dd0a00bf0a71bb7
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/translate.c
    M target-ppc/translate/fp-impl.inc.c
    M target-ppc/translate/fp-ops.inc.c
    M target-ppc/translate/spe-impl.inc.c
    M target-ppc/translate/vmx-impl.inc.c
    M target-ppc/translate/vsx-impl.inc.c

  Log Message:
  -----------
  target-ppc: convert st64 to use new macro

Use macro for st64 as well, this changes the function signature from
gen_qemu_st64 => gen_qemu_st64_i64. Replace this at all the call sites.

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 804108aaf9aa2256534c6ef8e6736934a2ec79c8
      
https://github.com/qemu/qemu/commit/804108aaf9aa2256534c6ef8e6736934a2ec79c8
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: convert st[16,32,64]r to use new macro

Make byte-swap routines use the common GEN_QEMU_STORE macro

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 48793c95c963c3def3b6f3ecdbf89ec098d5e494
      
https://github.com/qemu/qemu/commit/48793c95c963c3def3b6f3ecdbf89ec098d5e494
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: consolidate load with reservation

Use tcg_gen_qemu_ld in the load with reservation instructions.

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: aa2008af0c1cd26f6a7c522825438f8d1d3de272
      
https://github.com/qemu/qemu/commit/aa2008af0c1cd26f6a7c522825438f8d1d3de272
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: move out stqcx impementation

Being a 16byte operation, qemu_ld/st still does not support this. Move
this out so other store operation can use qemu_ld/st in the following
patch. Also, convert it to two MO_Q operations for stqcx.

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 2391b3577365bfa16009268a16dc7df9a71460c7
      
https://github.com/qemu/qemu/commit/2391b3577365bfa16009268a16dc7df9a71460c7
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: consolidate store conditional

Use tcg_gen_qemu_st store conditional instructions.

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f113283525a46c16ee078caeefbc82b26aada86a
      
https://github.com/qemu/qemu/commit/f113283525a46c16ee078caeefbc82b26aada86a
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/translate.c
    M target-ppc/translate/vsx-impl.inc.c
    M target-ppc/translate/vsx-ops.inc.c

  Log Message:
  -----------
  target-ppc: add xxspltib instruction

xxspltib: VSX Vector Splat Immediate Byte

Copy the immediate byte in each byte of target VSR

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 740ae9a27f97be6f9139905700d949b4184a5df7
      
https://github.com/qemu/qemu/commit/740ae9a27f97be6f9139905700d949b4184a5df7
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/translate.c
    M target-ppc/translate/vsx-impl.inc.c
    M target-ppc/translate/vsx-ops.inc.c

  Log Message:
  -----------
  target-ppc: add lxsi[bw]zx instruction

lxsibzx - Load VSX Scalar as Integer Byte & Zero Indexed
lxsihzx - Load VSX Scalar as Integer Halfword & Zero Indexed

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: ddb9ac50ae999c8970fc5b145b0830b61d4da3f4
      
https://github.com/qemu/qemu/commit/ddb9ac50ae999c8970fc5b145b0830b61d4da3f4
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/translate.c
    M target-ppc/translate/vsx-impl.inc.c
    M target-ppc/translate/vsx-ops.inc.c

  Log Message:
  -----------
  target-ppc: add stxsi[bh]x instruction

stxsibx - Store VSX Scalar as Integer Byte Indexed
stxsihx - Store VSX Scalar as Integer Halfword Indexed

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: fec5c62a6434bc306906972e276c5a6f2cafdd9a
      
https://github.com/qemu/qemu/commit/fec5c62a6434bc306906972e276c5a6f2cafdd9a
  Author: Ravi Bangoria <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: implement darn instruction

darn: Deliver A Random Number

Currently return invalid random number for all the case. This needs
proper algorithm to provide cryptographically suitable random data.
Reading from /dev/random can block and that is not an expected behaviour
while the cpu instruction is getting executed. Moreover, /dev/random
would only work for linux-user

Signed-off-by: Ravi Bangoria <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
[dwg: Added minor clang warning fix for ppc32 target]
Signed-off-by: David Gibson <address@hidden>


  Commit: 7ebaf7955603cc50988e0eafd5e6074320fefc70
      
https://github.com/qemu/qemu/commit/7ebaf7955603cc50988e0eafd5e6074320fefc70
  Author: Bharata B Rao <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_cpu_core.c
    M include/hw/ppc/spapr_cpu_core.h
    M target-ppc/kvm.c

  Log Message:
  -----------
  spapr: Introduce sPAPRCPUCoreClass

Each spapr cpu core type defines an instance_init routine which just
populates the CPU class name. This can be done in the class_init
commonly for all core types which simplifies the registration.
This is inspired by how PowerNV core types are registered.

Certain types of spapr cpu cores ('host' and generic type based on host
CPU) are initialized in target-ppc/kvm.c. To convert these type
registrations to use class_init, we need to expose
spapr_cpu_core_class_init() outside of spapr_cpu_core.c.

Commit d11b268e1765 added a generic sPAPR CPU core family
type to support cases like POWER8 CPU type on POWER8E host CPU.
Switching to class_init would fix such scenarios to use the right
CPU thread type instead of defaulting to host-powerpc64-cpu.

In an unrelated cleanup, fix a typo in .get_hotplug_handler routine.

Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a8a6d53e3626e96d5a37b9eb6dc6ce759714502e
      
https://github.com/qemu/qemu/commit/a8a6d53e3626e96d5a37b9eb6dc6ce759714502e
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/helper_regs.h
    M target-ppc/mmu-hash64.c
    M target-ppc/mmu_helper.c

  Log Message:
  -----------
  target-ppc: add TLB_NEED_LOCAL_FLUSH flag

Introduces bit-flag in CPUPPCState::tlb_need_flush:

  TLB_NEED_LOCAL_FLUSH (0x1) - Flush local tlb

This would indicate a pending local tlb flush (isync instructions,
interrupts, ...)

Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: e3cffe6fad29e07d401eabb913a6d88501d5c143
      
https://github.com/qemu/qemu/commit/e3cffe6fad29e07d401eabb913a6d88501d5c143
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M hw/ppc/spapr_hcall.c
    M target-ppc/excp_helper.c
    M target-ppc/helper.h
    M target-ppc/helper_regs.h
    M target-ppc/mmu_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: add flag in check_tlb_flush()

We flush the qemu TLB lazily. check_tlb_flush is called whenever we hit
a context synchronizing event or instruction that requires a pending
flush to be performed.

However, we fail to handle broadcast TLB flush operations. In order to
fix that efficiently, we want to differentiate whether check_tlb_flush()
needs to only apply pending local flushes (isync instructions,
interrupts, ...) or also global pending flush operations. The latter is
only needed when executing instructions that are defined architecturally
as synchronizing global TLB flush operations. This in our case is
ptesync on BookS and tlbsync on BookE along with the paravirtualized
hypervisor calls.

Signed-off-by: Nikunj A Dadhania <address@hidden>
[dwg: Changed gen_check_tlb_flush() to also take a bool, and fixed
 some spelling errors in commit message]
Signed-off-by: David Gibson <address@hidden>


  Commit: d76ab5e1c7db5f064700b9c3cb0924ccfd9017e5
      
https://github.com/qemu/qemu/commit/d76ab5e1c7db5f064700b9c3cb0924ccfd9017e5
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M hw/ppc/spapr_hcall.c
    M target-ppc/cpu.h
    M target-ppc/helper_regs.h
    M target-ppc/mmu-hash64.c
    M target-ppc/mmu_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: tlbie/tlbivax should have global effect

tlbie (BookS) and tlbivax (BookE) plus the H_CALLs(pseries) should have
a global effect.

Introduces TLB_NEED_GLOBAL_FLUSH flag. During lazy tlb flush, after
taking care of pending local flushes, check broadcast flush(at context
synchronizing event ptesync/tlbsync, etc) is needed. Depending on the
bitmask state of the tlb_need_flush, tlb is flushed from other cpus if
needed and the flags are cleared.

Suggested-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[dwg: Use 'true' instead of '1' for call to check_tlb_flush()]
Signed-off-by: David Gibson <address@hidden>


  Commit: 5145ad4fad099983887c6e6caa2354376005226f
      
https://github.com/qemu/qemu/commit/5145ad4fad099983887c6e6caa2354376005226f
  Author: Nathan Whitehorn <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M hw/ppc/spapr.c
    M target-ppc/kvm.c
    M target-ppc/kvm_ppc.h

  Log Message:
  -----------
  Enable H_CLEAR_MOD and H_CLEAR_REF hypercalls on KVM/PPC64.

These are mandatory per PAPR and available on Linux 4.3 and newer kernels. The 
calls in question are required to run FreeBSD guests with reasonable 
performance, so enable them if possible.

Signed-off-by: Nathan Whitehorn <address@hidden>
[dwg: Added a stub to fix compile without KVM (e.g. on x86 host)]
Signed-off-by: David Gibson <address@hidden>


  Commit: 056b977521a907e9b84c0ad0017a082ff56e69f3
      
https://github.com/qemu/qemu/commit/056b977521a907e9b84c0ad0017a082ff56e69f3
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M hw/intc/xics.c

  Log Message:
  -----------
  ppc/xics: account correct irq status

Fix inconsistent irq status, because of this in the trace logs, for e.g.
LSI status was 0x7, i.e. XICS_STATUS_ASSERTED, XICS_STATUS_SENT and
XICS_STATUS_REJECTED all set, which did not make sense. So the REJECTED
would have been set in earlier interrupt cycle, and then asserted and
sent in this current one.

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 15ed653fa49a7ddda2034db5d722fd6c2d439dd8
      
https://github.com/qemu/qemu/commit/15ed653fa49a7ddda2034db5d722fd6c2d439dd8
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M include/hw/ppc/xics.h

  Log Message:
  -----------
  ppc/xics: An ICS with offset 0 is assumed to be uninitialized

This will make life easier for dealing with dynamically configured
ICSes such as PHB3

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0d594f5565837fe2886a8aa307ef8abb65eab8f7
      
https://github.com/qemu/qemu/commit/0d594f5565837fe2886a8aa307ef8abb65eab8f7
  Author: Thomas Huth <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M target-ppc/kvm.c

  Log Message:
  -----------
  ppc/kvm: Mark 64kB page size support as disabled if not available

QEMU currently refuses to start with KVM-PR and only prints out

        qemu: fatal: Unknown MMU model 851972

when being started there. This is because commit 4322e8ced5aaac719
("ppc: Fix 64K pages support in full emulation") introduced a new
POWERPC_MMU_64K bit to indicate support for this page size, but
it never gets cleared on KVM-PR if the host kernel does not support
this. Thus we've got to turn off this bit in the mmu_model for KVM-PR.

Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 58eb53083ccac82bc9c8e4b5f0800dcc47d22927
      
https://github.com/qemu/qemu/commit/58eb53083ccac82bc9c8e4b5f0800dcc47d22927
  Author: Michael Walle <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M linux-user/elfload.c

  Log Message:
  -----------
  linux-user: ppc64: fix ARCH_206 bit in AT_HWCAP

Only the POWER[789] CPUs should have the ARCH_206 bit set. This is what the
linux kernel does. I guess this was also the intention of commit 0e019746.
We have to make sure all *206 bits are set.

Before this patch, the flags check in the GET_FEATURES2 macro returned true
if _any_ bit was set. This worked well as long as there was only one bit
set in the 'flag' parameter. But as explained before, we have to make sure
all bits in the 'flag' parameter are set.

Signed-off-by: Michael Walle <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 27a83f8e7ed63ced7e36c47a42f46ab44ee02bd8
      
https://github.com/qemu/qemu/commit/27a83f8e7ed63ced7e36c47a42f46ab44ee02bd8
  Author: David Gibson <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M monitor.c

  Log Message:
  -----------
  monitor: fix crash for platforms without a CPU 0

Now that we allow CPU hot unplug on a few platforms, we can end up in a
situation where we don't have a CPU with index 0.  Or at least we could,
if we didn't have code to explicitly prohibit unplug of CPU 0.

Longer term we want to allow CPU 0 unplug, this patch is an early step in
allowing this, by removing an assumption in the monitor code that CPU 0
always exists.

Signed-off-by: Cédric Le Goater <address@hidden>
[dwg: Rewrote commit message to better explain background]
Reviewed-by: Igor Mammedov <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Reviewed-by: Luiz Capitulino <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4814401fa01271235df2ac60fafc831bd3d624f3
      
https://github.com/qemu/qemu/commit/4814401fa01271235df2ac60fafc831bd3d624f3
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M hw/ppc/spapr_pci.c
    M include/hw/pci-host/spapr.h

  Log Message:
  -----------
  spapr_pci: Add numa node id

This adds a numa id property to a PHB to allow linking passed PCI device
to CPU/memory. It is up to the management stack to do CPU/memory pinning
to the node with the actual PCI device.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
[dwg: Renamed property from "node" to "numa_node" to match the similar
 one in the pxb device]
Signed-off-by: David Gibson <address@hidden>


  Commit: c229472af095765cdbae95ad057b170d98f81e25
      
https://github.com/qemu/qemu/commit/c229472af095765cdbae95ad057b170d98f81e25
  Author: Peter Maydell <address@hidden>
  Date:   2016-09-23 (Fri, 23 Sep 2016)

  Changed paths:
    M MAINTAINERS
    M hw/input/adb.c
    M hw/intc/xics.c
    M hw/net/spapr_llan.c
    M hw/net/trace-events
    M hw/ppc/spapr.c
    M hw/ppc/spapr_cpu_core.c
    M hw/ppc/spapr_drc.c
    M hw/ppc/spapr_hcall.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_rtas.c
    M hw/ppc/spapr_vio.c
    M hw/ppc/trace-events
    M hw/scsi/spapr_vscsi.c
    M hw/scsi/trace-events
    A include/hw/input/adb-keys.h
    M include/hw/pci-host/spapr.h
    M include/hw/ppc/spapr_cpu_core.h
    A include/hw/ppc/spapr_rtas.h
    M include/hw/ppc/xics.h
    M linux-user/elfload.c
    M linux-user/main.c
    M linux-user/ppc/syscall_nr.h
    M linux-user/signal.c
    M monitor.c
    M qtest.c
    M target-ppc/cpu.h
    M target-ppc/excp_helper.c
    M target-ppc/helper.h
    M target-ppc/helper_regs.h
    M target-ppc/int_helper.c
    M target-ppc/kvm.c
    M target-ppc/kvm_ppc.h
    M target-ppc/mmu-hash64.c
    M target-ppc/mmu_helper.c
    M target-ppc/translate.c
    M target-ppc/translate/fp-impl.inc.c
    M target-ppc/translate/fp-ops.inc.c
    M target-ppc/translate/spe-impl.inc.c
    M target-ppc/translate/vmx-impl.inc.c
    M target-ppc/translate/vmx-ops.inc.c
    M target-ppc/translate/vsx-impl.inc.c
    M target-ppc/translate/vsx-ops.inc.c
    M tests/Makefile.include
    M tests/libqos/libqos-pc.c
    A tests/libqos/libqos-spapr.c
    A tests/libqos/libqos-spapr.h
    M tests/libqos/libqos.c
    A tests/libqos/malloc-spapr.c
    A tests/libqos/malloc-spapr.h
    A tests/libqos/rtas.c
    A tests/libqos/rtas.h
    M tests/libqtest.c
    M tests/libqtest.h
    A tests/rtas-test.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.8-20160923' into 
staging

ppc patch queue 2016-09-23

This pull request supersedes ppc-for-2.8-20160922.  There was a clang
build error in that, and I've also added one extra patch in the new pull.

Included in this set of ppc and spapr patches are:
    * TCG implementations for more POWER9 instructions
    * Some preliminary XICS fixes in preparataion for the pnv machine type
    * A significant ADB (Macintosh kbd/mouse) cleanup
    * Some conversions to use trace instead of debug macros
    * Fixes to correctly handle global TLB flush synchronization in
      TCG.  This is already a bug, but it will have much more impact
      when we get MTTCG
    * Add more qtest testcases for Power
    * Some MAINTAINERS updates
    * Assorted bugfixes
    * Add the basics of NUMA associativity to the spapr PCI host bridge

This touches some test files and monitor.c which are technically
outside the ppc code, but coming through this tree because the changes
are primarily of interest to ppc.

# gpg: Signature made Fri 23 Sep 2016 08:14:47 BST
# gpg:                using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>"
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg:                 aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.8-20160923: (45 commits)
  spapr_pci: Add numa node id
  monitor: fix crash for platforms without a CPU 0
  linux-user: ppc64: fix ARCH_206 bit in AT_HWCAP
  ppc/kvm: Mark 64kB page size support as disabled if not available
  ppc/xics: An ICS with offset 0 is assumed to be uninitialized
  ppc/xics: account correct irq status
  Enable H_CLEAR_MOD and H_CLEAR_REF hypercalls on KVM/PPC64.
  target-ppc: tlbie/tlbivax should have global effect
  target-ppc: add flag in check_tlb_flush()
  target-ppc: add TLB_NEED_LOCAL_FLUSH flag
  spapr: Introduce sPAPRCPUCoreClass
  target-ppc: implement darn instruction
  target-ppc: add stxsi[bh]x instruction
  target-ppc: add lxsi[bw]zx instruction
  target-ppc: add xxspltib instruction
  target-ppc: consolidate store conditional
  target-ppc: move out stqcx impementation
  target-ppc: consolidate load with reservation
  target-ppc: convert st[16,32,64]r to use new macro
  target-ppc: convert st64 to use new macro
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/4c892756fd13...c229472af095
[Prev in Thread]
Current Thread
[Next in Thread]
[Qemu-commits] [qemu/qemu] b5d550: MAINTAINERS: Add some missing ppc-related files, GitHub <=
Prev by Date: [Qemu-commits] [qemu/qemu] 0679f9: docker: Handle exceptions when looking for docker ...
Next by Date: [Qemu-commits] [qemu/qemu] e9deaa: target-mips: add 24KEc CPU definition
Previous by thread: [Qemu-commits] [qemu/qemu] 0679f9: docker: Handle exceptions when looking for docker ...
Next by thread: [Qemu-commits] [qemu/qemu] e9deaa: target-mips: add 24KEc CPU definition
Index(es):
- Date
- Thread