[Qemu-commits] [qemu/qemu] 1b1746: xics_kvm: drop extra checking of kern

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[Qemu-commits] [qemu/qemu] 1b1746: xics_kvm: drop extra checking of kern

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 1b1746: xics_kvm: drop extra checking of kernel_xics_fd
Date:	Thu, 08 Sep 2016 04:30:07 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 1b1746a4368c960652ca7e4a36aea8a65fa9f319
      
https://github.com/qemu/qemu/commit/1b1746a4368c960652ca7e4a36aea8a65fa9f319
  Author: Greg Kurz <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M hw/intc/xics_kvm.c

  Log Message:
  -----------
  xics_kvm: drop extra checking of kernel_xics_fd

We abort a few lines above if kernel_xics_fd == -1.

This is only code cleanup.

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 7804c353a9f93c3eeb3eb744ee4c962fd34bc760
      
https://github.com/qemu/qemu/commit/7804c353a9f93c3eeb3eb744ee4c962fd34bc760
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_events.c
    A include/hw/ppc/fdt.h

  Log Message:
  -----------
  hw/ppc: include fdt helper routine in a common file

spapr_pci would also be a good candidate but the macro _FDT is
slightly different. It returns and does not exit.

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 706d64675ac2cd72d803cb2f28aa3a332c402ba9
      
https://github.com/qemu/qemu/commit/706d64675ac2cd72d803cb2f28aa3a332c402ba9
  Author: Aneesh Kumar K.V <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/cpu-models.c
    M target-ppc/cpu-models.h
    M target-ppc/cpu-qom.h
    M target-ppc/mmu_helper.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: Introduce Power9 family

The patch adds CPU PVR definition for POWER9 and enables QEMU to launch
guests/linux-user in TCG mode.

Signed-off-by: Aneesh Kumar K.V <address@hidden>
[ Added POWER9 alias, POWER9 SPAPR core and dropped MMU defines ]
Signed-off-by: Nikunj A Dadhania <address@hidden>
[dwg: Dropped sPAPR core type again for now]
Signed-off-by: David Gibson <address@hidden>


  Commit: eb640b13a39b13011273bcaf19e39c81c1d1b03b
      
https://github.com/qemu/qemu/commit/eb640b13a39b13011273bcaf19e39c81c1d1b03b
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: Introduce POWER ISA 3.0 flag

This flag will be used for POWER9 instructions.

Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: c5b2b9ce126a629b45a11353bf315078c21c6904
      
https://github.com/qemu/qemu/commit/c5b2b9ce126a629b45a11353bf315078c21c6904
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: adding addpcis instruction

ISA 3.0 instruction for adding immediate value shifted with next
instruction address and return the result in the target register.

Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f2442ef93c5f032901baceb52811924b71516266
      
https://github.com/qemu/qemu/commit/f2442ef93c5f032901baceb52811924b71516266
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: add cmprb instruction

ISA 3.0 Compare Ranged Byte instruction useful for
isupper/islower/isaplha kind of operation.

Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: af2c66200ec1458e92a97bbc505244a4817e3f84
      
https://github.com/qemu/qemu/commit/af2c66200ec1458e92a97bbc505244a4817e3f84
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: add modulo word operations

Adding following instructions:

moduw: Modulo Unsigned Word
modsw: Modulo Signed Word

Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 063cf14fe3206ffb37f063245787ccd78f684e2c
      
https://github.com/qemu/qemu/commit/063cf14fe3206ffb37f063245787ccd78f684e2c
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: add modulo dword operations

Adding following instructions for ISA3.0 support

modud: Modulo Unsigned Dword
modsd: Modulo Signed Dword

Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden
Signed-off-by: David Gibson <address@hidden>


  Commit: e91d95b27703c6d67370cb3aa78ed5e4f8b03bbb
      
https://github.com/qemu/qemu/commit/e91d95b27703c6d67370cb3aa78ed5e4f8b03bbb
  Author: Sandipan Das <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: add cnttzd[.] instruction

Add ISA3.0 Count trailing zeros double word

Signed-off-by: Sandipan Das <address@hidden>
[ added ISA300 flag ]
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b35344e4a0968fd1341ec1c1ed2e6b5c0d851542
      
https://github.com/qemu/qemu/commit/b35344e4a0968fd1341ec1c1ed2e6b5c0d851542
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: add cnttzw[.] instruction

Add ISA3.0: Count trailing zeros word instruction.

Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 082ce33005d81ff45b929e826ac48a5696059efc
      
https://github.com/qemu/qemu/commit/082ce33005d81ff45b929e826ac48a5696059efc
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: add cmpeqb instruction

Search a byte in the stream of 8bytes provided in the register

Suggested-by: Richard Henderson <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: dc2ee038daa88222c4e333ffcc81070b8d0656d2
      
https://github.com/qemu/qemu/commit/dc2ee038daa88222c4e333ffcc81070b8d0656d2
  Author: Vivek Andrew Sha <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: add setb instruction

The CR number is provided in the opcode as - BFA (11:13)

Returns:
  -1 if bit 0 of CR field is set
   1 if bit 1 of CR field is set
   0 otherwise.

Signed-off-by: Vivek Andrew Sha <address@hidden>
[ reworded commit, used 32bit ops as crf is 32bits ]
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: aeeb044c7bd59ced2b630bf82f644a2137ac9a6f
      
https://github.com/qemu/qemu/commit/aeeb044c7bd59ced2b630bf82f644a2137ac9a6f
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: add maddld instruction

maddld: Multiply-Add Low Doubleword

Multiplies two 64-bit registers (RA * RB), adds third register(RC) to
the result(quadword) and returns the lower dword in the target
register(RT).

Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 5f29cc829225f777ca4697cb955572feebaf0748
      
https://github.com/qemu/qemu/commit/5f29cc829225f777ca4697cb955572feebaf0748
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: add maddhd and maddhdu instruction

maddhd: Multiply-Add High Doubleword
maddhdu: Multiply-Add High Doubleword Unsigned

Above two instruction are dual form and differ by 1 bit
(31st bit)

Multiplies two 64-bit registers (RA * RB), adds third register(RC) to
the result(quadword) and returns the higher dword in the target
register(RT).

Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 323ad19bcc601d3ec9cb6f0f5b4d67b602fc519e
      
https://github.com/qemu/qemu/commit/323ad19bcc601d3ec9cb6f0f5b4d67b602fc519e
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: introduce opc4 for Expanded Opcode

ISA 3.0 has introduced EO - Expanded Opcode. Introduce third level
indirect opcode table and corresponding parsing routines.

EO (11:12) Expanded opcode field
Formats: XX1

EO (11:15) Expanded opcode field
Formats: VX, X, XX2

Signed-off-by: Nikunj A Dadhania <address@hidden>
[dwg: Trivial checkpatch fixup]
Signed-off-by: David Gibson <address@hidden>


  Commit: db789c6cd3383e472c2de0115c3d3fa4b2e5c825
      
https://github.com/qemu/qemu/commit/db789c6cd3383e472c2de0115c3d3fa4b2e5c825
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/excp_helper.c

  Log Message:
  -----------
  ppc: Provide basic raise_exception_* functions

Instead of using the same helpers called from translate.c, let's have
a bunch of functions that take the various argument combinations,
especially the retaddr which will be needed in subsequent patches,
and leave the helpers to be just that, helpers for translate.c

We don't yet convert all users, we'll go through them in subsequent
patches.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
--

v2. Fix raise_exception_ra() to properly pass raddr
Signed-off-by: David Gibson <address@hidden>


  Commit: f96511215da118ffc635c2c3698c60bf519372ce
      
https://github.com/qemu/qemu/commit/f96511215da118ffc635c2c3698c60bf519372ce
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c
    A target-ppc/translate/fp-impl.c
    A target-ppc/translate/fp-ops.c

  Log Message:
  -----------
  ppc: Move classic fp ops out of translate.c

Makes things a bit more manageable

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4083de6b53a9f5a87cf20ed9465d4956d8169591
      
https://github.com/qemu/qemu/commit/4083de6b53a9f5a87cf20ed9465d4956d8169591
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c
    A target-ppc/translate/spe-impl.c
    A target-ppc/translate/spe-ops.c

  Log Message:
  -----------
  ppc: Move embedded spe ops out of translate.c

Makes things a bit more manageable

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 8b25cdd371e99221b27ddcfaa137cfd6c56df7c1
      
https://github.com/qemu/qemu/commit/8b25cdd371e99221b27ddcfaa137cfd6c56df7c1
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c
    A target-ppc/translate/dfp-impl.c
    A target-ppc/translate/dfp-ops.c

  Log Message:
  -----------
  ppc: Move DFP ops out of translate.c

Makes things a bit more manageable

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0304af897b4f2b0835808e2ede155afb50408432
      
https://github.com/qemu/qemu/commit/0304af897b4f2b0835808e2ede155afb50408432
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c
    A target-ppc/translate/vmx-impl.c
    A target-ppc/translate/vmx-ops.c

  Log Message:
  -----------
  ppc: Move VMX ops out of translate.c

Makes things a bit more manageable

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 3014427af550dfda54a067b15f7c69bcc23cec05
      
https://github.com/qemu/qemu/commit/3014427af550dfda54a067b15f7c69bcc23cec05
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c
    A target-ppc/translate/vsx-impl.c
    A target-ppc/translate/vsx-ops.c

  Log Message:
  -----------
  ppc: Move VSX ops out of translate.c

Makes things a bit more manageable

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f63fbc00d40b4a1cb1780b9abcdc019fae20ab1f
      
https://github.com/qemu/qemu/commit/f63fbc00d40b4a1cb1780b9abcdc019fae20ab1f
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/fpu_helper.c

  Log Message:
  -----------
  ppc: Rename fload_invalid_op_excp to float_invalid_op_excp

No other change

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a93ecff935af312d49e4c9349b6527813af303f5
      
https://github.com/qemu/qemu/commit/a93ecff935af312d49e4c9349b6527813af303f5
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/fpu_helper.c

  Log Message:
  -----------
  ppc: Make float_invalid_op_excp() pass the return address

Instead of relying on NIP having been updated already

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 44f35bd1ac3dccd4e7fbd5d443c84e959c8a1a14
      
https://github.com/qemu/qemu/commit/44f35bd1ac3dccd4e7fbd5d443c84e959c8a1a14
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/fpu_helper.c

  Log Message:
  -----------
  ppc: Make float_check_status() pass the return address

Instead of relying on NIP having been updated already.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[dwg: Fold in fix to mark function always_inline]
Signed-off-by: David Gibson <address@hidden>


  Commit: ef24726e4847d61ca647e3ae8dc47422ca721259
      
https://github.com/qemu/qemu/commit/ef24726e4847d61ca647e3ae8dc47422ca721259
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate/fp-impl.c
    M target-ppc/translate/vsx-impl.c

  Log Message:
  -----------
  ppc: Don't update the NIP in floating point generated code

This is no longer necessary as the helpers will properly retrieve
the return address.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 1b7d17cae4c31e7cf16abd7036f5a5ca5dee8c57
      
https://github.com/qemu/qemu/commit/1b7d17cae4c31e7cf16abd7036f5a5ca5dee8c57
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/excp_helper.c

  Log Message:
  -----------
  ppc: FP exceptions are always precise

We don't implement imprecise FP exceptions and using store_current
which sets SRR1 to the *previous* instruction never makes sense
for these. So let's be truthful and make them precise, which is
allowed by the architecture.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: e41029b378b4a65a0b89b5a8dc087aca6b5d012d
      
https://github.com/qemu/qemu/commit/e41029b378b4a65a0b89b5a8dc087aca6b5d012d
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/excp_helper.c
    M target-ppc/mem_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Don't update NIP in lswi/lswx/stswi/stswx

Instead, pass GETPC() result to the corresponding helpers. This
requires a bit of fiddling to get the PC (hopefully) right in
the case where we generate a program check, though the hacks there
are temporary, a subsequent patch will clean this all up by always
having the nip already set to the right instruction when taking
the fault.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[dwg: Fix trivial checkpatch warning]
Signed-off-by: David Gibson <address@hidden>


  Commit: af6d376ea18db87287a9e0de08fe23c68f2464a6
      
https://github.com/qemu/qemu/commit/af6d376ea18db87287a9e0de08fe23c68f2464a6
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/mem_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Don't update NIP in lmw/stmw/icbi

Instead, pass GETPC() result to the corresponding helpers.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: bd6fefe71cec5a0c7d2be4ac96307f25db56abf9
      
https://github.com/qemu/qemu/commit/bd6fefe71cec5a0c7d2be4ac96307f25db56abf9
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M linux-user/main.c
    M target-ppc/excp_helper.c
    M target-ppc/mmu_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Make tlb_fill() use new exception helper

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0f72b7c682811fc3281e3b5f4d467582550c6a51
      
https://github.com/qemu/qemu/commit/0f72b7c682811fc3281e3b5f4d467582550c6a51
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/mmu-hash64.c

  Log Message:
  -----------
  ppc: Fix source NIP on SLB related interrupts

We need to pass it to the raise helper since we don't update it
before the calls.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a13f0a9bc4e6f35be3f64bd7048eec565957a7d4
      
https://github.com/qemu/qemu/commit/a13f0a9bc4e6f35be3f64bd7048eec565957a7d4
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/timebase_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Don't update NIP in DCR access routines

This is no longer necessary as the helpers will properly retrieve
the return address when needed

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 57a2988b6f750548052254c20796be6d87d2ab9f
      
https://github.com/qemu/qemu/commit/57a2988b6f750548052254c20796be6d87d2ab9f
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/misc_helper.c
    M target-ppc/translate.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: Don't update NIP in facility unavailable interrupts

This is no longer necessary as the helpers will properly retrieve
the return address when needed. Also remove gen_update_current_nip()
which didn't seem to make much sense to me.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 8c8966e2188ade13c4ab9d3f8f4b12c99be0ade4
      
https://github.com/qemu/qemu/commit/8c8966e2188ade13c4ab9d3f8f4b12c99be0ade4
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/mmu_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Don't update NIP BookE 2.06 tlbwe

This is no longer necessary as the helpers will properly retrieve
the return address when needed.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 72073dcce0ad1e84b866e45bc60ccf459aa9fcd4
      
https://github.com/qemu/qemu/commit/72073dcce0ad1e84b866e45bc60ccf459aa9fcd4
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/excp_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Don't update NIP on conditional trap instructions

This is no longer necessary as the helpers will properly retrieve
the return address when needed.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 573708e3292a501e7f86ab13878a2799a1ec73ab
      
https://github.com/qemu/qemu/commit/573708e3292a501e7f86ab13878a2799a1ec73ab
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Don't update NIP if not taking alignment exceptions

Move the NIP update to after the conditional branch so that we
don't do it if we aren't going to take the alignment exception

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b00a3b3648c32cd1d2baaeef6d6a81e8d9341259
      
https://github.com/qemu/qemu/commit/b00a3b3648c32cd1d2baaeef6d6a81e8d9341259
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/mem_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Don't update NIP in dcbz and lscbx

Instead, pass GETPC() result to the corresponding helpers.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 3433b732a4c9abb413eb39a6badb63e83ad2288c
      
https://github.com/qemu/qemu/commit/3433b732a4c9abb413eb39a6badb63e83ad2288c
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/excp_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Make alignment exceptions suck less

The current alignment exception generation tries to load the opcode
to put in DSISR from a context where a cpu_ldl_code() is really not
a good idea. It might fault and longjmp out and that's not something
we want happening here.

Instead, pass the releavant opcode bits via the error_code.

There are a couple of cases of alignment interrupts that won't set
anything, the ones coming from access to direct store segments, but
that doesn't happen in practice, nobody used direct store segments
and they are gone from newer chips.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 22b56ee5682e64509621f9d5d303a0414e289b11
      
https://github.com/qemu/qemu/commit/22b56ee5682e64509621f9d5d303a0414e289b11
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Handle unconditional (always/never) traps at translation time

We don't need to call a helper for trap always and trap never
which are used by Linux under some circumstances.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
--

v2. Don't generate the helper call when trapping always
Signed-off-by: David Gibson <address@hidden>


  Commit: c9f82d013be0d8d9c5d9f51bb76e337a0a5a5cac
      
https://github.com/qemu/qemu/commit/c9f82d013be0d8d9c5d9f51bb76e337a0a5a5cac
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/mem_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Speed up dcbz

Use tlb_vaddr_to_host to do a fast path single translate for
the whole cache line. Also make the reservation check match
the entire range.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: fbc3b39b3974bd6d3960376a1d4898adbbd47787
      
https://github.com/qemu/qemu/commit/fbc3b39b3974bd6d3960376a1d4898adbbd47787
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Fix CFAR updates

We were one instruction off

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 5f2a6254522bd4cfb917822f678b117e6f005664
      
https://github.com/qemu/qemu/commit/5f2a6254522bd4cfb917822f678b117e6f005664
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Don't set access_type on all load/stores on hash64

We don't use it so let's not generate the updates.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 65f2475f1f3b46086dfeef9ba882ea3d9d909d57
      
https://github.com/qemu/qemu/commit/65f2475f1f3b46086dfeef9ba882ea3d9d909d57
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Use a helper to generate "LE unsupported" alignment interrupts

Some operations aren't allowed in LE mode, use a helper rather than
open coding the exception generation.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 5817355ed0d989c72713d89c8d1e9133ec376485
      
https://github.com/qemu/qemu/commit/5817355ed0d989c72713d89c8d1e9133ec376485
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: load/store multiple and string insns don't do LE

Just generate an alignment interrupt

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b07c32dc4bdda102803ed6699438fef059c8f408
      
https://github.com/qemu/qemu/commit/b07c32dc4bdda102803ed6699438fef059c8f408
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: implement branch-less divw[o][.]

While implementing modulo instructions figured out that the
implementation uses many branches. Change the logic to achieve the
branch-less code. Undefined value is set to dividend in case of invalid
input.

Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4110b586defd8499041275a9eca66264c344e823
      
https://github.com/qemu/qemu/commit/4110b586defd8499041275a9eca66264c344e823
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: implement branch-less divd[o][.]

Similar to divw, implement branch-less divd.

Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 217f6b88058fa5509ff721741862e26db071929a
      
https://github.com/qemu/qemu/commit/217f6b88058fa5509ff721741862e26db071929a
  Author: Sandipan Das <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/dfp_helper.c
    M target-ppc/helper.h
    M target-ppc/translate/dfp-impl.c
    M target-ppc/translate/dfp-ops.c

  Log Message:
  -----------
  target-ppc: add dtstsfi[q] instructions

DFP Test Significance Immediate [Quad]

Signed-off-by: Sandipan Das <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 377070595a5865a7db6fa671a1e84f149d80809a
      
https://github.com/qemu/qemu/commit/377070595a5865a7db6fa671a1e84f149d80809a
  Author: Sandipan Das <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate/vmx-impl.c
    M target-ppc/translate/vmx-ops.c

  Log Message:
  -----------
  target-ppc: add vabsdu[b,h,w] instructions

Adds following instructions:

vabsdub: Vector Absolute Difference Unsigned Byte
vabsduh: Vector Absolute Difference Unsigned Halfword
vabsduw: Vector Absolute Difference Unsigned Word

Signed-off-by: Sandipan Das <address@hidden>
[ use ISA300 define. Drop etype ]
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f7cc8466f1c29550b5ace0750813bc6c9190f604
      
https://github.com/qemu/qemu/commit/f7cc8466f1c29550b5ace0750813bc6c9190f604
  Author: Swapnil Bokade <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate/vmx-impl.c
    M target-ppc/translate/vmx-ops.c

  Log Message:
  -----------
  target-ppc: add vcmpnez[b,h,w][.] instructions

Adds following instructions:

vcmpnezb[.]: Vector Compare Not Equal or Zero Byte
vcmpnezh[.]: Vector Compare Not Equal or Zero Halfword
vcmpnezw[.]: Vector Compare Not Equal or Zero Word

Signed-off-by: Swapnil Bokade <address@hidden>
[ collapse switch case ]
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 5644a17567596eea8c4e16a8087dab9cc0292c6f
      
https://github.com/qemu/qemu/commit/5644a17567596eea8c4e16a8087dab9cc0292c6f
  Author: Vivek Andrew Sha <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate/vmx-impl.c
    M target-ppc/translate/vmx-ops.c

  Log Message:
  -----------
  target-ppc: add vslv instruction

vslv: Vector Shift Left Variable

Signed-off-by: Vivek Andrew Sha <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4004c1dbca3ac2399d51ba636b4de032448adc9f
      
https://github.com/qemu/qemu/commit/4004c1dbca3ac2399d51ba636b4de032448adc9f
  Author: Vivek Andrew Sha <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate/vmx-impl.c
    M target-ppc/translate/vmx-ops.c

  Log Message:
  -----------
  target-ppc: add vsrv instruction

Adds Vector Shift Right Variable instruction.

Signed-off-by: Vivek Andrew Sha <address@hidden>
[ reverse the order of computation to avoid temporary array ]
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 787bbe3711725c66c2c24b0afad487beb76fe9e7
      
https://github.com/qemu/qemu/commit/787bbe3711725c66c2c24b0afad487beb76fe9e7
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: add extswsli[.] instruction

extswsli : Extend Sign Word & Shift Left Immediate

Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 15848410af5caccb7ca419654e46b0ce42d6bf4b
      
https://github.com/qemu/qemu/commit/15848410af5caccb7ca419654e46b0ce42d6bf4b
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c
    R target-ppc/translate/dfp-impl.c
    A target-ppc/translate/dfp-impl.inc.c
    R target-ppc/translate/dfp-ops.c
    A target-ppc/translate/dfp-ops.inc.c
    R target-ppc/translate/fp-impl.c
    A target-ppc/translate/fp-impl.inc.c
    R target-ppc/translate/fp-ops.c
    A target-ppc/translate/fp-ops.inc.c
    R target-ppc/translate/spe-impl.c
    A target-ppc/translate/spe-impl.inc.c
    R target-ppc/translate/spe-ops.c
    A target-ppc/translate/spe-ops.inc.c
    R target-ppc/translate/vmx-impl.c
    A target-ppc/translate/vmx-impl.inc.c
    R target-ppc/translate/vmx-ops.c
    A target-ppc/translate/vmx-ops.inc.c
    R target-ppc/translate/vsx-impl.c
    A target-ppc/translate/vsx-impl.inc.c
    R target-ppc/translate/vsx-ops.c
    A target-ppc/translate/vsx-ops.inc.c

  Log Message:
  -----------
  ppc: Rename #include'd .c files to .inc.c

Also while at it, group the #include statements in translate.c

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: ce9863b7978976492efc2b57589516f3fcae79cb
      
https://github.com/qemu/qemu/commit/ce9863b7978976492efc2b57589516f3fcae79cb
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_drc.c
    M hw/ppc/spapr_iommu.c
    M hw/ppc/spapr_rtas.c
    M hw/ppc/spapr_vio.c
    M include/hw/ppc/fdt.h

  Log Message:
  -----------
  hw/ppc: use error_report instead of fprintf

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 3654fa95bc29e72c2eef22f26eb621af1f86feec
      
https://github.com/qemu/qemu/commit/3654fa95bc29e72c2eef22f26eb621af1f86feec
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M hw/ppc/Makefile.objs
    A hw/ppc/fdt.c
    M hw/ppc/spapr.c
    M include/hw/ppc/fdt.h

  Log Message:
  -----------
  hw/ppc: add a ppc_create_page_sizes_prop() helper routine

The exact same routine will be used in PowerNV.

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: dd2fa4f72d1ce44ce1635fe3a744bd47d8f2ab05
      
https://github.com/qemu/qemu/commit/dd2fa4f72d1ce44ce1635fe3a744bd47d8f2ab05
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M hw/misc/macio/macio.c

  Log Message:
  -----------
  ppc: Fix macio ESCC legacy mapping

The current mapping, while correct for the base ports (which is all the
driver uses these days), is wrong for the extended registers.

I suspect the bugs come from incorrect tables in the CHRP IO Ref document,
I have verified the new values here match Apple's MacTech.pdf.

Note: Nothing that I know of actually uses these registers so it's not a
huge deal, but this patch has the added advantage of adding comments to
document what the registers are.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: ba4a8df83f474be1ba02510f960e5224f29d229c
      
https://github.com/qemu/qemu/commit/ba4a8df83f474be1ba02510f960e5224f29d229c
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M linux-user/main.c

  Log Message:
  -----------
  ppc: Fix catching some segfaults in user mode

The usermode "translate" code generates an error code value that
has the "is_write" bit set, which causes our switch/case to miss
and display "Invalid segfault errno" and a spurrious second state
dump. Fix it.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4f5d326046fa522010c0a66f1bcaac9068253085
      
https://github.com/qemu/qemu/commit/4f5d326046fa522010c0a66f1bcaac9068253085
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M linux-user/main.c

  Log Message:
  -----------
  ppc: Stop dumping state on all exceptions in linux-user

Other archs don't do it, some programs catch signals just fine
and those dumps just clutter the output. Keep the dumps for cases
that aren't supposed to happen such as unknown codes.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: accc60c47c9b57f49865d1bed6df3d3085fec81d
      
https://github.com/qemu/qemu/commit/accc60c47c9b57f49865d1bed6df3d3085fec81d
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Don't generate dead code on unconditional branches

We are always generating the "else" case of the condition even when
generating an unconditional branch that will never hit it.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: d0f6ced17fb04b6a0cbeb32e5950a3df8b3c4b5d
      
https://github.com/qemu/qemu/commit/d0f6ced17fb04b6a0cbeb32e5950a3df8b3c4b5d
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/helper.h

  Log Message:
  -----------
  ppc: Improve flags for helpers loading/writing the time facilities

Those helpers never load from or store to the TCG tracked environment,
not do they generate synchronous exceptions (they might generate an
asynchronous interrupt but that's not an issue here).

So we can make them all use TCG_CALL_NO_RWG

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 76a3d2f750476e77a3287937bf4189e527514dc1
      
https://github.com/qemu/qemu/commit/76a3d2f750476e77a3287937bf4189e527514dc1
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/helper.h

  Log Message:
  -----------
  ppc: Improve the exception helpers flags

They generate exceptions, but they don't update the environment

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a007b19b37d571a01bc8a4458537345402eb01c0
      
https://github.com/qemu/qemu/commit/a007b19b37d571a01bc8a4458537345402eb01c0
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M target-ppc/helper.h

  Log Message:
  -----------
  ppc: Improve a few more helper flags

Mostly turn "store" type of helpers into TCG_CALL_NO_WG because
they can take exceptions. Also fixup_thrm doesn't read nor write
the tracked environment.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 32f5f50dade3def9e51fdff505f79c67809fe647
      
https://github.com/qemu/qemu/commit/32f5f50dade3def9e51fdff505f79c67809fe647
  Author: Laurent Vivier <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M hw/net/spapr_llan.c

  Log Message:
  -----------
  spapr: implement H_CHANGE_LOGICAL_LAN_MAC h_call

Since kernel v4.0, linux uses H_CHANGE_LOGICAL_LAN_MAC to change lively
the MAC address of an ibmveth interface.

As QEMU doesn't implement this h_call, we can't change anymore the
MAC address of an spapr-vlan interface.

Signed-off-by: Laurent Vivier <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 29531542bc92603a198d50412e1142b9f0fb0a73
      
https://github.com/qemu/qemu/commit/29531542bc92603a198d50412e1142b9f0fb0a73
  Author: Thomas Huth <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M tests/Makefile.include

  Log Message:
  -----------
  tests: Resort check-qtest entries in Makefile.include

The rather random list of check-qtest-xxx entries caused some
confusion in the past, where to use "=" and where to use "+="
(see commits 0ccac16f59462b8e2b9afbc1 and 1f5c1cfbaec0792cd2e5da
for example).
Sorting the check-qtest-xxx entries by architecure instead and
using some empty lines inbetween should help to ease this
situation a little bit, so that it is hopefully now obvious
that new tests should be added with "+=" instead of "=".
While we are at it, this patch also comments out two of the
"gcov-files-..." lines since the corresponding m48t59-test is
disabled for sparc and sparc64, too.

Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: d2ab58ffc927c00e88f53f9b853b015a76fa1bd2
      
https://github.com/qemu/qemu/commit/d2ab58ffc927c00e88f53f9b853b015a76fa1bd2
  Author: Thomas Huth <address@hidden>
  Date:   2016-09-07 (Wed, 07 Sep 2016)

  Changed paths:
    M tests/Makefile.include
    A tests/boot-serial-test.c

  Log Message:
  -----------
  tests: Check serial output of firmware boot of some machines

Some of the machines that we have got a firmware image for write
some output to the serial console while booting up. We can use
this output to make sure that the machine is basically working,
so this adds a test that checks the output of these machines
for some well-known "magic" strings.

Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 59351d9b40b1de0fb77e1ff3e53faa04c995c707
      
https://github.com/qemu/qemu/commit/59351d9b40b1de0fb77e1ff3e53faa04c995c707
  Author: Peter Maydell <address@hidden>
  Date:   2016-09-08 (Thu, 08 Sep 2016)

  Changed paths:
    M hw/intc/xics_kvm.c
    M hw/misc/macio/macio.c
    M hw/net/spapr_llan.c
    M hw/ppc/Makefile.objs
    A hw/ppc/fdt.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_drc.c
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_iommu.c
    M hw/ppc/spapr_rtas.c
    M hw/ppc/spapr_vio.c
    A include/hw/ppc/fdt.h
    M linux-user/main.c
    M target-ppc/cpu-models.c
    M target-ppc/cpu-models.h
    M target-ppc/cpu-qom.h
    M target-ppc/cpu.h
    M target-ppc/dfp_helper.c
    M target-ppc/excp_helper.c
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/mem_helper.c
    M target-ppc/misc_helper.c
    M target-ppc/mmu-hash64.c
    M target-ppc/mmu_helper.c
    M target-ppc/timebase_helper.c
    M target-ppc/translate.c
    A target-ppc/translate/dfp-impl.inc.c
    A target-ppc/translate/dfp-ops.inc.c
    A target-ppc/translate/fp-impl.inc.c
    A target-ppc/translate/fp-ops.inc.c
    A target-ppc/translate/spe-impl.inc.c
    A target-ppc/translate/spe-ops.inc.c
    A target-ppc/translate/vmx-impl.inc.c
    A target-ppc/translate/vmx-ops.inc.c
    A target-ppc/translate/vsx-impl.inc.c
    A target-ppc/translate/vsx-ops.inc.c
    M target-ppc/translate_init.c
    M tests/Makefile.include
    A tests/boot-serial-test.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.8-20160907' into 
staging

ppc patch queue for 2016-Sep-7

This is my first pull request for the newly opened qemu-2.8 tree.  It
contains a heap of things that were too late for 2.7 and have been
queued for a while.  In particular:
    * A number of preliminary patches for the powernv machine type
  * A substantial cleanup of exception handling which will be
    necessary to support running a TCG with hypervisor
    facilities
    * A start on support for POWER9
  * Some TCG implementations for new POWER9 instructions
  * Some TCG and related cleanups in preparation for POWER9
    * Some assorted TCG optimizations
    * An implementation of the H_CHANGE_LOGICAL_LAN_MAC hypercall
      which allows the MAC address to be changed on the PAPR virtual
      NIC.
    * Add some extra test cases for several machines (this isn't
      strictly in the ppc code, but is most value to ppc)

NOTE: This pull request supersedes ppc-for-2.8-20160906, which had
some problems.  Changes:
  * Dropped BenH's lmw/stmw speedups, which break for
    qemu-system-ppc64 on BE hosts
  * A small fix to Thomas' serial output test to avoid a warning on
    the isapc machine type.
  * Some trivial checkpatch fixes

Note that some of the patches in this series still have large numbers
of checkpatch warnings.  This is because they're moving existing code
that predates most of the checkpatch style conventions.

# gpg: Signature made Wed 07 Sep 2016 07:09:27 BST
# gpg:                using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>"
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg:                 aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.8-20160907: (64 commits)
  tests: Check serial output of firmware boot of some machines
  tests: Resort check-qtest entries in Makefile.include
  spapr: implement H_CHANGE_LOGICAL_LAN_MAC h_call
  ppc: Improve a few more helper flags
  ppc: Improve the exception helpers flags
  ppc: Improve flags for helpers loading/writing the time facilities
  ppc: Don't generate dead code on unconditional branches
  ppc: Stop dumping state on all exceptions in linux-user
  ppc: Fix catching some segfaults in user mode
  ppc: Fix macio ESCC legacy mapping
  hw/ppc: add a ppc_create_page_sizes_prop() helper routine
  hw/ppc: use error_report instead of fprintf
  ppc: Rename #include'd .c files to .inc.c
  target-ppc: add extswsli[.] instruction
  target-ppc: add vsrv instruction
  target-ppc: add vslv instruction
  target-ppc: add vcmpnez[b,h,w][.] instructions
  target-ppc: add vabsdu[b,h,w] instructions
  target-ppc: add dtstsfi[q] instructions
  target-ppc: implement branch-less divd[o][.]
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/0813cbf913b0...59351d9b40b1
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