[Qemu-commits] [qemu/qemu] c2da8a: ast2400: add a memory controller device model

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: c2da8a8b90faf0b77417e08fa942af1ff0f7cdc3
      
https://github.com/qemu/qemu/commit/c2da8a8b90faf0b77417e08fa942af1ff0f7cdc3
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-09-06 (Tue, 06 Sep 2016)

  Changed paths:
    M hw/arm/ast2400.c
    M hw/misc/Makefile.objs
    A hw/misc/aspeed_sdmc.c
    M include/hw/arm/ast2400.h
    A include/hw/misc/aspeed_sdmc.h

  Log Message:
  -----------
  ast2400: add a memory controller device model

The uboot in the previous release of the SDK was using a hardcoded
value for memory size. This is not true anymore, the value is now
retrieved from the memory controller.

Below is a model for this device, only supporting unlock and
configuration. Without it, we endup running a guest with 64MB, which
is a bit low nowdays. It uses a 'silicon-rev' property and ram_size to
build a default value. Some bits should be linked to SCU strapping
registers but it seems a bit complex to add for the current need.

The model is ready for the AST2500 SOC.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e0fe723c24562c8f909bb40f131bfdbe75650677
      
https://github.com/qemu/qemu/commit/e0fe723c24562c8f909bb40f131bfdbe75650677
  Author: Sergey Sorokin <address@hidden>
  Date:   2016-09-06 (Tue, 06 Sep 2016)

  Changed paths:
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Fix lpae bit in FSR on an alignment fault

If an alignment fault occurred and target EL is using AArch32,
then DFSR/IFSR bit LPAE[9] must be set correctly.

Signed-off-by: Sergey Sorokin <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f460be435f8750d5d1484d3d8b9e5b2c334f0e20
      
https://github.com/qemu/qemu/commit/f460be435f8750d5d1484d3d8b9e5b2c334f0e20
  Author: Wei Huang <address@hidden>
  Date:   2016-09-06 (Tue, 06 Sep 2016)

  Changed paths:
    M hw/arm/virt-acpi-build.c

  Log Message:
  -----------
  ARM: ACPI: fix the AML ID format for CPU devices

Current QEMU will stall guest VM booting under ACPI mode when vcpu count
is >= 12. Analyzing the booting log, it turns out that DSDT table can't
be loaded correctly due to "Invalid character(s) in name (0x62303043),
repaired: [C00*]". This is because existing QEMU uses a lower case AML
ID for CPU devices (e.g. C000, C001, ..., C00a, C00b). The ACPI code
inside guest VM detects this lower case character as an invalid character
(see acpi_ut_valid_acpi_char() in drivers/acpi/acpica/utstring.c file)
and converts it to "*". This causes duplicated IDs (i.e. "C00a" ==>"C00*"
and "C00b" ==> "C00*"). So ACPI refuses to load the table.

This patch fixes the problem by changing the format with a upper case
character. It matches the CPU ID formats used in other parts of QEMU
code.

Reported-by: Eric Auger <address@hidden>
Signed-off-by: Wei Huang <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Tested-by: Eric Auger <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c827c06a4dd6c768eeb3aaa6af6cfd29663116af
      
https://github.com/qemu/qemu/commit/c827c06a4dd6c768eeb3aaa6af6cfd29663116af
  Author: Marcin Krzeminski <address@hidden>
  Date:   2016-09-06 (Tue, 06 Sep 2016)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  block: m25p80: Fix vmstate structure name

Correct bad name of the vmstate structure. Since this breaks
compatibility also update vmstate version back to 0 and make
all fields independent of the VMState version.

Signed-off-by: Marcin Krzeminski <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7faae0b36e51ffdb17d4716ddc40dcfa682d93d9
      
https://github.com/qemu/qemu/commit/7faae0b36e51ffdb17d4716ddc40dcfa682d93d9
  Author: Peter Maydell <address@hidden>
  Date:   2016-09-06 (Tue, 06 Sep 2016)

  Changed paths:
    M hw/arm/ast2400.c
    M hw/arm/virt-acpi-build.c
    M hw/block/m25p80.c
    M hw/misc/Makefile.objs
    A hw/misc/aspeed_sdmc.c
    M include/hw/arm/ast2400.h
    A include/hw/misc/aspeed_sdmc.h
    M target-arm/op_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20160906-1' into staging

target-arm queue:
 * fix incorrect LPAE bit in FSR for alignment faults
 * ACPI: fix the AML ID format for CPU devices to work for
   large numbers of CPUs
 * ast2400: add memory controller device model
 * m25p80: fix the vmstate structure name (migration break)

# gpg: Signature made Tue 06 Sep 2016 20:02:28 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20160906-1:
  block: m25p80: Fix vmstate structure name
  ARM: ACPI: fix the AML ID format for CPU devices
  target-arm: Fix lpae bit in FSR on an alignment fault
  ast2400: add a memory controller device model

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/2926375cffce...7faae0b36e51