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[Qemu-commits] [qemu/qemu] 405140: hw/mips: implement GIC Interval Timer

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 405140: hw/mips: implement GIC Interval Timer
Date: Tue, 12 Jul 2016 05:30:03 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 405140519f58815b422db086b7461d6c00b79b57
      
https://github.com/qemu/qemu/commit/405140519f58815b422db086b7461d6c00b79b57
  Author: Yongbok Kim <address@hidden>
  Date:   2016-07-12 (Tue, 12 Jul 2016)

  Changed paths:
    M hw/timer/Makefile.objs
    A hw/timer/mips_gictimer.c
    A include/hw/timer/mips_gictimer.h

  Log Message:
  -----------
  hw/mips: implement GIC Interval Timer

The interval timer is similar to the CP0 Count/Compare timer within
each processor. The difference is the GIC_SH_COUNTER register is global
to the system so that all processors have the same time reference.

To ease implementation, all VPs are having its own QEMU timer but sharing
global settings and registers such as GIC_SH_CONFIG.COUTNSTOP and
GIC_SH_COUNTER.

MIPS GIC Interval Timer does support upto 64 bits of Count register but
in this implementation it is limited to 32 bits only.

Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: e8bd336dd1af6d1073e9411bd1c47b045988b30a
      
https://github.com/qemu/qemu/commit/e8bd336dd1af6d1073e9411bd1c47b045988b30a
  Author: Yongbok Kim <address@hidden>
  Date:   2016-07-12 (Tue, 12 Jul 2016)

  Changed paths:
    M hw/intc/Makefile.objs
    A hw/intc/mips_gic.c
    A include/hw/intc/mips_gic.h

  Log Message:
  -----------
  hw/mips: implement Global Interrupt Controller

The Global Interrupt Controller (GIC) is responsible for mapping each
internal and external interrupt to the correct location for servicing.

The internal representation of registers is different from the specification
in order to consolidate information for each GIC Interrupt Sources and Virtual
Processors with same functionalities. For example SH_MAP00_VP00 registers are
defined like each bit represents a VP but in this implementation the equivalent
map_vp contains VP number in integer form for ease accesses. When it is being
accessed via read write functions an internal data is converted back into the
original format as the specification.

Limitations:
Level triggering only
GIC CounterHi not implemented (Countbits = 32bits)
DINT not implemented
Local WatchDog, Fast Debug Channel, Perf Counter not implemented

Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 19494f811a43c6bc226aa272d86300d9229224fe
      
https://github.com/qemu/qemu/commit/19494f811a43c6bc226aa272d86300d9229224fe
  Author: Leon Alrae <address@hidden>
  Date:   2016-07-12 (Tue, 12 Jul 2016)

  Changed paths:
    M hw/mips/cps.c
    M hw/mips/mips_malta.c
    M hw/misc/mips_cmgcr.c
    M include/hw/mips/cps.h
    M include/hw/misc/mips_cmgcr.h

  Log Message:
  -----------
  hw/mips/cps: create GIC block inside CPS

Add GIC to CPS and expose its interrupt pins instead of CPU's.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 89777fd10fc3dd573c3b4d1b2efdd10af823c001
      
https://github.com/qemu/qemu/commit/89777fd10fc3dd573c3b4d1b2efdd10af823c001
  Author: Leon Alrae <address@hidden>
  Date:   2016-07-12 (Tue, 12 Jul 2016)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add exception base to MIPS CPU

Replace hardcoded 0xbfc00000 with exception_base which is initialized with
this default address so there is no functional change here.
However, it is now exposed and consequently it will be possible to modify
it from outside of the CPU.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: dff94251f02708d2ef9aee5149abd69f039e4a13
      
https://github.com/qemu/qemu/commit/dff94251f02708d2ef9aee5149abd69f039e4a13
  Author: Leon Alrae <address@hidden>
  Date:   2016-07-12 (Tue, 12 Jul 2016)

  Changed paths:
    M hw/misc/mips_cpc.c

  Log Message:
  -----------
  hw/mips_cpc: make VP correctly start from the reset vector

When VP enters the Run state it starts execution from the reset vector.
Currently used CPU_INTERRUPT_WAKE does not do that if reset exception
base has been modified. Therefore fix that by simply resetting given VP.

Drop the usage of CPU_INTERRUPT_WAKE also in VP_STOP and instead raise
the CPU_INTERRUPT_HALT to halt a VP.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: c09199fe73f382b66293a1f571b8cbaaed023629
      
https://github.com/qemu/qemu/commit/c09199fe73f382b66293a1f571b8cbaaed023629
  Author: Leon Alrae <address@hidden>
  Date:   2016-07-12 (Tue, 12 Jul 2016)

  Changed paths:
    M hw/misc/mips_cmgcr.c
    M include/hw/misc/mips_cmgcr.h

  Log Message:
  -----------
  hw/mips_cmgcr: implement RESET_BASE register in CM GCR

Implement RESET_BASE register which is local to each VP and a write to
it changes VP's reset exception base. Also, add OTHER register to
allow a software running on one VP to access other VP's local registers.

Guest can use this mechanism to specify custom address from which a VP
will start execution.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 8f95ad1c79b4166350b982a6defe0e21faa04dac
      
https://github.com/qemu/qemu/commit/8f95ad1c79b4166350b982a6defe0e21faa04dac
  Author: Leon Alrae <address@hidden>
  Date:   2016-07-12 (Tue, 12 Jul 2016)

  Changed paths:
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: replace MIPS64R6-generic with the real I6400 CPU model

MIPS64R6-generic gradually gets closer to I6400 CPU, feature-wise. Rename
it to make it clear which MIPS processor it is supposed to emulate.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 6ec98bd7b64ad75870c8e9d87a90fcd1a64b4942
      
https://github.com/qemu/qemu/commit/6ec98bd7b64ad75870c8e9d87a90fcd1a64b4942
  Author: Paul Burton <address@hidden>
  Date:   2016-07-12 (Tue, 12 Jul 2016)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/helper.c
    M target-mips/op_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add ASID mask field and replace magic values

Signed-off-by: Paul Burton <address@hidden>
Signed-off-by: James Hogan <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 2d72e7b047d800c9f99262466f65a98684ecca14
      
https://github.com/qemu/qemu/commit/2d72e7b047d800c9f99262466f65a98684ecca14
  Author: Paul Burton <address@hidden>
  Date:   2016-07-12 (Tue, 12 Jul 2016)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/helper.c
    M target-mips/machine.c
    M target-mips/op_helper.c

  Log Message:
  -----------
  target-mips: change ASID type to hold more than 8 bits

ASID currently has uint8_t type which is too small since some processors
support more than 8 bits ASID. Therefore change its type to uint16_t.

Signed-off-by: Paul Burton <address@hidden>
Signed-off-by: James Hogan <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: a0c8060841f2d56fb3504292c18522b957972e4c
      
https://github.com/qemu/qemu/commit/a0c8060841f2d56fb3504292c18522b957972e4c
  Author: Paul Burton <address@hidden>
  Date:   2016-07-12 (Tue, 12 Jul 2016)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: support CP0.Config4.AE bit

The read-only Config4.AE bit set denotes extended 10 bits ASID.

Signed-off-by: Paul Burton <address@hidden>
Signed-off-by: James Hogan <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: cdc46fab07a122dfcc8a1054510a68d936ae3440
      
https://github.com/qemu/qemu/commit/cdc46fab07a122dfcc8a1054510a68d936ae3440
  Author: Leon Alrae <address@hidden>
  Date:   2016-07-12 (Tue, 12 Jul 2016)

  Changed paths:
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: enable 10-bit ASIDs in I6400 CPU

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 74e1b782b34e280b06a90f61fdbac5a046cbe491
      
https://github.com/qemu/qemu/commit/74e1b782b34e280b06a90f61fdbac5a046cbe491
  Author: Peter Maydell <address@hidden>
  Date:   2016-07-12 (Tue, 12 Jul 2016)

  Changed paths:
    M hw/intc/Makefile.objs
    A hw/intc/mips_gic.c
    M hw/mips/cps.c
    M hw/mips/mips_malta.c
    M hw/misc/mips_cmgcr.c
    M hw/misc/mips_cpc.c
    M hw/timer/Makefile.objs
    A hw/timer/mips_gictimer.c
    A include/hw/intc/mips_gic.h
    M include/hw/mips/cps.h
    M include/hw/misc/mips_cmgcr.h
    A include/hw/timer/mips_gictimer.h
    M target-mips/cpu.h
    M target-mips/helper.c
    M target-mips/machine.c
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160712' into staging

MIPS patches 2016-07-12

Changes:
* support 10-bit ASIDs
* MIPS64R6-generic renamed to I6400
* initial GIC support
* implement RESET_BASE register in CM GCR

# gpg: Signature made Tue 12 Jul 2016 11:49:50 BST
# gpg:                using RSA key 0x52118E3C0B29DA6B
# gpg: Good signature from "Leon Alrae <address@hidden>"
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4  4FC0 5211 8E3C 0B29 DA6B

* remotes/lalrae/tags/mips-20160712:
  target-mips: enable 10-bit ASIDs in I6400 CPU
  target-mips: support CP0.Config4.AE bit
  target-mips: change ASID type to hold more than 8 bits
  target-mips: add ASID mask field and replace magic values
  target-mips: replace MIPS64R6-generic with the real I6400 CPU model
  hw/mips_cmgcr: implement RESET_BASE register in CM GCR
  hw/mips_cpc: make VP correctly start from the reset vector
  target-mips: add exception base to MIPS CPU
  hw/mips/cps: create GIC block inside CPS
  hw/mips: implement Global Interrupt Controller
  hw/mips: implement GIC Interval Timer

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/c1ac514a0444...74e1b782b34e
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