[Qemu-commits] [qemu/qemu] d31709: linux-user: Make semihosting heap/stack fields abi...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: d317091d5ed616328ef5a7b8502167c4e7de8e6b
      
https://github.com/qemu/qemu/commit/d317091d5ed616328ef5a7b8502167c4e7de8e6b
  Author: Peter Maydell <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M linux-user/qemu.h

  Log Message:
  -----------
  linux-user: Make semihosting heap/stack fields abi_ulongs

The fields in the TaskState heap_base, heap_limit and stack_base
are all guest addresses (representing the locations of the heap
and stack for the guest binary), so they should be abi_ulong
rather than uint32_t. (This only in practice affects ARM AArch64
since all the other semihosting implementations are 32-bit.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden


  Commit: f5666418c449b49917ea24cdb0bed76a602a3c74
      
https://github.com/qemu/qemu/commit/f5666418c449b49917ea24cdb0bed76a602a3c74
  Author: Peter Maydell <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M target-arm/arm-semi.c

  Log Message:
  -----------
  target-arm/arm-semi.c: Fix SYS_HEAPINFO for 64-bit guests

SYS_HEAPINFO is one of the few semihosting calls which has to write
values back into a parameter block in memory.  When we added
support for 64-bit semihosting we updated the code which reads from
the parameter block to read 64-bit words but forgot to change the
code that writes back into the block. Update it to treat the
block as a set of words of the appropriate width for the guest.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: a1777f7f6462c66e1ee6e98f0d5c431bfe988aa5
      
https://github.com/qemu/qemu/commit/a1777f7f6462c66e1ee6e98f0d5c431bfe988aa5
  Author: Peter Maydell <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M docs/memory.txt
    M include/exec/memory.h
    M memory.c

  Log Message:
  -----------
  memory: Provide memory_region_init_rom()

Provide a new helper function memory_region_init_rom() for memory
regions which are read-only (and unlike those created by
memory_region_init_rom_device() don't have special behaviour
for writes). This has the same behaviour as calling
memory_region_init_ram() and then memory_region_set_readonly()
(which is what we do today in boards with pure ROMs) but is a
more easily discoverable API for the purpose.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: a7aeb5f7b2c713e2ab7e0a142e0c89f7b2aa5bb7
      
https://github.com/qemu/qemu/commit/a7aeb5f7b2c713e2ab7e0a142e0c89f7b2aa5bb7
  Author: Peter Maydell <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M hw/arm/fsl-imx25.c
    M hw/arm/fsl-imx31.c
    M hw/arm/fsl-imx6.c

  Log Message:
  -----------
  imx: Use memory_region_init_rom() for ROMs

The imx boards were all incorrectly creating ROMs using
memory_region_init_rom_device() with a NULL ops pointer. This
will cause QEMU to abort if the guest tries to write to the
ROM. Switch to the new memory_region_init_rom() instead.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 39e0b03dec518254fabd2acff29548d3f1d2b754
      
https://github.com/qemu/qemu/commit/39e0b03dec518254fabd2acff29548d3f1d2b754
  Author: Peter Maydell <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M include/exec/memory.h
    M memory.c

  Log Message:
  -----------
  memory: Assert that memory_region_init_rom_device() ops aren't NULL

It doesn't make sense to pass a NULL ops argument to
memory_region_init_rom_device(), because the effect will
be that if the guest tries to write to the memory region
then QEMU will segfault. Catch the bug earlier by sanity
checking the arguments to this function, and remove the
misleading documentation that suggests that passing NULL
might be sensible.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: a19861666b574f54c71d1fea9a8d8a84915dfa70
      
https://github.com/qemu/qemu/commit/a19861666b574f54c71d1fea9a8d8a84915dfa70
  Author: Andrey Smirnov <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  armv7m_nvic: Use qemu_get_cpu(0) instead of current_cpu

Starting QEMU with -S results in current_cpu containing its initial
value of NULL. It is however possible to connect to such QEMU instance
and query various CPU registers, one example being CPUID, and doing that
results in QEMU segfaulting.

Using qemu_get_cpu(0) seem reasonable enough given that ARMv7M
architecture is a single core architecture.

Signed-off-by: Andrey Smirnov <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5d636e21c44ecf982a22a7bc4ca89186079ac283
      
https://github.com/qemu/qemu/commit/5d636e21c44ecf982a22a7bc4ca89186079ac283
  Author: Ard Biesheuvel <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: mark the PCIe host controller as DMA coherent in the DT

Since QEMU performs cacheable accesses to guest memory when doing DMA
as part of the implementation of emulated PCI devices, guest drivers
should use cacheable accesses as well when running under KVM. Since this
essentially means that emulated PCI devices are DMA coherent, set the
'dma-coherent' DT property on the PCIe host controller DT node.

This brings the DT description into line with the ACPI description,
which already marks the PCI bridge as cache coherent (see commit
bc64b96c984abf).

Signed-off-by: Ard Biesheuvel <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ae2923b5c20a21c6457680330506a9c13873485c
      
https://github.com/qemu/qemu/commit/ae2923b5c20a21c6457680330506a9c13873485c
  Author: Alistair Francis <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M include/qemu/bitops.h

  Log Message:
  -----------
  bitops: Add MAKE_64BIT_MASK macro

Add a macro that creates a 64bit value which has length number of ones
shifted across by the value of shift.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1599121b57d9bcfff868ad589bb87cf6e0e2c4ac
      
https://github.com/qemu/qemu/commit/1599121b57d9bcfff868ad589bb87cf6e0e2c4ac
  Author: Alistair Francis <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M hw/core/Makefile.objs
    A hw/core/register.c
    A include/hw/register.h

  Log Message:
  -----------
  register: Add Register API

This API provides some encapsulation of registers and factors out some
common functionality to common code. Bits of device state (usually MMIO
registers) often have all sorts of access restrictions and semantics
associated with them. This API allows you to define what those
restrictions are on a bit-by-bit basis.

Helper functions are then used to access the register which observe the
semantics defined by the RegisterAccessInfo struct.

Some features:
Bits can be marked as read_only (ro field)
Bits can be marked as write-1-clear (w1c field)
Bits can be marked as reserved (rsvd field)
Reset values can be defined (reset)
Bits can be marked clear on read (cor)
Pre and post action callbacks can be added to read and write ops
Verbose debugging info can be enabled/disabled

Useful for defining device register spaces in a data driven way. Cuts
down on a lot of the verbosity and repetition in the switch-case blocks
in the standard foo_mmio_read/write functions.

Also useful for automated generation of device models from hardware
design sources.

Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0b73c9bb066c6b66a9466ad9c3bbfd841477bf50
      
https://github.com/qemu/qemu/commit/0b73c9bb066c6b66a9466ad9c3bbfd841477bf50
  Author: Alistair Francis <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M hw/core/register.c
    M include/hw/register.h

  Log Message:
  -----------
  register: Add Memory API glue

Add memory io handlers that glue the register API to the memory API.
Just translation functions at this stage. Although it does allow for
devices to be created without all-in-one mmio r/w handlers.

This patch also adds the RegisterInfoArray struct, which allows all of
the individual RegisterInfo structs to be grouped into a single memory
region.

Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 684204593d9b81ba4cd4c441b5ee395a29cff606
      
https://github.com/qemu/qemu/commit/684204593d9b81ba4cd4c441b5ee395a29cff606
  Author: Peter Crosthwaite <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M include/hw/register.h

  Log Message:
  -----------
  register: Define REG and FIELD macros

Define some macros that can be used for defining registers and fields.

The REG32 macro will define A_FOO, for the byte address of a register
as well as R_FOO for the uint32_t[] register number (A_FOO / 4).

The FIELD macro will define FOO_BAR_MASK, FOO_BAR_SHIFT and
FOO_BAR_LENGTH constants for field BAR in register FOO.

Finally, there are some shorthand helpers for extracting/depositing
fields from registers based on these naming schemes.

Usage can greatly reduce the verbosity of device code.

The deposit and extract macros (eg FIELD_EX32, FIELD_DP32  etc.) can be
used to generate extract and deposits without any repetition of the name
stems.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
[ EI Changes:
  * Add Deposit macros
]
Signed-off-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 49e14ddbcef3477c9c47900ef132a92d1ca4180c
      
https://github.com/qemu/qemu/commit/49e14ddbcef3477c9c47900ef132a92d1ca4180c
  Author: Peter Crosthwaite <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M hw/core/register.c
    M include/hw/register.h

  Log Message:
  -----------
  register: QOMify

QOMify registers as a child of TYPE_DEVICE. This allows registers to
define GPIOs.

Define an init helper that will do QOM initialisation.

Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: KONRAD Frederic <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a74229597e2c226a1a1f46a8926a0d2ec9c7574e
      
https://github.com/qemu/qemu/commit/a74229597e2c226a1a1f46a8926a0d2ec9c7574e
  Author: Peter Crosthwaite <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M hw/core/register.c
    M include/hw/register.h

  Log Message:
  -----------
  register: Add block initialise helper

Add a helper that will scan a static RegisterAccessInfo Array
and populate a container MemoryRegion with registers as defined.

Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 034c2e69023007ac855a86ab5d91591f70506a62
      
https://github.com/qemu/qemu/commit/034c2e69023007ac855a86ab5d91591f70506a62
  Author: Alistair Francis <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/dma/Makefile.objs
    A hw/dma/xlnx-zynq-devcfg.c
    A include/hw/dma/xlnx-zynq-devcfg.h

  Log Message:
  -----------
  dma: Add Xilinx Zynq devcfg device model

Add a minimal model for the devcfg device which is part of Zynq.
This model supports DMA capabilities and interrupt generation.

Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f4b99537f1caac9864e3e93ac5a980e5d62ece0f
      
https://github.com/qemu/qemu/commit/f4b99537f1caac9864e3e93ac5a980e5d62ece0f
  Author: Peter Crosthwaite <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M hw/arm/xilinx_zynq.c

  Log Message:
  -----------
  xilinx_zynq: Connect devcfg to the Zynq machine model

Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7673bb4cd305637b37bd0c0b79dd3bf6deb55172
      
https://github.com/qemu/qemu/commit/7673bb4cd305637b37bd0c0b79dd3bf6deb55172
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M hw/arm/spitz.c
    M hw/arm/tosa.c
    M hw/arm/z2.c
    M hw/block/m25p80.c
    M hw/display/ads7846.c
    M hw/display/ssd0323.c
    M hw/misc/max111x.c
    M hw/sd/ssi-sd.c
    M hw/ssi/ssi.c
    M include/hw/ssi/ssi.h

  Log Message:
  -----------
  ssi: change ssi_slave_init to be a realize ops

This enables qemu to handle late inits and report errors. All the SSI
slave routine names were changed accordingly. Code was modified to
handle errors when possible (m25p80 and ssi-sd)

Tested with the m25p80 slave object.

Suggested-by: Paolo Bonzini <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: cace7b801d49430522840fa13e9ac2bdc2dcf941
      
https://github.com/qemu/qemu/commit/cace7b801d49430522840fa13e9ac2bdc2dcf941
  Author: Paolo Bonzini <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  m25p80: do not put iovec on the stack

When doing a read-modify-write cycle, QEMU uses the iovec after returning
from blk_aio_pwritev.  m25p80 puts the iovec on the stack of blk_aio_pwritev's
caller, which causes trouble in this case.  This has been a problem
since commit 243e6f6 ("m25p80: Switch to byte-based block access",
2016-05-12) started doing writes at a smaller granularity than 512 bytes.
In principle however it could have broken before when using -drive
if=mtd,cache=none on a disk with 4K native sectors.

Signed-off-by: Paolo Bonzini <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Eric Blake <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b68cb06093a36bd6fbd4d06cd62c08629fea2242
      
https://github.com/qemu/qemu/commit/b68cb06093a36bd6fbd4d06cd62c08629fea2242
  Author: Paolo Bonzini <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  m25p80: avoid out of bounds accesses

s->cur_addr can be made to point outside s->storage, either by
writing a value >= 128 to s->ear (because s->ear * MAX_3BYTES_SIZE
is a signed integer and sign-extends into the 64-bit cur_addr),
or just by writing an address beyond the size of the flash being
emulated.  Avoid the sign extension to make the code cleaner, and
on top of that mask s->cur_addr to s->size.

Signed-off-by: Paolo Bonzini <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Reviewed by: Marcin Krzeminski <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b7f480c3f69edc74dd8e2ecfc51c9e35590965de
      
https://github.com/qemu/qemu/commit/b7f480c3f69edc74dd8e2ecfc51c9e35590965de
  Author: Paolo Bonzini <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  m25p80: change cur_addr to 32 bit integer

The maximum amount of storage that can be addressed by the m25p80 command
set is 4 GiB.  However, cur_addr is currently a 64-bit integer.  To avoid
further problems related to sign extension of signed 32-bit integer
expressions, change cur_addr to a 32 bit integer.  Preserve migration
format by adding a dummy 4-byte field in place of the (big-endian)
high four bytes in the formerly 64-bit cur_addr field.

Signed-off-by: Paolo Bonzini <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 73bce5187ba93b34944aab08d1da5712c1183a68
      
https://github.com/qemu/qemu/commit/73bce5187ba93b34944aab08d1da5712c1183a68
  Author: Paolo Bonzini <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M hw/arm/sabrelite.c
    M hw/arm/xilinx_zynq.c
    M hw/arm/xlnx-ep108.c
    M hw/block/m25p80.c
    M hw/microblaze/petalogix_ml605_mmu.c

  Log Message:
  -----------
  m25p80: qdev-ify drive property

This allows specifying the property via -drive if=none and creating
the flash device with -device.

Signed-off-by: Paolo Bonzini <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
[clg: added an extra fix for sabrelite_init()
      keeping the test on flash_dev did not seem necessary. ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7c1c69bca43c345481b778382e605e1d49a12d56
      
https://github.com/qemu/qemu/commit/7c1c69bca43c345481b778382e605e1d49a12d56
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M hw/arm/ast2400.c
    M hw/ssi/Makefile.objs
    A hw/ssi/aspeed_smc.c
    M include/hw/arm/ast2400.h
    A include/hw/ssi/aspeed_smc.h

  Log Message:
  -----------
  ast2400: add SMC controllers (FMC and SPI)

The Aspeed AST2400 soc includes a static memory controller for the BMC
which supports NOR, NAND and SPI flash memory modules. This controller
has two modes : the SMC for the legacy interface which supports only
one module and the FMC for the new interface which supports up to five
modules. The AST2400 also includes a SPI only controller used for the
host firmware, commonly called BIOS on Intel. It can be used in three
mode : a SPI master, SPI slave and SPI pass-through

Below is the initial framework for the SMC controller (FMC mode only)
and the SPI controller: the sysbus object, MMIO for registers
configuration and controls. Each controller has a SPI bus and a
configurable number of CS lines for SPI flash slaves.

The differences between the controllers are small, so they are
abstracted using indirections on the register numbers.

Only SPI flash modules are supported.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: added one missing error_propagate]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 924ed16386ac8e079a9798f7de3b0d933fc3132c
      
https://github.com/qemu/qemu/commit/924ed16386ac8e079a9798f7de3b0d933fc3132c
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M hw/arm/ast2400.c
    M hw/ssi/aspeed_smc.c
    M include/hw/ssi/aspeed_smc.h

  Log Message:
  -----------
  ast2400: add SPI flash slaves

Each controller on the ast2400 has a memory range on which it maps its
flash module slaves. Each slave is assigned a memory segment for its
mapping that can be changed at bootime with the Segment Address
Register. This is not supported in the current implementation so we
are using the defaults provided by the specs.

Each SPI flash slave can then be accessed in two modes: Command and
User. When in User mode, accesses to the memory segment of the slaves
are translated in SPI transfers. When in Command mode, the HW
generates the SPI commands automatically and the memory segment is
accessed as if doing a MMIO. Other SPI controllers call that mode
linear addressing mode.

For this purpose, we are adding below each crontoller an array of
structs gathering for each SPI flash module, a segment rank, a
MemoryRegion to handle the memory accesses and the associated SPI
slave device, which should be a m25p80.

Only the User mode is supported for now but we are preparing ground
for the Command mode. The framework is sufficient to support Linux.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
[PMM: Use g_new0() rather than g_malloc0()]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e1ad9bc405afbd7581831ca1705f39e73c94c5ff
      
https://github.com/qemu/qemu/commit/e1ad9bc405afbd7581831ca1705f39e73c94c5ff
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M hw/arm/palmetto-bmc.c

  Log Message:
  -----------
  ast2400: create SPI flash slaves

A set of SPI flash slaves is attached under the flash controllers of
the palmetto platform. "n25q256a" flash modules are used for the BMC
and "mx25l25635e" for the host. These types are common in the
OpenPower ecosystem.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3173a1fd549b7fa0f7029b2c6a6b86ba6efa92aa
      
https://github.com/qemu/qemu/commit/3173a1fd549b7fa0f7029b2c6a6b86ba6efa92aa
  Author: Peter Maydell <address@hidden>
  Date:   2016-07-04 (Mon, 04 Jul 2016)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M docs/memory.txt
    M hw/arm/ast2400.c
    M hw/arm/fsl-imx25.c
    M hw/arm/fsl-imx31.c
    M hw/arm/fsl-imx6.c
    M hw/arm/palmetto-bmc.c
    M hw/arm/sabrelite.c
    M hw/arm/spitz.c
    M hw/arm/tosa.c
    M hw/arm/virt.c
    M hw/arm/xilinx_zynq.c
    M hw/arm/xlnx-ep108.c
    M hw/arm/z2.c
    M hw/block/m25p80.c
    M hw/core/Makefile.objs
    A hw/core/register.c
    M hw/display/ads7846.c
    M hw/display/ssd0323.c
    M hw/dma/Makefile.objs
    A hw/dma/xlnx-zynq-devcfg.c
    M hw/intc/armv7m_nvic.c
    M hw/microblaze/petalogix_ml605_mmu.c
    M hw/misc/max111x.c
    M hw/sd/ssi-sd.c
    M hw/ssi/Makefile.objs
    A hw/ssi/aspeed_smc.c
    M hw/ssi/ssi.c
    M include/exec/memory.h
    M include/hw/arm/ast2400.h
    A include/hw/dma/xlnx-zynq-devcfg.h
    A include/hw/register.h
    A include/hw/ssi/aspeed_smc.h
    M include/hw/ssi/ssi.h
    M include/qemu/bitops.h
    M linux-user/qemu.h
    M memory.c
    M target-arm/arm-semi.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160704' 
into staging

target-arm queue:
 * fix semihosting SYS_HEAPINFO call for A64 guests
 * fix crash if guest tries to write to ROM on imx boards
 * armv7m_nvic: fix crash for debugger reads from some registers
 * virt: mark PCIe host controller as dma-coherent in the DT
 * add data-driven register API
 * Xilinx Zynq: add devcfg device model
 * m25p80: fix various bugs
 * ast2400: add SMC controllers and SPI flash slaves

# gpg: Signature made Mon 04 Jul 2016 13:17:34 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20160704: (23 commits)
  ast2400: create SPI flash slaves
  ast2400: add SPI flash slaves
  ast2400: add SMC controllers (FMC and SPI)
  m25p80: qdev-ify drive property
  m25p80: change cur_addr to 32 bit integer
  m25p80: avoid out of bounds accesses
  m25p80: do not put iovec on the stack
  ssi: change ssi_slave_init to be a realize ops
  xilinx_zynq: Connect devcfg to the Zynq machine model
  dma: Add Xilinx Zynq devcfg device model
  register: Add block initialise helper
  register: QOMify
  register: Define REG and FIELD macros
  register: Add Memory API glue
  register: Add Register API
  bitops: Add MAKE_64BIT_MASK macro
  hw/arm/virt: mark the PCIe host controller as DMA coherent in the DT
  armv7m_nvic: Use qemu_get_cpu(0) instead of current_cpu
  memory: Assert that memory_region_init_rom_device() ops aren't NULL
  imx: Use memory_region_init_rom() for ROMs
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/9b9611c85d81...3173a1fd549b