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[Qemu-commits] [qemu/qemu] 8eeb33: ppc: Add a bunch of hypervisor SPRs t

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 8eeb33: ppc: Add a bunch of hypervisor SPRs to Book3s
Date: Fri, 01 Jul 2016 06:30:07 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 8eeb330c69bbfa2667a7c60c7765974bf8442aa7
      
https://github.com/qemu/qemu/commit/8eeb330c69bbfa2667a7c60c7765974bf8442aa7
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: Add a bunch of hypervisor SPRs to Book3s

We don't give them a KVM reg number yet as no current KVM version
supports HV mode.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: SPRs AMOR,DAWR,DARWX were already included in commit f401dd32cb8e9]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 88536935c00311781addc980b0be8fe74f9f5706
      
https://github.com/qemu/qemu/commit/88536935c00311781addc980b0be8fe74f9f5706
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M target-ppc/cpu.h

  Log Message:
  -----------
  ppc: Update LPCR definitions

Includes all the bits up to ISA 2.07

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: fixed checkpatch.pl errors ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4b3fc37788fe5a9c6ec0c43863c78604db40cbb3
      
https://github.com/qemu/qemu/commit/4b3fc37788fe5a9c6ec0c43863c78604db40cbb3
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/mmu-hash64.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: Use a helper to filter writes to LPCR

This handles filtering bits based on what is implemented by a
given architecture version. We also use it to copy to LPCR
some of the relevant 970 HID4 bits.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: fixed checkpatch.pl errors ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: d1dbe37c1ee3f14cb64a9ae3c89f637fdd08fca1
      
https://github.com/qemu/qemu/commit/d1dbe37c1ee3f14cb64a9ae3c89f637fdd08fca1
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M target-ppc/excp_helper.c

  Log Message:
  -----------
  ppc: Fix conditions for delivering external interrupts to a guest

External interrupts can bypass the MSR_EE test if they occur in guest
mode and LPES0 is clear. In that case they are directed to the hypervisor

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b378bb0948277d71c78bc6d0c1ef80a253aafc80
      
https://github.com/qemu/qemu/commit/b378bb0948277d71c78bc6d0c1ef80a253aafc80
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M target-ppc/helper_regs.h

  Log Message:
  -----------
  ppc: Enforce setting MSR:EE,IR and DR when MSR:PR is set

The architecture specifies that any instruction that sets MSR:PR will also
set MSR:EE, IR and DR.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4b236b621bf090509c4a0be372edfd31d13b289a
      
https://github.com/qemu/qemu/commit/4b236b621bf090509c4a0be372edfd31d13b289a
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M hw/ppc/ppc.c
    M target-ppc/excp_helper.c
    M target-ppc/helper.h
    M target-ppc/timebase_helper.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: Initial HDEC support

The current behaviour isn't completely right, as for the DEC, we
don't properly re-arm when wrapping around, but I will fix this
in a separate patch.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: fixed checkpatch.pl errors ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 635dff20a3c5fbf6726954dd2892e5b476ca7494
      
https://github.com/qemu/qemu/commit/635dff20a3c5fbf6726954dd2892e5b476ca7494
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: LPCR is a HV resource

Don't allow access in guest mode

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f2b70fded9b32c4b9e45e5b7f11bfc2ef961ede7
      
https://github.com/qemu/qemu/commit/f2b70fded9b32c4b9e45e5b7f11bfc2ef961ede7
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Print HSRR0/HSRR1 in "info registers"

They are generally useful when debugging HV mode stuff

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: fixed checkpatch.pl errors ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 6cc09e261b267e5b06c03efdf0c8e7a0d9e59721
      
https://github.com/qemu/qemu/commit/6cc09e261b267e5b06c03efdf0c8e7a0d9e59721
  Author: Thomas Huth <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  hw/ppc/spapr: Add some missing hcall function set strings

Add "hcall-sprg0" (for H_SET_SPRG0), "hcall-copy" (for H_PAGE_INIT)
and "hcall-debug" (for H_LOGICAL_CI_LOAD/STORE) to the property
"ibm,hypertas-functions" to indicate that we support these hypercalls.

Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: dde35bc966ef8c1afb4f4e0f3c0e99fc0f27ca04
      
https://github.com/qemu/qemu/commit/dde35bc966ef8c1afb4f4e0f3c0e99fc0f27ca04
  Author: Greg Kurz <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M hw/ppc/spapr_cpu_core.c

  Log Message:
  -----------
  spapr: fix write-past-end-of-array error in cpu core device init code

This fixes a potential QEMU crash introduced by commit 3b542549661.

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: ff461b8da9d3444bf1c33a9a94edcf88435c4268
      
https://github.com/qemu/qemu/commit/ff461b8da9d3444bf1c33a9a94edcf88435c4268
  Author: Bharata B Rao <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M hw/ppc/spapr_cpu_core.c

  Log Message:
  -----------
  spapr: Restore support for older PowerPC CPU cores

Introduction of core based CPU hotplug for PowerPC sPAPR didn't
add support for 970 and POWER5+ based core types. Add support for
the same.

Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a36848ff7ca54d9181ec6c2202ce7563a2c5cfdc
      
https://github.com/qemu/qemu/commit/a36848ff7ca54d9181ec6c2202ce7563a2c5cfdc
  Author: Aaron Larson <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M hw/ppc/e500.c
    M hw/ppc/e500.h
    M hw/ppc/ppce500_spin.c

  Log Message:
  -----------
  target-ppc: Eliminate redundant and incorrect function 
booke206_page_size_to_tlb

Eliminate redundant and incorrect booke206_page_size_to_tlb function
from ppce500_spin.c in preference to previously existing but newly
exported definition from e500.c

Defect analysis:

The booke206_page_size_to_tlb function in e500.c was updated in commit
2bd9543 "ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pages" to
reflect a change in the definition of MAS1_TSIZE_SHIFT from 8
(corresponding to a min TLB page size of 4kb) to a value of 7 (TLB
page size 2k).  The booke206_page_size_to_tlb() function defined in
ppce500_spin.c was never updated to reflect the change in
MAS1_TSIZE_SHIFT.

In http://lists.nongnu.org/archive/html/qemu-ppc/2016-06/msg00533.html,
Scott Wood suggested this "root cause" explanation:

SW> The patch that changed MAS1_TSIZE_SHIFT from 8 to 7 was around the
SW> same time as the patch that added this code, which is probably why
SW> adjusting it got missed.  Commit 2bd9543cd3 did update the
SW> equivalent code in ppce500_mpc8544ds.c, which now resides in
SW> hw/ppc/e500.c and has been changed to not assume a power-of-2
SW> size.  The ppce500_spin version should be eliminated.

Signed-off-by: Aaron Larson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4322e8ced5aaac7191958f09622d199fe61e2d87
      
https://github.com/qemu/qemu/commit/4322e8ced5aaac7191958f09622d199fe61e2d87
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M target-ppc/cpu-qom.h
    M target-ppc/mmu-hash64.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: Fix 64K pages support in full emulation

We were always advertising only 4K & 16M. Additionally the code wasn't
properly matching the page size with the PTE content, which meant we
could potentially hit an incorrect PTE if the guest used multiple sizes.

Finally, honor the CPU capabilities when decoding the size from the SLB
so we don't try to use 64K pages on 970.

This still doesn't add support for MPSS (Multiple Page Sizes per Segment)

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: fixed checkpatch.pl errors
      commits 61a36c9b5a12 and 1114e712c998 reworked the hpte code
      doing insertion/removal in hw/ppc/spapr_hcall.c. The hunks
      modifying these areas were removed. ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 161deaf225e70dee991744cd3164a30726a1b0eb
      
https://github.com/qemu/qemu/commit/161deaf225e70dee991744cd3164a30726a1b0eb
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M hw/intc/xics.c
    M hw/intc/xics_kvm.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_vio.c
    M include/hw/ppc/xics.h

  Log Message:
  -----------
  ppc/xics: Rename existing xics to xics_spapr

The common class doesn't change, the KVM one is sPAPR specific. Rename
variables and functions to xics_spapr.

Retain the type name as "xics" to preserve migration for existing sPAPR
guests.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9c7027ba947d95dedaa760758cc378c8496e0316
      
https://github.com/qemu/qemu/commit/9c7027ba947d95dedaa760758cc378c8496e0316
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M default-configs/ppc64-softmmu.mak
    M hw/intc/Makefile.objs
    M hw/intc/xics.c
    A hw/intc/xics_spapr.c
    M include/hw/ppc/xics.h

  Log Message:
  -----------
  ppc/xics: Move SPAPR specific code to a separate file

Leave the core ICP/ICS logic in xics.c and move the top level
class wrapper, hypercall and RTAS handlers to xics_spapr.c

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[add cpu.h in xics_spapr.c, move set_nr_irqs and set_nr_servers to
 xics_spapr.c]
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 1cbd22205594c4cf024c50cb437755c64f385da1
      
https://github.com/qemu/qemu/commit/1cbd22205594c4cf024c50cb437755c64f385da1
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M hw/intc/xics.c
    M hw/intc/xics_spapr.c
    M include/hw/ppc/xics.h

  Log Message:
  -----------
  ppc/xics: Implement H_IPOLL using an accessor

None of the other presenter functions directly mucks with the
internal state, so don't do it there either.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 27f2458245e259618beb2635abccf00286ea8b2d
      
https://github.com/qemu/qemu/commit/27f2458245e259618beb2635abccf00286ea8b2d
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M hw/intc/xics.c
    M hw/intc/xics_kvm.c
    M hw/intc/xics_spapr.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_cpu_core.c
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_vio.c
    M include/hw/pci-host/spapr.h
    M include/hw/ppc/spapr.h
    M include/hw/ppc/spapr_vio.h
    M include/hw/ppc/xics.h

  Log Message:
  -----------
  ppc/xics: Replace "icp" with "xics" in most places

The "ICP" is a different object than the "XICS". For historical reasons,
we have a number of places where we name a variable "icp" while it contains
a XICSState pointer. There *is* an ICPState structure too so this makes
the code really confusing.

This is a mechanical replacement of all those instances to use the name
"xics" instead. There should be no functional change.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[spapr_cpu_init has been moved to spapr_cpu_core.c, change there]
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9e196938aa1c0517f81139bda0f2f26e0347c64e
      
https://github.com/qemu/qemu/commit/9e196938aa1c0517f81139bda0f2f26e0347c64e
  Author: Aaron Larson <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: gen_pause for instructions: yield, mdoio, mdoom, miso

Call gen_pause for all "or rx,rx,rx" encodings other nop.  This
provides a reasonable implementation for yield, and a better
approximation for mdoio, mdoom, and miso.  The choice to pause for all
encodings !=0 leverages the PowerISA admonition that the reserved
encodings might change program priority, providing a slight "future
proofing".

Signed-off-by: Aaron Larson <address@hidden>
Acked-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 470f2157877d49034d2ae0e755fbd4d059def164
      
https://github.com/qemu/qemu/commit/470f2157877d49034d2ae0e755fbd4d059def164
  Author: Bharata B Rao <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M hw/ppc/spapr_cpu_core.c

  Log Message:
  -----------
  spapr: Restore support for 970MP and POWER8NVL CPU cores

Introduction of core based CPU hotplug for PowerPC sPAPR didn't
add support for 970MP and POWER8NVL based core types. Add support for
the same.

While we are here, add support for explicit specification of POWER5+_v2.1
core type.

Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 8e758dee663bfda2ccfe0076914bf49108055386
      
https://github.com/qemu/qemu/commit/8e758dee663bfda2ccfe0076914bf49108055386
  Author: Greg Kurz <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M hw/ppc/spapr_cpu_core.c

  Log Message:
  -----------
  spapr: drop reference on child object during core realization

When a core is being realized, we create a child object for each thread
of the core.

The child is first initialized with object_initialize() which sets its ref
count to 1, and then added to the core with object_property_add_child()
which bumps the ref count to 2.

When the core gets released, object_unparent() decreases the ref count to 1,
and we g_free() the object: we hence loose the reference on an unfinalized
object. This is likely to cause random crashes.

Let's drop the extra reference as soon as we don't need it, after the
thread is added to the core.

Signed-off-by: Greg Kurz <address@hidden>
Reviewed-by: Bharata B Rao <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f11235b92065e06e789ee1b523dd71999bc6b3e6
      
https://github.com/qemu/qemu/commit/f11235b92065e06e789ee1b523dd71999bc6b3e6
  Author: Greg Kurz <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M hw/ppc/spapr_cpu_core.c

  Log Message:
  -----------
  spapr: do proper error propagation in spapr_cpu_core_realize_child()

This patch changes spapr_cpu_core_realize_child() to have a local error
pointer and use error_propagate() as it is supposed to be done.

Signed-off-by: Greg Kurz <address@hidden>
Reviewed-by: Bharata B Rao <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 8a1eb71bd8cf46a0fd163bc8805a3e86762ea798
      
https://github.com/qemu/qemu/commit/8a1eb71bd8cf46a0fd163bc8805a3e86762ea798
  Author: Greg Kurz <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M hw/ppc/spapr_cpu_core.c

  Log Message:
  -----------
  spapr: drop duplicate variable in spapr_core_release()

Signed-off-by: Greg Kurz <address@hidden>
Reviewed-by: Bharata B Rao <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 13f5e8003e7b67039cb7a19e41b4f7f7ac669cb3
      
https://github.com/qemu/qemu/commit/13f5e8003e7b67039cb7a19e41b4f7f7ac669cb3
  Author: Igor Mammedov <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M qmp-commands.hx

  Log Message:
  -----------
  qmp: fix spapr example of query-hotpluggable-cpus

27393c33 qapi: keep names in 'CpuInstanceProperties' in sync with struct CPUCore
added -id suffix to property names but forgot to fix example in qmp-commands.hx

Fix example to have 'core-id' instead of 'core' to match current code

Signed-off-by: Igor Mammedov <address@hidden>
Reviewed-by: Peter Krempa <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 1b756f1abfb68130dc79e998fc501a032b2ca29d
      
https://github.com/qemu/qemu/commit/1b756f1abfb68130dc79e998fc501a032b2ca29d
  Author: Peter Maydell <address@hidden>
  Date:   2016-07-01 (Fri, 01 Jul 2016)

  Changed paths:
    M default-configs/ppc64-softmmu.mak
    M hw/intc/Makefile.objs
    M hw/intc/xics.c
    M hw/intc/xics_kvm.c
    A hw/intc/xics_spapr.c
    M hw/ppc/e500.c
    M hw/ppc/e500.h
    M hw/ppc/ppc.c
    M hw/ppc/ppce500_spin.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_cpu_core.c
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_vio.c
    M include/hw/pci-host/spapr.h
    M include/hw/ppc/spapr.h
    M include/hw/ppc/spapr_vio.h
    M include/hw/ppc/xics.h
    M qmp-commands.hx
    M target-ppc/cpu-qom.h
    M target-ppc/cpu.h
    M target-ppc/excp_helper.c
    M target-ppc/helper.h
    M target-ppc/helper_regs.h
    M target-ppc/mmu-hash64.c
    M target-ppc/timebase_helper.c
    M target-ppc/translate.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160701' into 
staging

ppc patch queue 2016-07-01

Here's the current ppc patch queue.  This is a fairly large batch,
containing:
    * A number of further preliminary patches towards full hypervisor
      mode emulation
    * Some further fixes / cleanups for the recently merged device_add
      based CPU hotplug
    * Preliminary patches towards supporting a native (rather than
      paravirtualized) XICS device.  This will be needed to emulate a
      physical Power machine, including hypervisor capabilities
    * Assorted bug fixes

# gpg: Signature made Fri 01 Jul 2016 06:56:35 BST
# gpg:                using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>"
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.7-20160701: (23 commits)
  qmp: fix spapr example of query-hotpluggable-cpus
  spapr: drop duplicate variable in spapr_core_release()
  spapr: do proper error propagation in spapr_cpu_core_realize_child()
  spapr: drop reference on child object during core realization
  spapr: Restore support for 970MP and POWER8NVL CPU cores
  target-ppc: gen_pause for instructions: yield, mdoio, mdoom, miso
  ppc/xics: Replace "icp" with "xics" in most places
  ppc/xics: Implement H_IPOLL using an accessor
  ppc/xics: Move SPAPR specific code to a separate file
  ppc/xics: Rename existing xics to xics_spapr
  ppc: Fix 64K pages support in full emulation
  target-ppc: Eliminate redundant and incorrect function 
booke206_page_size_to_tlb
  spapr: Restore support for older PowerPC CPU cores
  spapr: fix write-past-end-of-array error in cpu core device init code
  hw/ppc/spapr: Add some missing hcall function set strings
  ppc: Print HSRR0/HSRR1 in "info registers"
  ppc: LPCR is a HV resource
  ppc: Initial HDEC support
  ppc: Enforce setting MSR:EE,IR and DR when MSR:PR is set
  ppc: Fix conditions for delivering external interrupts to a guest
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/94e31093ff34...1b756f1abfb6
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