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[Qemu-commits] [qemu/qemu] c11759: powerpc/mm: Update the WIMG check dur
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[Qemu-commits] [qemu/qemu] c11759: powerpc/mm: Update the WIMG check during H_ENTER |
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Date: |
Thu, 23 Jun 2016 05:00:07 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: c117590769ea863da3ac082863e6c2ee1cce3eca
https://github.com/qemu/qemu/commit/c117590769ea863da3ac082863e6c2ee1cce3eca
Author: Aneesh Kumar K.V <address@hidden>
Date: 2016-06-22 (Wed, 22 Jun 2016)
Changed paths:
M hw/ppc/spapr_hcall.c
Log Message:
-----------
powerpc/mm: Update the WIMG check during H_ENTER
Support for 0 value for memeory coherence is optional and with ppc64
we can always enable memory coherence. Linux kernel did that during
the development of 4.7 kernel. But that resulted in failure in Qemu
in H_ENTER hcall due to below check. The mentioned change was reverted
in the kernel and kernel right now enable memory coherence only if
cache inhibited is not set. Nevertheless update qemu WIMG flag check
to cover the case where we enable memory coherence along with cache
inhibited flag.
In order to handle older and newer kernel version consider both Cache
inhibitted and (cache inhibitted | memory conference) as valid values
for wimg flags.
Signed-off-by: Aneesh Kumar K.V <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 0ccac16f59462b8e2b9afbc1a602558ea3784f74
https://github.com/qemu/qemu/commit/0ccac16f59462b8e2b9afbc1a602558ea3784f74
Author: Thomas Huth <address@hidden>
Date: 2016-06-22 (Wed, 22 Jun 2016)
Changed paths:
M tests/Makefile.include
Log Message:
-----------
tests: Use '+=' to add additional tests, not '='
The recent commit that added the prom-env-test accidentially
overwrote the check-qtest-ppc-y, check-qtest-ppc64-y and
check-qtest-sparc-y variables instead of extending them.
Fixes: fcbf4a3c0c576eec1321f9cff4fa0dd8e0b1a82f
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 7f2b1744b3ea0f9860ece4bd9493d88286601408
https://github.com/qemu/qemu/commit/7f2b1744b3ea0f9860ece4bd9493d88286601408
Author: Laurent Vivier <address@hidden>
Date: 2016-06-22 (Wed, 22 Jun 2016)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
ppc64: disable gen_pause() for linux-user mode
While trying to install a fedora container with
"lxc-create -t fedora -- -I qemu-ppc64" the installation abort with
the following error:
qemu: fatal: Unknown exception 0x65537. Aborting
NIP 0000004000927924 LR 00000040009e325c CTR 0000004000927480 XER
0000000000000000 CPU#0
MSR 9000000102806000 HID0 0000000000000000 HF 9000000002806000 iidx 3 didx 3
TB 00248932 1069155773327487
GPR00 00000040009e325c 00000040007ff800 0000004000aba098 0000000000000000
GPR04 00000040007ff878 0000004000dcb588 0000004000dcb830 0000004000a7a098
GPR08 0000000000000000 0000000000000000 00000040007ff878 0000004000927960
GPR12 0000000022022448 0000004000e2aef0 0000000000000000 0000000000000000
GPR16 0000000000000000 0000000000000000 0000000000000002 0000000000000001
GPR20 0000000000000000 0000000000000000 0000000000000000 0000004000800699
GPR24 0000004000e13320 0000000000000000 0000004000ac9ad8 0000004000ac9ae0
GPR28 0000000000000001 00000000100210a0 0000000000000000 0000000000000038
CR 22022442 [ E E - E E G G E ] RES ffffffffffffffff
FPR00 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR04 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR08 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR12 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR16 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR20 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR24 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR28 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPSCR 0000000000000000
/usr/share/lxc/templates/lxc-fedora: line 487: 26661 Aborted
(core dumped) chroot . yum -y --nogpgcheck --installroot /run/install install
python rpm yum
I've bisected until the commit:
commit b68e60e6f0d2865e961a800fb8db96a7fc6494c4
Author: Benjamin Herrenschmidt <address@hidden>
Date: Tue May 3 18:03:33 2016 +0200
ppc: Get out of emulation on SMT "OR" ops
Otherwise tight loops at smt_low for example, which OPAL does,
eat so much CPU that we can't boot a kernel anymore. With that,
I can boot 8 CPUs just fine with powernv.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
We can fix that by preventing to send EXCP_HLT in the case of linux-user mode,
as the main loop doesn't know how to manage it.
Signed-off-by: Laurent Vivier <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 820724d170dd97bd216810c6965ee1ebd0ba01e8
https://github.com/qemu/qemu/commit/820724d170dd97bd216810c6965ee1ebd0ba01e8
Author: Richard Henderson <address@hidden>
Date: 2016-06-22 (Wed, 22 Jun 2016)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Fix rlwimi, rlwinm, rlwnm again
In 63ae0915f8ec, I arranged to use a 32-bit rotate, without
considering the effect of a mask value that wraps around to
the high bits of the word.
[dwg: In 2e11b15 this was partially fixed, but an edge case was still
incorrect, which this fixes]
Signed-off-by: Richard Henderson <address@hidden>
[dwg: Folded with a revert of 2e11b15, an earlier buggy version of
this patch which already went upstream]
Tested-by: Anton Blanchard <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f0278900d38b2d8d9531c484bd088d9a7d5d4ea2
https://github.com/qemu/qemu/commit/f0278900d38b2d8d9531c484bd088d9a7d5d4ea2
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2016-06-22 (Wed, 22 Jun 2016)
Changed paths:
M target-ppc/helper.h
M target-ppc/misc_helper.c
M target-ppc/translate_init.c
Log Message:
-----------
ppc: Improve emulation of THRM registers
The 75x and 74xx processors have some thermal monitoring SPRs that
some OSes such as MacOS do use. Our current "dumb" implementation
isn't good enough and will cause some versions of MacOS to hang during
boot.
This lifts an improved emulation from MacOnLinux and adapts it to
qemu, thus fixing the problem.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[dwg: Fixed typo in comment, a number of minor checkpatch warnings,
and a compile failure with CONFIG_USER_ONLY]
Signed-off-by: David Gibson <address@hidden>
Commit: f682e9c244af7166225f4a50cc18ff296bb9d43e
https://github.com/qemu/qemu/commit/f682e9c244af7166225f4a50cc18ff296bb9d43e
Author: Alexey Kardashevskiy <address@hidden>
Date: 2016-06-22 (Wed, 22 Jun 2016)
Changed paths:
M hw/ppc/spapr_iommu.c
M hw/vfio/common.c
M include/exec/memory.h
M memory.c
Log Message:
-----------
memory: Add reporting of supported page sizes
Every IOMMU has some granularity which MemoryRegionIOMMUOps::translate
uses when translating, however this information is not available outside
the translate context for various checks.
This adds a get_min_page_size callback to MemoryRegionIOMMUOps and
a wrapper for it so IOMMU users (such as VFIO) can know the minimum
actual page size supported by an IOMMU.
As IOMMU MR represents a guest IOMMU, this uses TARGET_PAGE_SIZE
as fallback.
This removes vfio_container_granularity() and uses new helper in
memory_region_iommu_replay() when replaying IOMMU mappings on added
IOMMU memory region.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Acked-by: Alex Williamson <address@hidden>
[dwg: Removed an unnecessary calculation]
Signed-off-by: David Gibson <address@hidden>
Commit: a2e71b28e832346409efc795ecd1f0a2bcb705a3
https://github.com/qemu/qemu/commit/a2e71b28e832346409efc795ecd1f0a2bcb705a3
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M target-ppc/excp_helper.c
M target-ppc/translate.c
Log Message:
-----------
ppc: Fix rfi/rfid/hrfi/... emulation
This reworks emulation of the various "rfi" variants. I removed
some masking bits that I couldn't make sense of, the only bit that
I am aware we should mask here is POW, the CPU's MSR mask should
take care of the rest.
This also fixes some problems when running 32-bit userspace under
a 64-bit kernel.
This patch broke 32bit OpenBIOS when run under a 970 cpu. A fix was
proposed here :
https://www.coreboot.org/pipermail/openbios/2016-June/009452.html
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[clg: updated the commit log with the reference of the openbios fix ]
Signed-off-by: Cédric Le Goater <address@hidden>
[dwg: Remove hunk which disabled rfi on 64-bit CPUS. The change was
correct, but we need to fix OpenBIOS before applying it]
Signed-off-by: David Gibson <address@hidden>
Commit: 61687db252da0df7e584668ed665f1075dd179fa
https://github.com/qemu/qemu/commit/61687db252da0df7e584668ed665f1075dd179fa
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
ppc: define a default LPCR value
This allows us to set the appropriate LPCR bits which will be used
when fixing the exception model for the HV mode.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[clg: previous commit 26a7f1291bb5 did not include the LPCR setting as
it was not needed at the time, adapted commit log ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 6d49d6d4edb8106f1a83375d91fa518c631ba00f
https://github.com/qemu/qemu/commit/6d49d6d4edb8106f1a83375d91fa518c631ba00f
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M target-ppc/excp_helper.c
Log Message:
-----------
ppc: fix exception model for HV mode
This properly implements LPES0 handling for HV vs. !HV mode and
removes the unsupported LPES1. This has been removed from the specs
since ISA v2.07.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: AIL implementation was fixed in commit 5c94b2a5e5ef. This patch
only contains the bits of the original patch related to LPES0
handling, adapted commit log.
fixed checkpatch.pl errors. ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f03a1af581b926118d619ad1acc3304ad84d5e5b
https://github.com/qemu/qemu/commit/f03a1af581b926118d619ad1acc3304ad84d5e5b
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M target-ppc/cpu.h
M target-ppc/translate_init.c
Log Message:
-----------
ppc: Fix POWER7 and POWER8 exception definitions
We were initializing unused ones and missing some
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[clg: fixed checkpatch.pl errors ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 33595dc9f3f4839fa7d1195df6007f3457e515be
https://github.com/qemu/qemu/commit/33595dc9f3f4839fa7d1195df6007f3457e515be
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M target-ppc/mmu-hash64.c
Log Message:
-----------
ppc: Fix generation if ISI/DSI vs. HV mode
Under some circumstances, we need to direct ISI and DSI interrupts
at the hypervisor, turning them into HISI/HDSI, and using different
SPRs (HDSISR and HDAR) depending on the combination of MSR_DR and
the corresponding VPM bits in LPCR.
This moves part of the code into helpers that are fixed to select
the right exception type and registers. On pre-P7 processors, LPCR
is 0 which provides the old behaviour of directing the interrupts
at the supervisor.
Thanks to Andrei Warkentin for finding a bug when HV=1
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[clg: Merged a fix on POWERPC_EXCP_HDSI fixing the condition on
msr_hv, from Andrei Warkentin <address@hidden> ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 9b2fadda3e0196ffd485adde4fe9cdd6fae35300
https://github.com/qemu/qemu/commit/9b2fadda3e0196ffd485adde4fe9cdd6fae35300
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M linux-user/main.c
M target-ppc/excp_helper.c
M target-ppc/translate.c
Log Message:
-----------
ppc: Rework generation of priv and inval interrupts
Recent server processors use the Hypervisor Emulation Assistance
interrupt for illegal instructions and *some* type of SPR accesses.
Also the code was always generating inval instructions even for priv
violations due to setting the wrong flags
Finally, the checking for PR/HV was open coded everywhere.
This reworks it all, using little helper macros for checking, and
adding the HV interrupt (which gets converted back to program check
in the slow path of excp_helper.c on CPUs that don't want it).
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: fixed checkpatch.pl errors ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b781537560e3b968b6fe1395e3d07bd67f0009ba
https://github.com/qemu/qemu/commit/b781537560e3b968b6fe1395e3d07bd67f0009ba
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M target-ppc/cpu.h
M target-ppc/translate.c
M target-ppc/translate_init.c
Log Message:
-----------
ppc: Add real mode CI load/store instructions for P7 and P8
Those instructions are only available in hypervisor real mode and
allow cache inhibited garded access to devices in that mode.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: fixed checkpatch.pl errors ]
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5c3ae92910d4cfafd93aa10f107b5da3efb6558a
https://github.com/qemu/qemu/commit/5c3ae92910d4cfafd93aa10f107b5da3efb6558a
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
ppc: Turn a bunch of booleans from int to bool
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b9971cc53e31d0c6139dd74acd879d8a902577ef
https://github.com/qemu/qemu/commit/b9971cc53e31d0c6139dd74acd879d8a902577ef
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
ppc: Move exception generation code out of line
There's no point inlining this, if you hit the exception case you exit
anyway, and not inlining saves about 100K of code size (and cache
footprint).
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: removed '__attribute__((noinline))' from original patch ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 7778a575c7055276afdd01737e9d1029a65f923d
https://github.com/qemu/qemu/commit/7778a575c7055276afdd01737e9d1029a65f923d
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M target-ppc/cpu-qom.h
M target-ppc/cpu.h
M target-ppc/excp_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
M target-ppc/translate_init.c
Log Message:
-----------
ppc: Add P7/P8 Power Management instructions
This adds the ISA 2.06 and later power management instructions
(doze, nap, sleep and rvwinkle) and associated wakeup cause testing
in LPCR
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: fixed checkpatch.pl errors ]
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 86b50f2e1befc33407bdfeb6f45f7b0d2439a740
https://github.com/qemu/qemu/commit/86b50f2e1befc33407bdfeb6f45f7b0d2439a740
Author: Thomas Huth <address@hidden>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M target-ppc/kvm.c
Log Message:
-----------
ppc: Disable huge page support if it is not available for main RAM
On powerpc, we must only signal huge page support to the guest if
all memory areas are capable of supporting huge pages. The commit
2d103aae8765 ("fix hugepage support when using memory-backend-file")
already fixed the case when the user specified the mem-path property
for NUMA memory nodes instead of using the global "-mem-path" option.
However, there is one more case where it currently can go wrong.
When specifying additional memory DIMMs without using NUMA, e.g.
qemu-system-ppc64 -enable-kvm ... -m 1G,slots=2,maxmem=2G \
-device pc-dimm,id=dimm-mem1,memdev=mem1 -object \
memory-backend-file,policy=default,mem-path=/...,size=1G,id=mem1
the code in getrampagesize() currently assumes that huge pages
are possible since they are enabled for the mem1 object. But
since the main RAM is not backed by a huge page filesystem,
the guest Linux kernel then crashes very quickly after being
started. So in case the we've got "normal" memory without NUMA
and without the global "-mem-path" option, we must not announce
huge pages to the guest. Since this is likely a mis-configuration
by the user, also spill out a message in this case.
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c7288767523f6510cf557707d3eb5e78e519b90d
https://github.com/qemu/qemu/commit/c7288767523f6510cf557707d3eb5e78e519b90d
Author: Peter Maydell <address@hidden>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_iommu.c
M hw/vfio/common.c
M include/exec/memory.h
M linux-user/main.c
M memory.c
M target-ppc/cpu-qom.h
M target-ppc/cpu.h
M target-ppc/excp_helper.c
M target-ppc/helper.h
M target-ppc/kvm.c
M target-ppc/misc_helper.c
M target-ppc/mmu-hash64.c
M target-ppc/translate.c
M target-ppc/translate_init.c
M tests/Makefile.include
Log Message:
-----------
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160623' into
staging
ppc patch queue for 2016-06-23
Currently outstanding patches for spapr, target-ppc and related
devices. This batch has:
* Significant new progress towards full support for hypervisor
mode
* Assorted bugfixes
* Some preliminary patches towards dynamic DMA window support
The last involves a change to memory.c, which Paolo has said I can
take through this tree.
# gpg: Signature made Thu 23 Jun 2016 06:47:53 BST
# gpg: using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg: aka "David Gibson (Red Hat) <address@hidden>"
# gpg: aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg: It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.7-20160623:
ppc: Disable huge page support if it is not available for main RAM
ppc: Add P7/P8 Power Management instructions
ppc: Move exception generation code out of line
ppc: Turn a bunch of booleans from int to bool
ppc: Add real mode CI load/store instructions for P7 and P8
ppc: Rework generation of priv and inval interrupts
ppc: Fix generation if ISI/DSI vs. HV mode
ppc: Fix POWER7 and POWER8 exception definitions
ppc: fix exception model for HV mode
ppc: define a default LPCR value
ppc: Fix rfi/rfid/hrfi/... emulation
memory: Add reporting of supported page sizes
ppc: Improve emulation of THRM registers
target-ppc: Fix rlwimi, rlwinm, rlwnm again
ppc64: disable gen_pause() for linux-user mode
tests: Use '+=' to add additional tests, not '='
powerpc/mm: Update the WIMG check during H_ENTER
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/c6eb076aecbe...c7288767523f
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