[Qemu-commits] [qemu/qemu] 2a5a9a: target-arm: Add the HSTR_EL2 register

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 2a5a9abd4bc45e2f4c62c77e07aebe53608c6915
      
https://github.com/qemu/qemu/commit/2a5a9abd4bc45e2f4c62c77e07aebe53608c6915
  Author: Alistair Francis <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add the HSTR_EL2 register

Add the Hypervisor System Trap Register for EL2.

This register is used early in the Linux boot and without it the kernel
aborts with a "Synchronous Abort" error.

Signed-off-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: aaa1f954d4cab243e3d5337a72bc6d104e1c4808
      
https://github.com/qemu/qemu/commit/aaa1f954d4cab243e3d5337a72bc6d104e1c4808
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: A64: Create Instruction Syndromes for Data Aborts

Add support for generating the ISS (Instruction Specific Syndrome) for
Data Abort exceptions taken from AArch64.
These syndromes are used by hypervisors for example to trap and emulate
memory accesses.

We save the decoded data out-of-band with the TBs at translation time.
When exceptions hit, the extra data attached to the TB is used to
recreate the state needed to encode instruction syndromes.
This avoids the need to emit moves with every load/store.

Based on a suggestion from Peter Maydell.

Suggested-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 04ce861ea545477425ad9e045eec3f61c8a27df9
      
https://github.com/qemu/qemu/commit/04ce861ea545477425ad9e045eec3f61c8a27df9
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M target-arm/internals.h

  Log Message:
  -----------
  target-arm: Set IL bit in syndromes for insn abort, watchpoint, swstep

For some exception syndrome types, the IL bit should always be set.
This includes the instruction abort, watchpoint and software step
syndrome types; add the missing ARM_EL_IL bit to the syndrome
values returned by syn_insn_abort(), syn_swstep() and syn_watchpoint().

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 78f1edb19fe11fa0c5d0bf484db59a384f455d3c
      
https://github.com/qemu/qemu/commit/78f1edb19fe11fa0c5d0bf484db59a384f455d3c
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64()

Remove some incorrect code from arm_cpu_do_interrupt_aarch64()
which attempts to set the IL bit in the syndrome register based
on the value of env->thumb. This is wrong in several ways:
 * IL doesn't indicate Thumb-vs-ARM, it indicates instruction
   length (which may be 16 or 32 for Thumb and is always 32 for ARM)
 * not every syndrome format uses IL like this -- for some IL is
   always set, and for some it is always clear
 * the code is changing esr_el[new_el] even for interrupt entry,
   which is not supposed to modify ESR_ELx at all

Delete the code, and instead rely on the syndrome value in
env->exception.syndrome having already been set up with the
correct value of IL.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: e40c3d2e7f4b58669a1b4e5dfb684e57c0bf62ce
      
https://github.com/qemu/qemu/commit/e40c3d2e7f4b58669a1b4e5dfb684e57c0bf62ce
  Author: Ard Biesheuvel <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/arm/virt-acpi-build.c

  Log Message:
  -----------
  hw/arm/virt: fix limit of 64-bit ACPI/ECAM PCI MMIO range

Set the MMIO range limit field to 'base + size - 1' as required.

Signed-off-by: Ard Biesheuvel <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fea8a08e1691a22cdf379dfb32ac3e64648c72b7
      
https://github.com/qemu/qemu/commit/fea8a08e1691a22cdf379dfb32ac3e64648c72b7
  Author: Jens Wiklander <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/intc/arm_gic.c

  Log Message:
  -----------
  hw/intc/gic: RAZ/WI non-sec access to sec interrupts

Treat non-secure accesses to registers and bits in registers of secure
interrupts as RAZ/WI.

Signed-off-by: Jens Wiklander <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1602001195dca96aaea8b16f740ac860238555a5
      
https://github.com/qemu/qemu/commit/1602001195dca96aaea8b16f740ac860238555a5
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/arm/ast2400.c
    M hw/i2c/Makefile.objs
    A hw/i2c/aspeed_i2c.c
    M include/hw/arm/ast2400.h
    A include/hw/i2c/aspeed_i2c.h

  Log Message:
  -----------
  i2c: add aspeed i2c controller

The Aspeed AST2400 integrates a set of 14 I2C/SMBus bus controllers
directly connected to the APB bus. They can be programmed as master or
slave but the propopsed model only supports the master mode.

On the TODO list, we also have :

 - improve and harden the state machine.
 - bus recovery support (used by the Linux driver).
 - transfer mode state machine bits. this is not strictly necessary as
   it is mostly used for debug. The bus busy bit is deducted from the
   I2C core engine of qemu.
 - support of the pool buffer: 2048 bytes of internal SRAM (not used
   by the Linux driver).

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
[PMM: removed unused functions aspeed_i2c_bus_get_state() and
 aspeed_i2c_bus_set_state()]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0bf8039dca6bfecec243a13ebcd224d3941d9242
      
https://github.com/qemu/qemu/commit/0bf8039dca6bfecec243a13ebcd224d3941d9242
  Author: Cole Robinson <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Reject gic-version=host for non-KVM

If you try to gic-version=host with TCG on a KVM aarch64 host,
qemu segfaults, since host requires KVM APIs.

Explicitly reject gic-version=host if KVM is not enabled

https://bugzilla.redhat.com/show_bug.cgi?id=1339977
Signed-off-by: Cole Robinson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 37d42473d173367969ec915be1e40e3d658b8e3b
      
https://github.com/qemu/qemu/commit/37d42473d173367969ec915be1e40e3d658b8e3b
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  xlnx-zynqmp: Add a secure prop to en/disable ARM Security Extensions

Add a secure prop to en/disable ARM Security Extensions.
This is particularly useful for KVM runs.

Default to disabled to match the behavior of KVM.

This changes the default setup from having the ARM Security
Extensions to not longer having them.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6ed92b14f610c78aea52b087d6bdc59a3f2de72a
      
https://github.com/qemu/qemu/commit/6ed92b14f610c78aea52b087d6bdc59a3f2de72a
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  xlnx-zynqmp: Make the RPU subsystem optional

The way we currently model the RPU subsystem is of quite
limited use. In addition to that, it causes problems for
KVM and for GDB debugging.

Make the RPU optional by adding a has_rpu property and
default to having it disabled.

This changes the default setup from having the RPU to not
longer having it.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0776d9679da63bcfddd41dce0f1b9ae127542cb3
      
https://github.com/qemu/qemu/commit/0776d9679da63bcfddd41dce0f1b9ae127542cb3
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c

  Log Message:
  -----------
  xlnx-zynqmp: Delay realization of GIC until post CPU realization

Delay the realization of the GIC until after CPUs are
realized. This is needed for KVM as the in-kernel GIC
model will fail if it is realized with no available CPUs.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2a0ee672c9f0a13fd0535d831366670561b4586e
      
https://github.com/qemu/qemu/commit/2a0ee672c9f0a13fd0535d831366670561b4586e
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c

  Log Message:
  -----------
  xlnx-zynqmp: Use the in kernel GIC model for KVM runs

Use the in kernel GIC model when running with KVM enabled.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e91171e30235ae99ab8060988aa3c9536692bba8
      
https://github.com/qemu/qemu/commit/e91171e30235ae99ab8060988aa3c9536692bba8
  Author: Dmitry Osipenko <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/core/ptimer.c

  Log Message:
  -----------
  hw/ptimer: Fix issues caused by the adjusted timer limit value

Multiple issues here related to the timer with a adjusted .limit value:

1) ptimer_get_count() returns incorrect counter value for the disabled
timer after loading the counter with a small value, because adjusted limit
value is used instead of the original.

For instance:
    1) ptimer_stop(t)
    2) ptimer_set_period(t, 1)
    3) ptimer_set_limit(t, 0, 1)
    4) ptimer_get_count(t) <-- would return 10000 instead of 0

2) ptimer_get_count() might return incorrect value for the timer running
with a adjusted limit value.

For instance:
    1) ptimer_stop(t)
    2) ptimer_set_period(t, 1)
    3) ptimer_set_limit(t, 10, 1)
    4) ptimer_run(t)
    5) ptimer_get_count(t) <-- might return value > 10

3) Neither ptimer_set_period() nor ptimer_set_freq() are adjusting the
limit value, so it is still possible to make timer timeout value
arbitrary small.

For instance:
    1) ptimer_set_period(t, 10000)
    2) ptimer_set_limit(t, 1, 0)
    3) ptimer_set_period(t, 1) <-- bypass limit correction

Fix all of the above issues by adjusting timer period instead of the limit.
Perform the adjustment for periodic timer only. Use the delta value instead
of the limit to make decision whether adjustment is required, as limit could
be altered while timer is running, resulting in incorrect value returned by
ptimer_get_count.

Signed-off-by: Dmitry Osipenko <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5a50307b48f834d0048fde20aa6c0e24cd9f33be
      
https://github.com/qemu/qemu/commit/5a50307b48f834d0048fde20aa6c0e24cd9f33be
  Author: Dmitry Osipenko <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/core/ptimer.c

  Log Message:
  -----------
  hw/ptimer: Perform counter wrap around if timer already expired

ptimer_get_count() might be called while QEMU timer already been expired.
In that case ptimer would return counter = 0, which might be undesirable
in case of polled timer. Do counter wrap around for periodic timer to keep
it distributed. In order to achieve more accurate emulation behaviour of
certain hardware, don't perform wrap around when in icount mode and return
counter = 0 in that case (that doesn't affect polled counter distribution).

Signed-off-by: Dmitry Osipenko <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7ef6e3cf8d29022c31d417be12042af33682e2b8
      
https://github.com/qemu/qemu/commit/7ef6e3cf8d29022c31d417be12042af33682e2b8
  Author: Dmitry Osipenko <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/core/ptimer.c

  Log Message:
  -----------
  hw/ptimer: Update .delta on period/freq change

Delta value must be updated on period/freq change, otherwise running timer
would be restarted (counter reloaded with old delta). Only m68k/mcf520x
and arm/arm_timer devices are currently doing freq change correctly, i.e.
stopping the timer. Perform delta update to fix affected devices and
eliminate potential further mistakes.

Signed-off-by: Dmitry Osipenko <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 869e92b5c392eb6b2c7b398b878c435442b8e9dd
      
https://github.com/qemu/qemu/commit/869e92b5c392eb6b2c7b398b878c435442b8e9dd
  Author: Dmitry Osipenko <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/core/ptimer.c

  Log Message:
  -----------
  hw/ptimer: Support "on the fly" timer mode switch

Allow switching between periodic <-> oneshot modes while timer is running.

Signed-off-by: Dmitry Osipenko <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 578c4b2f23debf68a0e081279f91be0e96525824
      
https://github.com/qemu/qemu/commit/578c4b2f23debf68a0e081279f91be0e96525824
  Author: Dmitry Osipenko <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/core/ptimer.c
    M include/hw/ptimer.h

  Log Message:
  -----------
  hw/ptimer: Introduce ptimer_get_limit

Currently ptimer users are used to store copy of the limit value, because
ptimer doesn't provide facility to retrieve the limit. Let's provide it.

Signed-off-by: Dmitry Osipenko <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f0d1d2c115dffc1fbaf954d0b449db05c5eb79b1
      
https://github.com/qemu/qemu/commit/f0d1d2c115dffc1fbaf954d0b449db05c5eb79b1
  Author: xiaoqiang zhao <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/arm/bcm2835_peripherals.c
    M hw/arm/highbank.c
    M hw/arm/integratorcp.c
    M hw/arm/realview.c
    M hw/arm/stellaris.c
    M hw/arm/versatilepb.c
    M hw/arm/vexpress.c
    M hw/arm/virt.c
    M hw/char/pl011.c
    A include/hw/char/pl011.h

  Log Message:
  -----------
  hw/char: QOM'ify pl011 model

* drop qemu_char_get_next_serial and use chardev prop
* add pl011_create wrapper function to create pl011 uart device
* change affected board code to use the new way

Signed-off-by: xiaoqiang zhao <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4be12ea09acc32f7e1b9d11e9f34969c7ae603ee
      
https://github.com/qemu/qemu/commit/4be12ea09acc32f7e1b9d11e9f34969c7ae603ee
  Author: xiaoqiang zhao <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/arm/xilinx_zynq.c
    M hw/arm/xlnx-zynqmp.c
    M hw/char/cadence_uart.c
    M include/hw/char/cadence_uart.h

  Log Message:
  -----------
  hw/char: QOM'ify cadence_uart model

* drop qemu_char_get_next_serial and use chardev prop
* create cadence_uart_create wrapper function to create
  cadence_uart_device
* change affected board code to use the new way

Signed-off-by: xiaoqiang zhao <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 746c3b3eba0d091d2e2d84b63ce4ca3186e212a7
      
https://github.com/qemu/qemu/commit/746c3b3eba0d091d2e2d84b63ce4ca3186e212a7
  Author: xiaoqiang zhao <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/arm/digic.c
    M hw/char/digic-uart.c

  Log Message:
  -----------
  hw/char: QOM'ify digic-uart model

* drop qemu_char_get_next_serial and use chardev prop
* change affected board code to use the new way

Signed-off-by: xiaoqiang zhao <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7bd43519da16633d88e9d2faf8077768a1b36ce9
      
https://github.com/qemu/qemu/commit/7bd43519da16633d88e9d2faf8077768a1b36ce9
  Author: xiaoqiang zhao <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/arm/stm32f205_soc.c
    M hw/char/stm32f2xx_usart.c

  Log Message:
  -----------
  hw/char: QOM'ify stm32f2xx_usart model

* drop qemu_char_get_next_serial and use chardev prop
* change affected board code to use the new way

Signed-off-by: xiaoqiang zhao <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1b6d0781c29412d8a152a39178a91c634d47a823
      
https://github.com/qemu/qemu/commit/1b6d0781c29412d8a152a39178a91c634d47a823
  Author: xiaoqiang zhao <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/char/xilinx_uartlite.c
    M hw/microblaze/petalogix_s3adsp1800_mmu.c
    A include/hw/char/xilinx_uartlite.h

  Log Message:
  -----------
  hw/char: QOM'ify xilinx_uartlite model

* drop qemu_char_get_next_serial and use chardev prop
* create xilinx_uartlite_create wrapper function to create
  xilinx_uartlite device
* change affected board code to use the new way

Signed-off-by: xiaoqiang zhao <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e5fabad7ccfd3b23afd370dba81a93cc280be60e
      
https://github.com/qemu/qemu/commit/e5fabad7ccfd3b23afd370dba81a93cc280be60e
  Author: xiaoqiang zhao <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M include/sysemu/char.h
    M qemu-char.c

  Log Message:
  -----------
  char: get rid of qemu_char_get_next_serial

since there is no user of qemu_char_get_next_serial any more,
it's time to let it go away.

Acked-by: Paolo Bonzini <address@hidden>
Signed-off-by: xiaoqiang zhao <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6e99f762612827afeff54add2e4fc2c3b2657fed
      
https://github.com/qemu/qemu/commit/6e99f762612827afeff54add2e4fc2c3b2657fed
  Author: Sergey Sorokin <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation

Address size is 40-bit for the AArch32 stage 2 translation,
and t0sz can be negative (from -8 to 7),
so we need to adjust it to use the existing TTBR selecting logic.

Signed-off-by: Sergey Sorokin <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0c18c6c67e06859ef354b697cce567ebe29061f1
      
https://github.com/qemu/qemu/commit/0c18c6c67e06859ef354b697cce567ebe29061f1
  Author: Alistair Francis <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/arm/xlnx-ep108.c

  Log Message:
  -----------
  zynqmp: Add the ZCU102 board

Most Zynq UltraScale+ users will be targetting and using the ZCU102
board instead of the development focused EP108. To make our QEMU machine
names clearer add a ZCU102 machine model.

Signed-off-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 76462405809d29bab65a3699686998ba124ab942
      
https://github.com/qemu/qemu/commit/76462405809d29bab65a3699686998ba124ab942
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-06 (Mon, 06 Jun 2016)

  Changed paths:
    M hw/arm/ast2400.c
    M hw/arm/bcm2835_peripherals.c
    M hw/arm/digic.c
    M hw/arm/highbank.c
    M hw/arm/integratorcp.c
    M hw/arm/realview.c
    M hw/arm/stellaris.c
    M hw/arm/stm32f205_soc.c
    M hw/arm/versatilepb.c
    M hw/arm/vexpress.c
    M hw/arm/virt-acpi-build.c
    M hw/arm/virt.c
    M hw/arm/xilinx_zynq.c
    M hw/arm/xlnx-ep108.c
    M hw/arm/xlnx-zynqmp.c
    M hw/char/cadence_uart.c
    M hw/char/digic-uart.c
    M hw/char/pl011.c
    M hw/char/stm32f2xx_usart.c
    M hw/char/xilinx_uartlite.c
    M hw/core/ptimer.c
    M hw/i2c/Makefile.objs
    A hw/i2c/aspeed_i2c.c
    M hw/intc/arm_gic.c
    M hw/microblaze/petalogix_s3adsp1800_mmu.c
    M include/hw/arm/ast2400.h
    M include/hw/arm/xlnx-zynqmp.h
    M include/hw/char/cadence_uart.h
    A include/hw/char/pl011.h
    A include/hw/char/xilinx_uartlite.h
    A include/hw/i2c/aspeed_i2c.h
    M include/hw/ptimer.h
    M include/sysemu/char.h
    M qemu-char.c
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/internals.h
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20160606-1' into staging

target-arm queue:
 * support instruction syndrome info for data aborts from A64 to EL2
 * add HSTR_EL2 register
 * fix incorrect ESR IL bits in various syndrome register cases
 * virt: fix limit of 64-bit ACPI/ECAM PCI MMIO range
 * gicv2: RAZ/WI non-sec access to sec interrupts
 * i2c: add aspeed i2c controller
 * virt: Reject gic-version=host for non-KVM (don't segv on aarch64 host)
 * xlnx-zynqmp: Add a secure prop to en/disable ARM Security Extensions
 * xlnx-zynqmp: Support KVM on AArch64 hosts
 * ptimer: Various fixes for awkward corner cases
 * char: QOMify various ARM UART models
 * char: get rid of qemu_char_get_next_serial
 * target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation
 * zynqmp: Add the ZCU102 board

# gpg: Signature made Mon 06 Jun 2016 17:01:11 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20160606-1: (25 commits)
  zynqmp: Add the ZCU102 board
  target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation
  char: get rid of qemu_char_get_next_serial
  hw/char: QOM'ify xilinx_uartlite model
  hw/char: QOM'ify stm32f2xx_usart model
  hw/char: QOM'ify digic-uart model
  hw/char: QOM'ify cadence_uart model
  hw/char: QOM'ify pl011 model
  hw/ptimer: Introduce ptimer_get_limit
  hw/ptimer: Support "on the fly" timer mode switch
  hw/ptimer: Update .delta on period/freq change
  hw/ptimer: Perform counter wrap around if timer already expired
  hw/ptimer: Fix issues caused by the adjusted timer limit value
  xlnx-zynqmp: Use the in kernel GIC model for KVM runs
  xlnx-zynqmp: Delay realization of GIC until post CPU realization
  xlnx-zynqmp: Make the RPU subsystem optional
  xlnx-zynqmp: Add a secure prop to en/disable ARM Security Extensions
  hw/arm/virt: Reject gic-version=host for non-KVM
  i2c: add aspeed i2c controller
  hw/intc/gic: RAZ/WI non-sec access to sec interrupts
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/280b2358cd1f...76462405809d