[Qemu-commits] [qemu/qemu] 0dc198: hw/arm/bcm2836: Wire up CPU timer interrupts corre...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 0dc1982312a7f8b5379b039d9f799bac343cc8f3
      
https://github.com/qemu/qemu/commit/0dc1982312a7f8b5379b039d9f799bac343cc8f3
  Author: Peter Maydell <address@hidden>
  Date:   2016-04-04 (Mon, 04 Apr 2016)

  Changed paths:
    M hw/arm/bcm2836.c

  Log Message:
  -----------
  hw/arm/bcm2836: Wire up CPU timer interrupts correctly

Wire up the CPU timer interrupts in the right order, with the
nonsecure physical timer on cntpnsirq, the hyp timer on cnthpirq,
and the secure physical timer on cntpsirq. (We did get the
virt timer right, at least.)

Reported-by: Antonio Huete Jiménez <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Andrew Baumann <address@hidden>
Message-id: address@hidden


  Commit: f911e0a323f29ecc780a94380cfbf9f574c19eb7
      
https://github.com/qemu/qemu/commit/f911e0a323f29ecc780a94380cfbf9f574c19eb7
  Author: Peter Maydell <address@hidden>
  Date:   2016-04-04 (Mon, 04 Apr 2016)

  Changed paths:
    M linux-user/main.c

  Log Message:
  -----------
  linux-user: arm: Handle (ignore) EXCP_YIELD in ARM cpu_loop()

The new-in-ARMv8 YIELD instruction has been implemented to throw
an EXCP_YIELD back up to the QEMU main loop. In system emulation
we use this to decide to schedule a different guest CPU in SMP
configurations. In usermode emulation there is nothing to do,
so just ignore it and resume the guest.

This prevents an abort with "unhandled CPU exception 0x10004"
if the guest process uses the YIELD instruction.

Reported-by: Hunter Laux <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: e24fdd238a159d830a9a65dd9b08f80fba9b9e06
      
https://github.com/qemu/qemu/commit/e24fdd238a159d830a9a65dd9b08f80fba9b9e06
  Author: Peter Maydell <address@hidden>
  Date:   2016-04-04 (Mon, 04 Apr 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Correctly reset SCTLR_EL3 for 64-bit CPUs

The regdef for SCTRL_EL3 was incorrectly marked as being an
ARM_CP_ALIAS, with the remark that this was because the 32-bit
definition would take care of reset and migration. However the
intention for banked registers as documented in the comment in
add_cpreg_to_hashtable() is:

 * 2) If ARMv8 is enabled then we can count on a 64-bit version
 *    taking care of the secure bank.  This requires that separate
 *    32 and 64-bit definitions are provided.

and so it marks the 32-bit secure banked version as an alias.
This results in the sctlr_s/sctlr_el[3] field never being reset
or migrated for a 64-bit CPU with EL3 enabled.

Fix this by removing the ARM_CP_ALIAS annotation from SCTLR_EL3.
Since this means it now needs a real reset value, move the regdef
into the same place that we define the 32-bit SCTLR.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: 094a7d0b9d10812d06be2c5c19288cee4603c693
      
https://github.com/qemu/qemu/commit/094a7d0b9d10812d06be2c5c19288cee4603c693
  Author: Peter Maydell <address@hidden>
  Date:   2016-04-04 (Mon, 04 Apr 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3

The regdefs for the ESR_EL2 and ESR_EL3 system registers should not
be marked as ARM_CP_ALIAS, because these are the master copies; the
DFSR regdef in vmsa_pmsa_cp_reginfo[] is marked as an alias.
Remove the ALIAS tags so that these registers are correctly migrated.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: bf06c1123a427fefc2cf9cf8019578eafc19eb6f
      
https://github.com/qemu/qemu/commit/bf06c1123a427fefc2cf9cf8019578eafc19eb6f
  Author: Peter Maydell <address@hidden>
  Date:   2016-04-04 (Mon, 04 Apr 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Make the 64-bit version of VTCR do the migration

Move the ALIAS tag from VTCR_EL2 to VTCR so that we migrate the
64-bit version, as is usual. (This has no particular effect now
unless the guest wrote to the high RES0 bits of VTCR_EL2.)
Add a comment about why it's OK that we don't have the various
accessor functions that the EL1 TCR regdefs do.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: 2e3a76ae3e47d502f9f0c4424b719945fba9d459
      
https://github.com/qemu/qemu/commit/2e3a76ae3e47d502f9f0c4424b719945fba9d459
  Author: Peter Maydell <address@hidden>
  Date:   2016-04-04 (Mon, 04 Apr 2016)

  Changed paths:
    M hw/arm/bcm2836.c
    M linux-user/main.c
    M target-arm/helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160404' 
into staging

target-arm queue:
 * bcm2836: wire up CPU timer interrupts correctly
 * linux-user: ignore EXCP_YIELD in ARM cpu_loop()
 * target-arm: correctly reset SCTLR_EL3
 * target-arm: remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3
 * target-arm: make the 64-bit version of VTCR do the migration

# gpg: Signature made Mon 04 Apr 2016 17:42:16 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20160404:
  target-arm: Make the 64-bit version of VTCR do the migration
  target-arm: Remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3
  target-arm: Correctly reset SCTLR_EL3 for 64-bit CPUs
  linux-user: arm: Handle (ignore) EXCP_YIELD in ARM cpu_loop()
  hw/arm/bcm2836: Wire up CPU timer interrupts correctly

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/c40e13e10624...2e3a76ae3e47