[Qemu-commits] [qemu/qemu] 8b9f21: ppc64: set MSR_SF bit

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 8b9f2118ca40b1de72d8f75b59a5fb4d347a69f7
      
https://github.com/qemu/qemu/commit/8b9f2118ca40b1de72d8f75b59a5fb4d347a69f7
  Author: Laurent Vivier <address@hidden>
  Date:   2016-03-24 (Thu, 24 Mar 2016)

  Changed paths:
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc64: set MSR_SF bit

When a qemu-system-ppc64 is started, the 64-bit mode bit
is not set in MSR.

Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0ddbd0536296f5a36c8f225edd4d14441be6b153
      
https://github.com/qemu/qemu/commit/0ddbd0536296f5a36c8f225edd4d14441be6b153
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2016-03-24 (Thu, 24 Mar 2016)

  Changed paths:
    M hw/ppc/spapr.c
    M target-ppc/kvm.c

  Log Message:
  -----------
  spapr/target-ppc/kvm: Only add hcall-instructions if KVM supports it

ePAPR defines "hcall-instructions" device-tree property which contains
code to call hypercalls in ePAPR paravirtualized guests.  In general
pseries guests won't use this property, instead using the PAPR defined
hypercall interface.

However, this property has been re-used to implement a hack to allow
PR KVM to run (slightly modified) guests in some situations where it
otherwise wouldn't be able to (because the system's L0 hypervisor
doesn't forward the PAPR hypercalls to the PR KVM kernel).

Hence, this property is always present in the device tree for pseries
guests. All KVM guests use it at least to read features via the
KVM_HC_FEATURES hypercall.

The property is populated by the code returned from the KVM's
KVM_PPC_GET_PVINFO ioctl; if not implemented in the KVM, QEMU supplies
code which will fail all hypercall attempts. If QEMU does not create
the property, and the guest kernel is compiled with
CONFIG_EPAPR_PARAVIRT (which is normally the case), there is exactly
the same stub at @epapr_hypercall_start already.

Rather than maintaining this fairly useless stub implementation, it
makes more sense not to create the property in the device tree in the
first place if the host kernel does not implement it.

This changes kvmppc_get_hypercall() to return 1 if the host kernel
does not implement KVM_CAP_PPC_GET_PVINFO. The caller can use it to decide
on whether to create the property or not.

This changes the pseries machine to not create the property if KVM does
not implement KVM_PPC_GET_PVINFO. In practice this means that from now
on the property will not be created if either HV KVM or TCG is used.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
[reworded commit message for clarity --dwg]
Signed-off-by: David Gibson <address@hidden>


  Commit: 1488270e822dc497a9bc799c6c49fdca85b9f28b
      
https://github.com/qemu/qemu/commit/1488270e822dc497a9bc799c6c49fdca85b9f28b
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-03-24 (Thu, 24 Mar 2016)

  Changed paths:
    M target-ppc/cpu.h

  Log Message:
  -----------
  ppc: Update SPR definitions

Add definitions for additional SPR numbers and SPR bit definitions
that will be relevant for subsequent improvements to POWER8 emulation

Also fix the definition of LPIDR which was incorrect (and is different
for server and embedded).

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: eb94268e73a379a54326701a0341f2649e222d29
      
https://github.com/qemu/qemu/commit/eb94268e73a379a54326701a0341f2649e222d29
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-03-24 (Thu, 24 Mar 2016)

  Changed paths:
    M target-ppc/translate.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: Add macros to register hypervisor mode SPRs

The current set of spr_register_* macros only take the user and
supervisor function pointers. To make the transition easy, we
don't change that but we add "_hv" variants that can be used to
register all 3 sets.

To simplify the transition, users of the "old" macro will set the
hypervisor callback to be the same as the supervisor one. The new
registration function only needs to be used for registers that are
either hypervisor only or behave differently in HV mode.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[clg: fixed else if condition in gen_op_mfspr() ]
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f401dd32cb8e9ef68bc4f0d600479f670c2bf39a
      
https://github.com/qemu/qemu/commit/f401dd32cb8e9ef68bc4f0d600479f670c2bf39a
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-03-24 (Thu, 24 Mar 2016)

  Changed paths:
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: Add a bunch of hypervisor SPRs to Book3s

We don't give them a KVM reg number to most of the registers yet as no
current KVM version supports HV mode. For DAWR and DAWRX, the KVM reg
number is needed since this register can be set by the guest via the
H_SET_MODE hypercall.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: squashed in patch 'ppc: Add KVM numbers to some P8 SPRs'
      changed the commit log with a proposal of Thomas Huth
      removed all hunks except those related to AMOR and DAWR* ]
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 26a7f1291bb5581e51c413d744207d0a5910ff4c
      
https://github.com/qemu/qemu/commit/26a7f1291bb5581e51c413d744207d0a5910ff4c
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-03-24 (Thu, 24 Mar 2016)

  Changed paths:
    M hw/ppc/spapr.c
    M target-ppc/cpu.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: Create cpu_ppc_set_papr() helper

And move the code adjusting the MSR mask and calling kvmppc_set_papr()
to it. This allows us to add a few more things such as disabling setting
of MSR:HV and appropriate LPCR bits which will be used when fixing
the exception model.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[clg: removed LPCR setting ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 21a558bed91f363ea8fc3f9a95b222a0949c70e7
      
https://github.com/qemu/qemu/commit/21a558bed91f363ea8fc3f9a95b222a0949c70e7
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-03-24 (Thu, 24 Mar 2016)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: Add dummy SPR_IC for POWER8

It's supposed to be an instruction counter. For now make us not
crash when accessing it.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 6a9c4ef452c98060e919aa49db49c09ed8c37745
      
https://github.com/qemu/qemu/commit/6a9c4ef452c98060e919aa49db49c09ed8c37745
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-03-24 (Thu, 24 Mar 2016)

  Changed paths:
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: Initialize AMOR in PAPR mode

Make sure we give the guest full authorization

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 97eaf30ec68eab6efdedf32ad210581d074bcb03
      
https://github.com/qemu/qemu/commit/97eaf30ec68eab6efdedf32ad210581d074bcb03
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-03-24 (Thu, 24 Mar 2016)

  Changed paths:
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: Fix writing to AMR/UAMOR

The masks weren't chosen nor applied properly. The architecture specifies
that writes to AMR are masked by UAMOR for PR=1, otherwise AMOR for HV=0.

The writes to UAMOR are masked by AMOR for HV=0

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: moved gen_spr_amr() prototype change to next patch ]
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a6eabb9e5908ddf521ea372651b8321ffa804bd8
      
https://github.com/qemu/qemu/commit/a6eabb9e5908ddf521ea372651b8321ffa804bd8
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-03-24 (Thu, 24 Mar 2016)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: Add POWER8 IAMR register

With appropriate AMR-like masks. Not actually used by the translation
logic at that point

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: changed spr_register_hv(SPR_IAMR) to spr_register_kvm_hv(SPR_IAMR)
      changed gen_spr_amr() prototype ]
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: eb5ceb4d389b1b34b210baf9fa49b48bacb2538b
      
https://github.com/qemu/qemu/commit/eb5ceb4d389b1b34b210baf9fa49b48bacb2538b
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-03-24 (Thu, 24 Mar 2016)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: Add dummy CIABR SPR

We should implement HW breakpoint/watchpoint, qemu supports them...

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9c1cf38d28fd0c09efc08b6f9e86dff293248e44
      
https://github.com/qemu/qemu/commit/9c1cf38d28fd0c09efc08b6f9e86dff293248e44
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-03-24 (Thu, 24 Mar 2016)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: A couple more dummy POWER8 Book4 regs

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: squashed in patch 'ppc: Add dummy ACOP SPR' ]
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: d6f39fdfcd30b3f65f9aad396e7caa49285a5a0a
      
https://github.com/qemu/qemu/commit/d6f39fdfcd30b3f65f9aad396e7caa49285a5a0a
  Author: Thomas Huth <address@hidden>
  Date:   2016-03-24 (Thu, 24 Mar 2016)

  Changed paths:
    M hw/net/spapr_llan.c

  Log Message:
  -----------
  hw/net/spapr_llan: Extract rx buffer code into separate functions

Refactor the code a little bit by extracting the code that reads
and writes the receive buffer list page into separate functions.
There should be no functional change in this patch, this is just
a preparation for the upcoming extensions that introduce receive
buffer pools.

Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 831e8822530bb511a24329494f9121ad1f8b94ab
      
https://github.com/qemu/qemu/commit/831e8822530bb511a24329494f9121ad1f8b94ab
  Author: Thomas Huth <address@hidden>
  Date:   2016-03-24 (Thu, 24 Mar 2016)

  Changed paths:
    M hw/net/spapr_llan.c

  Log Message:
  -----------
  hw/net/spapr_llan: Fix receive buffer handling for better performance

tl;dr:
This patch introduces an alternate way of handling the receive
buffers of the spapr-vlan device, resulting in much better
receive performance for the guest.

Full story:
One of our testers recently discovered that the performance of the
spapr-vlan device is very poor compared to other NICs, and that
a simple "ping -i 0.2 -s 65507 someip" in the guest can result
in more than 50% lost ping packets (especially with older guest
kernels < 3.17).

After doing some analysis, it was clear that there is a problem
with the way we handle the receive buffers in spapr_llan.c: The
ibmveth driver of the guest Linux kernel tries to add a lot of
buffers into several buffer pools (with 512, 2048 and 65536 byte
sizes by default, but it can be changed via the entries in the
/sys/devices/vio/1000/pool* directories of the guest). However,
the spapr-vlan device of QEMU only tries to squeeze all receive
buffer descriptors into one single page which has been supplied
by the guest during the H_REGISTER_LOGICAL_LAN call, without
taking care of different buffer sizes. This has two bad effects:
First, only a very limited number of buffer descriptors is accepted
at all. Second, we also hand 64k buffers to the guest even if
the 2k buffers would fit better - and this results in dropped packets
in the IP layer of the guest since too much skbuf memory is used.

Though it seems at a first glance like PAPR says that we should store
the receive buffer descriptors in the page that is supplied during
the H_REGISTER_LOGICAL_LAN call, chapter 16.4.1.2 in the LoPAPR spec
declares that "the contents of these descriptors are architecturally
opaque, none of these descriptors are manipulated by code above
the architected interfaces". That means we don't have to store
the RX buffer descriptors in this page, but can also manage the
receive buffers at the hypervisor level only. This is now what we
are doing here: Introducing proper RX buffer pools which are also
sorted by size of the buffers, so we can hand out a buffer with
the best fitting size when a packet has been received.

To avoid problems with migration from/to older version of QEMU,
the old behavior is also retained and enabled by default. The new
buffer management has to be enabled via a new "use-rx-buffer-pools"
property.

Now with the new buffer pool management enabled, the problem with
"ping -s 65507" is fixed for me, and the throughput of a simple
test with wget increases from creeping 3MB/s up to 20MB/s!

Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 57c522f47bf85de20c5bef3706b6fca6a70d7ac5
      
https://github.com/qemu/qemu/commit/57c522f47bf85de20c5bef3706b6fca6a70d7ac5
  Author: Thomas Huth <address@hidden>
  Date:   2016-03-24 (Thu, 24 Mar 2016)

  Changed paths:
    M hw/net/spapr_llan.c
    M hw/ppc/spapr.c

  Log Message:
  -----------
  hw/net/spapr_llan: Enable the RX buffer pools by default for new machines

RX buffer pools are now enabled by default for new machine types.
For older machine types, they are still disabled to avoid breaking
migration.

Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9d0e5c8ceb70e738101bfcb31fa1c0f7375d844b
      
https://github.com/qemu/qemu/commit/9d0e5c8ceb70e738101bfcb31fa1c0f7375d844b
  Author: Cédric Le Goater <address@hidden>
  Date:   2016-03-24 (Thu, 24 Mar 2016)

  Changed paths:
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: move POWER8 Book4 regs in their own routine

commit fce55481360d "ppc: A couple more dummy POWER8 Book4 regs"
squashed in to rapidly a set of POWER8 Book4 regs in the wrong
routine. This patch introduces the missing gen_spr_power8_book4()
routine to fix their location.

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 490dda053e3324c97b28439813fab4c2f362183e
      
https://github.com/qemu/qemu/commit/490dda053e3324c97b28439813fab4c2f362183e
  Author: Peter Maydell <address@hidden>
  Date:   2016-03-24 (Thu, 24 Mar 2016)

  Changed paths:
    M hw/net/spapr_llan.c
    M hw/ppc/spapr.c
    M target-ppc/cpu.h
    M target-ppc/kvm.c
    M target-ppc/translate.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.6-20160324' into 
staging

ppc patch queue for 2016-03-24

Accumulated patches for target-ppc, pseries machine type and related
devices.

* Preliminary patches from BenH & Cédric Le Goater's powernv code
    * We don't want the full machine type before 2.7
    * Adding some of the SPRs also fixes migration corner cases for
      spapr (when qemu has no knowledge of the registers, they're
      obviously not migrated)
    * We include some patches that aren't strictly fixes, but make
      applying the others easier, and they're low risk
* Fix to buffer management which significantly improves throughput in
  the spapr-llan virtual network device
* Start with 64-bit mode enabled on spapr.  This is the way it's
  supposed to be but we broke it a while back and didn't notice
  because Linux guests cope anyway.
    * Picked up by kvm-unit-tests
    * Still some bugs here that I'm working on

# gpg: Signature made Thu 24 Mar 2016 04:29:42 GMT using RSA key ID 20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>"
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.6-20160324:
  ppc: move POWER8 Book4 regs in their own routine
  hw/net/spapr_llan: Enable the RX buffer pools by default for new machines
  hw/net/spapr_llan: Fix receive buffer handling for better performance
  hw/net/spapr_llan: Extract rx buffer code into separate functions
  ppc: A couple more dummy POWER8 Book4 regs
  ppc: Add dummy CIABR SPR
  ppc: Add POWER8 IAMR register
  ppc: Fix writing to AMR/UAMOR
  ppc: Initialize AMOR in PAPR mode
  ppc: Add dummy SPR_IC for POWER8
  ppc: Create cpu_ppc_set_papr() helper
  ppc: Add a bunch of hypervisor SPRs to Book3s
  ppc: Add macros to register hypervisor mode SPRs
  ppc: Update SPR definitions
  spapr/target-ppc/kvm: Only add hcall-instructions if KVM supports it
  ppc64: set MSR_SF bit

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/10805344811f...490dda053e33