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[Qemu-commits] [qemu/qemu] 1f75cb: target-tricore: add missing break in


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 1f75cb: target-tricore: add missing break in insn decode s...
Date: Thu, 24 Mar 2016 07:00:04 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 1f75cba8f8e0acb079b196e73874595b9523094f
      
https://github.com/qemu/qemu/commit/1f75cba8f8e0acb079b196e73874595b9523094f
  Author: Bastian Koppelmann <address@hidden>
  Date:   2016-03-23 (Wed, 23 Mar 2016)

  Changed paths:
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: add missing break in insn decode switch stmt

After decoding/translating a RRR_DIVIDE/RRRR_EXTRACT_INSERT type instruction
we would simply fall through and would decode/translate another unintended
RRR2_MADD/RRRW_EXTRACT_INSERT instruction.

Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>


  Commit: 9029710b9ead9c11649ec142d18581412d8f3e68
      
https://github.com/qemu/qemu/commit/9029710b9ead9c11649ec142d18581412d8f3e68
  Author: Bastian Koppelmann <address@hidden>
  Date:   2016-03-23 (Wed, 23 Mar 2016)

  Changed paths:
    M target-tricore/op_helper.c

  Log Message:
  -----------
  target-tricore: Fix helper_msub64_q_ssov not reseting OVF bit

When this instruction does not produce an overflow the corresponding
bit has to be reset.

Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>


  Commit: 1bd3e2fc3de683941f18e346a1793b81b20cab2d
      
https://github.com/qemu/qemu/commit/1bd3e2fc3de683941f18e346a1793b81b20cab2d
  Author: Bastian Koppelmann <address@hidden>
  Date:   2016-03-23 (Wed, 23 Mar 2016)

  Changed paths:
    M target-tricore/helper.c

  Log Message:
  -----------
  target-tricore: Fix psw_read() clearing too many bits

psw_read() ought to sync the PSW value with the
cached status bits (C,V,SV,AV,SAV). For this the bits
are cleared in the PSW before they are written from the
cached bits. The clear mask is too big and clears two
additional bits.

Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>


  Commit: 996a729f9b7f93fb921891bf0e07757a29d0c68a
      
https://github.com/qemu/qemu/commit/996a729f9b7f93fb921891bf0e07757a29d0c68a
  Author: Bastian Koppelmann <address@hidden>
  Date:   2016-03-23 (Wed, 23 Mar 2016)

  Changed paths:
    M fpu/softfloat-specialize.h
    M target-tricore/Makefile.objs
    M target-tricore/cpu.h
    A target-tricore/fpu_helper.c
    M target-tricore/helper.c
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: Add FPU infrastructure

This patch adds a file for all the FPU related helpers with all the includes,
useful defines, and a function to update the status bits. Additionally it adds
a mask for the rounding mode bits of PSW as well as all the opcodes for the
FPU instructions.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>


  Commit: c433a17141fb2a400ecb656e55d8d21caa2e2390
      
https://github.com/qemu/qemu/commit/c433a17141fb2a400ecb656e55d8d21caa2e2390
  Author: Bastian Koppelmann <address@hidden>
  Date:   2016-03-23 (Wed, 23 Mar 2016)

  Changed paths:
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide

The add.f and sub.f to be implemented don't use 64 bit registers
and a general usage of CHECK_REG_PAIR would always generate an
exception for them.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>


  Commit: baf410dccac82f446d83bb10509608f59adbd8ee
      
https://github.com/qemu/qemu/commit/baf410dccac82f446d83bb10509608f59adbd8ee
  Author: Bastian Koppelmann <address@hidden>
  Date:   2016-03-23 (Wed, 23 Mar 2016)

  Changed paths:
    M target-tricore/fpu_helper.c
    M target-tricore/helper.h
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: add add.f/sub.f instructions

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>


  Commit: daab3f7fa8c9b29ed6dff9160a6a87e0ea09d705
      
https://github.com/qemu/qemu/commit/daab3f7fa8c9b29ed6dff9160a6a87e0ea09d705
  Author: Bastian Koppelmann <address@hidden>
  Date:   2016-03-23 (Wed, 23 Mar 2016)

  Changed paths:
    M target-tricore/fpu_helper.c
    M target-tricore/helper.h
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Add mul.f instruction

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>


  Commit: 446ee5b2a86766bc5cc9d23a106f364bd8ce01b4
      
https://github.com/qemu/qemu/commit/446ee5b2a86766bc5cc9d23a106f364bd8ce01b4
  Author: Bastian Koppelmann <address@hidden>
  Date:   2016-03-23 (Wed, 23 Mar 2016)

  Changed paths:
    M target-tricore/fpu_helper.c
    M target-tricore/helper.h
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Add div.f instruction

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>


  Commit: 743cd09dd7775aaffb7f57444bef0d052bed9691
      
https://github.com/qemu/qemu/commit/743cd09dd7775aaffb7f57444bef0d052bed9691
  Author: Bastian Koppelmann <address@hidden>
  Date:   2016-03-23 (Wed, 23 Mar 2016)

  Changed paths:
    M target-tricore/fpu_helper.c
    M target-tricore/helper.h
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Add cmp.f instruction

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>


  Commit: 0d4c3b8010320a8ebb4061d88510e082b06ed2cc
      
https://github.com/qemu/qemu/commit/0d4c3b8010320a8ebb4061d88510e082b06ed2cc
  Author: Bastian Koppelmann <address@hidden>
  Date:   2016-03-23 (Wed, 23 Mar 2016)

  Changed paths:
    M target-tricore/fpu_helper.c
    M target-tricore/helper.h
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Add ftoi and itof instructions

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>


  Commit: a2ecc80db5078dd98b60a7d03af9a4da3e1bad25
      
https://github.com/qemu/qemu/commit/a2ecc80db5078dd98b60a7d03af9a4da3e1bad25
  Author: Peter Maydell <address@hidden>
  Date:   2016-03-24 (Thu, 24 Mar 2016)

  Changed paths:
    M fpu/softfloat-specialize.h
    M target-tricore/Makefile.objs
    M target-tricore/cpu.h
    A target-tricore/fpu_helper.c
    M target-tricore/helper.c
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20160323' 
into staging

TriCore FPU + bugfixes

# gpg: Signature made Wed 23 Mar 2016 08:26:03 GMT using RSA key ID 6B69CA14
# gpg: Good signature from "Bastian Koppelmann <address@hidden>"

* remotes/bkoppelmann/tags/pull-tricore-20160323:
  target-tricore: Add ftoi and itof instructions
  target-tricore: Add cmp.f instruction
  target-tricore: Add div.f instruction
  target-tricore: Add mul.f instruction
  target-tricore: add add.f/sub.f instructions
  target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide
  target-tricore: Add FPU infrastructure
  target-tricore: Fix psw_read() clearing too many bits
  target-tricore: Fix helper_msub64_q_ssov not reseting OVF bit
  target-tricore: add missing break in insn decode switch stmt

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/2538039f2c26...a2ecc80db507

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