[Qemu-commits] [qemu/qemu] 8b33e8: target-i386: Avoid repeated calls to the bnd_jmp h...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 8b33e82b863d1c6fce7e69a41f6c96a8e15b73fb
      
https://github.com/qemu/qemu/commit/8b33e82b863d1c6fce7e69a41f6c96a8e15b73fb
  Author: Paolo Bonzini <address@hidden>
  Date:   2016-03-14 (Mon, 14 Mar 2016)

  Changed paths:
    M target-i386/translate.c

  Log Message:
  -----------
  target-i386: Avoid repeated calls to the bnd_jmp helper

Two flags were tested the wrong way.

Tested-by: Hervé Poussineau <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
[rth: Fixed enable test as well.]


  Commit: 880f8486503b32a29b653a3c0b3cfc5432012f38
      
https://github.com/qemu/qemu/commit/880f8486503b32a29b653a3c0b3cfc5432012f38
  Author: Paolo Bonzini <address@hidden>
  Date:   2016-03-14 (Mon, 14 Mar 2016)

  Changed paths:
    M target-i386/translate.c

  Log Message:
  -----------
  target-i386: Fix SMSW and LMSW from/to register

SMSW and LMSW accept register operands, but commit 1906b2a ("target-i386:
Rearrange processing of 0F 01", 2016-02-13) did not account for that.

Fixes: 1906b2af7c2345037d9b2fdf484b457b5acd09d1
Reported-by: Hervé Poussineau <address@hidden>
Tested-by: Hervé Poussineau <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: a657f79e32422634415c09f3f15c73d610297af5
      
https://github.com/qemu/qemu/commit/a657f79e32422634415c09f3f15c73d610297af5
  Author: Richard Henderson <address@hidden>
  Date:   2016-03-14 (Mon, 14 Mar 2016)

  Changed paths:
    M target-i386/translate.c

  Log Message:
  -----------
  target-i386: Fix SMSW for 64-bit mode

In non-64-bit modes, the instruction always stores 16 bits.
But in 64-bit mode, when the destination is a register, the
instruction can write 32 or 64 bits.

Tested-by: Hervé Poussineau <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: e2e02a820741ec4d96b8f313b06a2a7ed5e94fbd
      
https://github.com/qemu/qemu/commit/e2e02a820741ec4d96b8f313b06a2a7ed5e94fbd
  Author: Paolo Bonzini <address@hidden>
  Date:   2016-03-14 (Mon, 14 Mar 2016)

  Changed paths:
    M target-i386/translate.c

  Log Message:
  -----------
  target-i386: Fix addr16 prefix

While ADDSEG will only be false in 16-bit mode for LEA, it can be
false even in other cases when 16-bit addresses are obtained via
the 67h prefix in 32-bit mode.  In this case, gen_lea_v_seg forgets
to add a nonzero FS or GS base if CS/DS/ES/SS are all zero.  This
case is pretty rare but happens when booting Windows 95/98, and
this patch fixes it.

The bug is visible since commit d6a291498, but it was introduced
together with gen_lea_v_seg and it probably could be reproduced
with a "addr16 gs movsb" instruction as early as in commit
ca2f29f555805d07fb0b9ebfbbfc4e3656530977.

Reported-by: Hervé Poussineau <address@hidden>
Tested-by: Hervé Poussineau <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 26317698ef3be5942c5ee5630997dbc98431c5f6
      
https://github.com/qemu/qemu/commit/26317698ef3be5942c5ee5630997dbc98431c5f6
  Author: Richard Henderson <address@hidden>
  Date:   2016-03-14 (Mon, 14 Mar 2016)

  Changed paths:
    M target-i386/translate.c

  Log Message:
  -----------
  target-i386: Use gen_nop_modrm for prefetch instructions

Tested-by: Hervé Poussineau <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: f083d92c03e7a0741d2a9eba774a60d5a3ca772f
      
https://github.com/qemu/qemu/commit/f083d92c03e7a0741d2a9eba774a60d5a3ca772f
  Author: Richard Henderson <address@hidden>
  Date:   2016-03-14 (Mon, 14 Mar 2016)

  Changed paths:
    M target-i386/translate.c

  Log Message:
  -----------
  target-i386: Fix inhibit irq mask handling

The patch in 7f0b714 was too simplistic, in that we wound up setting
the flag and then resetting it immediately in gen_eob.

Fixes the reported boot problem with Windows XP.

Reported-by: Hervé Poussineau <address@hidden>
Tested-by: Hervé Poussineau <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: b9f9c5b41aab06479cb1695990b7cca98ef84fc7
      
https://github.com/qemu/qemu/commit/b9f9c5b41aab06479cb1695990b7cca98ef84fc7
  Author: Richard Henderson <address@hidden>
  Date:   2016-03-14 (Mon, 14 Mar 2016)

  Changed paths:
    M target-i386/translate.c

  Log Message:
  -----------
  target-i386: Dump unknown opcodes with -d unimp

We discriminate here between opcodes that are illegal in the current
cpu mode or with illegal arguments (such as modrm.mod == 3) and
encodings that are unknown (such as an unimplemented isa extension).

Signed-off-by: Richard Henderson <address@hidden>


  Commit: 9828f9b6c84009ecb07796202317297bdbb8c0ef
      
https://github.com/qemu/qemu/commit/9828f9b6c84009ecb07796202317297bdbb8c0ef
  Author: Peter Maydell <address@hidden>
  Date:   2016-03-15 (Tue, 15 Mar 2016)

  Changed paths:
    M target-i386/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-i386-20160314' into 
staging

target-i386 fixes

# gpg: Signature made Mon 14 Mar 2016 17:54:06 GMT using RSA key ID 4DD0279B
# gpg: Good signature from "Richard Henderson <address@hidden>"
# gpg:                 aka "Richard Henderson <address@hidden>"
# gpg:                 aka "Richard Henderson <address@hidden>"

* remotes/rth/tags/pull-i386-20160314:
  target-i386: Dump unknown opcodes with -d unimp
  target-i386: Fix inhibit irq mask handling
  target-i386: Use gen_nop_modrm for prefetch instructions
  target-i386: Fix addr16 prefix
  target-i386: Fix SMSW for 64-bit mode
  target-i386: Fix SMSW and LMSW from/to register
  target-i386: Avoid repeated calls to the bnd_jmp helper

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/1a8b40816839...9828f9b6c840