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[Qemu-commits] [qemu/qemu] c489e5: mips/kvm: Remove a couple of noisy DP

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] c489e5: mips/kvm: Remove a couple of noisy DPRINTFs
Date: Fri, 26 Feb 2016 05:30:05 -0800 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: c489e5591ff998204dc4736748b9441514f2cbee
      
https://github.com/qemu/qemu/commit/c489e5591ff998204dc4736748b9441514f2cbee
  Author: James Hogan <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-mips/kvm.c

  Log Message:
  -----------
  mips/kvm: Remove a couple of noisy DPRINTFs

The DPRINTFs in cpu_mips_io_interrupts_pending() and kvm_arch_pre_run()
are particularly noisy during normal execution, and also not
particularly helpful. Remove them so that more important debug messages
can be more easily seen.

Signed-off-by: James Hogan <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 461a1582f0bce00f7a3e1ff714d3a9885ad8b012
      
https://github.com/qemu/qemu/commit/461a1582f0bce00f7a3e1ff714d3a9885ad8b012
  Author: James Hogan <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-mips/kvm.c

  Log Message:
  -----------
  mips/kvm: Implement PRid CP0 register

Implement saving and restoring to KVM state of the Processor ID (PRid)
CP0 register. This allows QEMU to control the PRid exposed to the guest
instead of using the default set by KVM.

Signed-off-by: James Hogan <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 03cbfd7b5cdb00a7dfadf502b5acdeeefd69422c
      
https://github.com/qemu/qemu/commit/03cbfd7b5cdb00a7dfadf502b5acdeeefd69422c
  Author: James Hogan <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-mips/kvm.c

  Log Message:
  -----------
  mips/kvm: Implement Config CP0 registers

Implement saving and restoring to KVM state of the Config CP0 registers
(namely Config, Config1, Config2, Config3, Config4, and Config5). These
control the features available to a guest, and a few of the fields will
soon be writeable by a guest so QEMU needs to know about them so as not
to clobber them on migration/savevm.

Signed-off-by: James Hogan <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Leon Alrae <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 0759487b56369a1f5d82528f9febd1aaa98bad26
      
https://github.com/qemu/qemu/commit/0759487b56369a1f5d82528f9febd1aaa98bad26
  Author: James Hogan <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-mips/kvm.c

  Log Message:
  -----------
  mips/kvm: Support unsigned KVM registers

Add KVM register access functions for the uint32_t type. This is
required for FP and MSA control registers, which are represented as
unsigned 32-bit integers.

Signed-off-by: James Hogan <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Leon Alrae <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: d319f83fe997b919ac3a74fa7a66771c8f4fa3a8
      
https://github.com/qemu/qemu/commit/d319f83fe997b919ac3a74fa7a66771c8f4fa3a8
  Author: James Hogan <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-mips/kvm.c

  Log Message:
  -----------
  mips/kvm: Support signed 64-bit KVM registers

Rename kvm_mips_{get,put}_one_reg64() to kvm_mips_{get,put}_one_ureg64()
since they take an int64_t pointer, and add separate signed 64-bit
accessors. These will be used for double precision floating point
registers.

Signed-off-by: James Hogan <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Leon Alrae <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 152db36ae63c70adc95afc3228f858ef6369519a
      
https://github.com/qemu/qemu/commit/152db36ae63c70adc95afc3228f858ef6369519a
  Author: James Hogan <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-mips/kvm.c

  Log Message:
  -----------
  mips/kvm: Support FPU in MIPS KVM guests

Support the new KVM_CAP_MIPS_FPU capability, which allows the host's FPU
to be exposed to the KVM guest.

The capability is enabled if the guest core has an FPU according to its
Config1 register. Various config bits are now writeable so that KVM is
aware of the configuration (Config1.FP) and so that QEMU can
save/restore the guest modifiable bits (Config5.FRE, Config5.UFR,
Config5.UFE). The FCSR/FIR registers and the floating point registers
are now saved/restored (depending on the FR mode bit).

Signed-off-by: James Hogan <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Leon Alrae <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: bee62662a312b99b4418b558a99b3963a4cbff07
      
https://github.com/qemu/qemu/commit/bee62662a312b99b4418b558a99b3963a4cbff07
  Author: James Hogan <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-mips/kvm.c

  Log Message:
  -----------
  mips/kvm: Support MSA in MIPS KVM guests

Support the new KVM_CAP_MIPS_MSA capability, which allows MIPS SIMD
Architecture (MSA) to be exposed to the KVM guest.

The capability is enabled if the guest core has MSA according to its
Config3 register. Various config bits are now writeable so that KVM is
aware of the configuration (Config3.MSAP) and so that QEMU can
save/restore the guest modifiable bits (Config5.MSAEn). The MSACSR/MSAIR
registers and the MSA vector registers are now saved/restored. Since the
FP registers are a subset of the vector registers, they are omitted if
the guest has MSA.

Signed-off-by: James Hogan <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Leon Alrae <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 01bc435b44b8802cc4697faa07d908684afbce4e
      
https://github.com/qemu/qemu/commit/01bc435b44b8802cc4697faa07d908684afbce4e
  Author: Yongbok Kim <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M disas/mips.c
    M target-mips/cpu.c
    M target-mips/cpu.h
    M target-mips/helper.h
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: implement R6 multi-threading

MIPS Release 6 provides multi-threading features which replace
pre-R6 MT Module. CP0.Config3.MT is always 0 in R6, instead there is new
CP0.Config5.VP (Virtual Processor) bit which indicates presence of
multi-threading support which includes CP0.GlobalNumber register and
DVP/EVP instructions.

Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 4d1e324b2241017c92d816ec3af51a14685dbf62
      
https://github.com/qemu/qemu/commit/4d1e324b2241017c92d816ec3af51a14685dbf62
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M disas/mips.c
    M target-mips/cpu.c
    M target-mips/cpu.h
    M target-mips/helper.h
    M target-mips/kvm.c
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160226' into staging

MIPS patches 2016-02-26

Changes:
* support for FPU and MSA in KVM guest
* support for R6 Virtual Processors

# gpg: Signature made Fri 26 Feb 2016 11:07:37 GMT using RSA key ID 0B29DA6B
# gpg: Good signature from "Leon Alrae <address@hidden>"

* remotes/lalrae/tags/mips-20160226:
  target-mips: implement R6 multi-threading
  mips/kvm: Support MSA in MIPS KVM guests
  mips/kvm: Support FPU in MIPS KVM guests
  mips/kvm: Support signed 64-bit KVM registers
  mips/kvm: Support unsigned KVM registers
  mips/kvm: Implement Config CP0 registers
  mips/kvm: Implement PRid CP0 register
  mips/kvm: Remove a couple of noisy DPRINTFs

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/a88a5cd2e8b9...4d1e324b2241
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