[Qemu-commits] [qemu/qemu] 6b7f0b: target-arm: Fix typo in comment in arm_is_secure_b...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 6b7f0b61f080b886c9b4bba8240379ce90e20b12
      
https://github.com/qemu/qemu/commit/6b7f0b61f080b886c9b4bba8240379ce90e20b12
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-11 (Thu, 11 Feb 2016)

  Changed paths:
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: Fix typo in comment in arm_is_secure_below_el3()

Fix a typo where "EL2" was written but "EL3" intended.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: 5513c3abed8e5fabe116830c63f0d3fe1f94bd21
      
https://github.com/qemu/qemu/commit/5513c3abed8e5fabe116830c63f0d3fe1f94bd21
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-11 (Thu, 11 Feb 2016)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement MDCR_EL3 and SDCR

Implement the MDCR_EL3 register (which is SDCR for AArch32).
For the moment we implement it as reads-as-written.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: efe4a274083f61484a8f1478d93f229d43aa8095
      
https://github.com/qemu/qemu/commit/efe4a274083f61484a8f1478d93f229d43aa8095
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-11 (Thu, 11 Feb 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR

The registers MVBAR and SCR should have the behaviour of trapping to
EL3 if accessed from Secure EL1, but we were incorrectly implementing
them to UNDEF (which would trap to EL1).  Fix this by using the new
access_trap_aa32s_el1() access function.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 533e93f1cf12c570aab45f14663dab6fb8ea3ffc
      
https://github.com/qemu/qemu/commit/533e93f1cf12c570aab45f14663dab6fb8ea3ffc
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-11 (Thu, 11 Feb 2016)

  Changed paths:
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: Update arm_generate_debug_exceptions() to handle EL2/EL3

The arm_generate_debug_exceptions() function as originally implemented
assumes no EL2 or EL3. Since we now have much more of an implementation
of those now, fix this assumption.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: 3f208fd76bcc91a8506681bb8472f2398fe6f487
      
https://github.com/qemu/qemu/commit/3f208fd76bcc91a8506681bb8472f2398fe6f487
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-11 (Thu, 11 Feb 2016)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/helper.h
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Add isread parameter to CPAccessFns

System registers might have access requirements which need to
be described via a CPAccessFn and which differ for reads and
writes. For this to be possible we need to pass the access
function a parameter to tell it whether the access being checked
is a read or a write.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: 2f027fc52d4b444a47cb05a9c96697372a6b57d2
      
https://github.com/qemu/qemu/commit/2f027fc52d4b444a47cb05a9c96697372a6b57d2
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-11 (Thu, 11 Feb 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement NSACR trapping behaviour

Implement some corner cases of the behaviour of the NSACR
register on ARMv8:
 * if EL3 is AArch64 then accessing the NSACR from Secure EL1
   with AArch32 should trap to EL3
 * if EL3 is not present or is AArch64 then reads from NS EL1 and
   NS EL2 return constant 0xc00

It would in theory be possible to implement all these with
a single reginfo definition, but for clarity we use three
separate definitions for the three cases and install the
right one based on the CPU feature flags.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 3ad901bc2b98f5539af9a7d4aef140a6d8fa6442
      
https://github.com/qemu/qemu/commit/3ad901bc2b98f5539af9a7d4aef140a6d8fa6442
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-11 (Thu, 11 Feb 2016)

  Changed paths:
    M target-arm/cpu64.c

  Log Message:
  -----------
  target-arm: Enable EL3 for Cortex-A53 and Cortex-A57

Enable EL3 support for our Cortex-A53 and Cortex-A57 CPU models.
We have enough implemented now to be able to run real world code
at least to some extent (I can boot ARM Trusted Firmware to the
point where it pulls in OP-TEE and then falls over because it
doesn't have a UEFI image it can chain to).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: fc05f4a62c568b607ec3fe428a419bb38205b570
      
https://github.com/qemu/qemu/commit/fc05f4a62c568b607ec3fe428a419bb38205b570
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-11 (Thu, 11 Feb 2016)

  Changed paths:
    M target-arm/internals.h

  Log Message:
  -----------
  target-arm: Correct misleading 'is_thumb' syn_* parameter names

In syndrome register values, the IL bit indicates the instruction
length, and is 1 for 4-byte instructions and 0 for 2-byte
instructions. All A64 and A32 instructions are 4-byte, but
Thumb instructions may be either 2 or 4 bytes long. Unfortunately
we named the parameter to the syn_* functions for constructing
syndromes "is_thumb", which falsely implies that it should be
set for all Thumb instructions, rather than only the 16-bit ones.
Fix the functions to name the parameter 'is_16bit' instead.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: 4df322593037d2700f72dfdfb967300b7ad2e696
      
https://github.com/qemu/qemu/commit/4df322593037d2700f72dfdfb967300b7ad2e696
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-11 (Thu, 11 Feb 2016)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Fix IL bit reported for Thumb coprocessor traps

All Thumb coprocessor instructions are 32 bits, so the IL
bit in the syndrome register should be set. Pass false to the
syn_* function's is_16bit argument rather than s->thumb
so we report the correct IL bit.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: 7d197d2db5e99e4c8b20f6771ddc7303acaa1c89
      
https://github.com/qemu/qemu/commit/7d197d2db5e99e4c8b20f6771ddc7303acaa1c89
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-11 (Thu, 11 Feb 2016)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Fix IL bit reported for Thumb VFP and Neon traps

All Thumb Neon and VFP instructions are 32 bits, so the IL
bit in the syndrome register should be set. Pass false to the
syn_* function's is_16bit argument rather than s->thumb
so we report the correct IL bit.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: 568496c0c0f1863a4bc18539962cd8d81baa4e30
      
https://github.com/qemu/qemu/commit/568496c0c0f1863a4bc18539962cd8d81baa4e30
  Author: Sergey Fedorov <address@hidden>
  Date:   2016-02-11 (Thu, 11 Feb 2016)

  Changed paths:
    M exec.c
    M include/qom/cpu.h
    M qom/cpu.c

  Log Message:
  -----------
  cpu: Add callback to check architectural watchpoint match

When QEMU watchpoint matches, that is not definitely an architectural
watchpoint match yet. If it is a stop-before-access watchpoint then that
is hardly possible to ignore it after throwing a TCG exception.

A special callback is introduced to check for architectural watchpoint
match before raising a TCG exception.

Signed-off-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3826121d9298cde1d29ead05910e1f40125ee9b0
      
https://github.com/qemu/qemu/commit/3826121d9298cde1d29ead05910e1f40125ee9b0
  Author: Sergey Fedorov <address@hidden>
  Date:   2016-02-11 (Thu, 11 Feb 2016)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/internals.h
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Implement checking of fired watchpoint

ARM stops before access to a location covered by watchpoint. Also, QEMU
watchpoint fire is not necessarily an architectural watchpoint match.
Unfortunately, that is hardly possible to ignore a fired watchpoint in
debug exception handler. So move watchpoint check from debug exception
handler to the dedicated watchpoint checking callback.

Signed-off-by: Sergey Fedorov <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 97f4ed3b71cca015e82bb601a17cd816b83fff05
      
https://github.com/qemu/qemu/commit/97f4ed3b71cca015e82bb601a17cd816b83fff05
  Author: Prasad J Pandit <address@hidden>
  Date:   2016-02-11 (Thu, 11 Feb 2016)

  Changed paths:
    M hw/sd/sd.c

  Log Message:
  -----------
  sd: limit 'req.cmd' while using as an array index

While processing standard SD commands, the 'req.cmd' value could
lead to OOB read when used as an index into 'sd_cmd_type' or
'sd_cmd_class' arrays. Limit 'req.cmd' value to avoid such an
access.

Reported-by: Qinghao Tang <address@hidden>
Signed-off-by: Prasad J Pandit <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7ea686f5dda7cb9a5425fab716ce41260eeecf15
      
https://github.com/qemu/qemu/commit/7ea686f5dda7cb9a5425fab716ce41260eeecf15
  Author: Andrew Jones <address@hidden>
  Date:   2016-02-11 (Thu, 11 Feb 2016)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: fix max-cpus check

mach-virt doesn't yet support hotplug, but command lines specifying
-smp <num>,maxcpus=<bigger-num> don't fail. Of course specifying
bigger-num as something bigger than the machine supports, e.g. > 8
on a gicv2 machine, should fail though. This fix also makes mach-
virt's max-cpus check truly consistent with the one in vl.c:main,
as the one there was already correctly checking max-cpus instead
of smp-cpus.

Reported-by: Shannon Zhao <address@hidden>
Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f0afa73164778570083504a185d7498884c68d65
      
https://github.com/qemu/qemu/commit/f0afa73164778570083504a185d7498884c68d65
  Author: Stephen Warren <address@hidden>
  Date:   2016-02-11 (Thu, 11 Feb 2016)

  Changed paths:
    M hw/arm/bcm2835_peripherals.c
    M hw/arm/bcm2836.c
    M hw/arm/raspi.c
    M hw/misc/bcm2835_property.c
    M include/hw/misc/bcm2835_property.h

  Log Message:
  -----------
  bcm2835_property: implement "get board revision" query

Return a valid value from the BCM2835 property mailbox query "get board
revision". This query is used by U-Boot. Implementing it fixes the first
obvious difference between qemu and real HW.

The value returned is currently hard-coded to match the RPi2 I own. Other
values are legal, e.g. different board manufacturer field values are
likely to exist in the wild.

Cc: Andrew Baumann <address@hidden>
Signed-off-by: Stephen Warren <address@hidden>
Reviewed-by: Andrew Baumann <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 36a9abd9be2f85c07e93378a5c5d1b180f5b2e15
      
https://github.com/qemu/qemu/commit/36a9abd9be2f85c07e93378a5c5d1b180f5b2e15
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-11 (Thu, 11 Feb 2016)

  Changed paths:
    M exec.c
    M hw/arm/bcm2835_peripherals.c
    M hw/arm/bcm2836.c
    M hw/arm/raspi.c
    M hw/arm/virt.c
    M hw/misc/bcm2835_property.c
    M hw/sd/sd.c
    M include/hw/misc/bcm2835_property.h
    M include/qom/cpu.h
    M qom/cpu.c
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/cpu64.c
    M target-arm/helper.c
    M target-arm/helper.h
    M target-arm/internals.h
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160211' 
into staging

target-arm queue:
 * fix some missing traps for EL3 support
 * enable EL3 on Cortex-A53 and Cortex-A57
 * fix syndrome IL bit for Thumb coprocessor, VFP and Neon traps
 * fix mishandling of architectural watchpoints
 * avoid buffer overflow in sd.c
 * fix max-cpus check in virt board
 * implement 'get board revision' query for BCM2835

# gpg: Signature made Thu 11 Feb 2016 11:23:47 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20160211:
  bcm2835_property: implement "get board revision" query
  hw/arm/virt: fix max-cpus check
  sd: limit 'req.cmd' while using as an array index
  target-arm: Implement checking of fired watchpoint
  cpu: Add callback to check architectural watchpoint match
  target-arm: Fix IL bit reported for Thumb VFP and Neon traps
  target-arm: Fix IL bit reported for Thumb coprocessor traps
  target-arm: Correct misleading 'is_thumb' syn_* parameter names
  target-arm: Enable EL3 for Cortex-A53 and Cortex-A57
  target-arm: Implement NSACR trapping behaviour
  target-arm: Add isread parameter to CPAccessFns
  target-arm: Update arm_generate_debug_exceptions() to handle EL2/EL3
  target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR
  target-arm: Implement MDCR_EL3 and SDCR
  target-arm: Fix typo in comment in arm_is_secure_below_el3()

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/88c73d16ad1b...36a9abd9be2f