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[Qemu-commits] [qemu/qemu] f698c8: qdev: get_child_bus(): Use QOM lookup


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] f698c8: qdev: get_child_bus(): Use QOM lookup if available
Date: Thu, 21 Jan 2016 08:00:05 -0800

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: f698c8ba48809454ba4a28fe3eb6f677943cd1ae
      
https://github.com/qemu/qemu/commit/f698c8ba48809454ba4a28fe3eb6f677943cd1ae
  Author: Peter Crosthwaite <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M hw/core/qdev.c

  Log Message:
  -----------
  qdev: get_child_bus(): Use QOM lookup if available

qbus_realize() adds busses as a QOM child of the device in addition to
adding it to the qdev bus list. Change get_child_bus() to use the QOM
child if it is available. This takes priority over the bus-list, but
the child object is checked for type correctness.

This prepares support for aliasing of buses. The use case is SoCs,
where a SoC container needs to present buses to the board level, but
the buses are implemented by controller IP we already model as self
contained qbus-containing devices.

Signed-off-by: Peter Crosthwaite <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d857c4c0235f2e891850b0d08b5a1a48d18bf8bf
      
https://github.com/qemu/qemu/commit/d857c4c0235f2e891850b0d08b5a1a48d18bf8bf
  Author: Alistair Francis <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  m25p80.c: Add sst25wf080 SPI flash device

Add the sst25wf080 SPI flash device.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8fd06719e7d37f91f1b843af4cdcdfe7eb3e4a69
      
https://github.com/qemu/qemu/commit/8fd06719e7d37f91f1b843af4cdcdfe7eb3e4a69
  Author: Alistair Francis <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M hw/arm/pxa2xx.c
    M hw/arm/spitz.c
    M hw/arm/stellaris.c
    M hw/arm/strongarm.c
    M hw/arm/tosa.c
    M hw/arm/xilinx_zynq.c
    M hw/arm/z2.c
    M hw/block/m25p80.c
    M hw/display/ads7846.c
    M hw/display/ssd0323.c
    M hw/microblaze/petalogix_ml605_mmu.c
    M hw/misc/max111x.c
    M hw/sd/ssi-sd.c
    M hw/ssi/pl022.c
    M hw/ssi/ssi.c
    M hw/ssi/xilinx_spi.c
    M hw/ssi/xilinx_spips.c
    R include/hw/ssi.h
    A include/hw/ssi/ssi.h

  Log Message:
  -----------
  ssi: Move ssi.h into a separate directory

Move the ssi.h include file into the ssi directory.

While touching the code also fix the typdef lines as
checkpatch complains.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6363235b2bd49d31a04c0229ae95e5f415c52a54
      
https://github.com/qemu/qemu/commit/6363235b2bd49d31a04c0229ae95e5f415c52a54
  Author: Alistair Francis <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M hw/ssi/xilinx_spips.c
    A include/hw/ssi/xilinx_spips.h

  Log Message:
  -----------
  xilinx_spips: Separate the state struct into a header

Separate out the XilinxSPIPS struct into a separate header
file.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 02d07eb49436aec8bd13b4ac7c63d9ca3f1c6e6c
      
https://github.com/qemu/qemu/commit/02d07eb49436aec8bd13b4ac7c63d9ca3f1c6e6c
  Author: Alistair Francis <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  xlnx-zynqmp: Connect the SPI devices

Connect the Xilinx SPI devices to the ZynqMP model.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
[ PC changes
 * Use QOM alias for bus connectivity on SoC level
]
Signed-off-by: Peter Crosthwaite <address@hidden>
[PMM: free the g_strdup_printf() string when finished with it]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a4b26335c8c2b513ee9383837704f264e0b8d83f
      
https://github.com/qemu/qemu/commit/a4b26335c8c2b513ee9383837704f264e0b8d83f
  Author: Alistair Francis <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M hw/arm/xlnx-ep108.c

  Log Message:
  -----------
  xlnx-ep108: Connect the SPI Flash

Connect the sst25wf080 SPI flash to the EP108 board.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
[PMM: free string when finished with it]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4a94fc9bf2dac5965acb8e264d55a356737a2aa6
      
https://github.com/qemu/qemu/commit/4a94fc9bf2dac5965acb8e264d55a356737a2aa6
  Author: Peter Crosthwaite <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M hw/misc/zynq-xadc.c

  Log Message:
  -----------
  misc: zynq-xadc: Fix off-by-one

This bounds check was off-by-one. Fix.

Reported-by: Paolo Bonzini <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 56943e8cc14b7eeeab67d1942fa5d8bcafe3e53f
      
https://github.com/qemu/qemu/commit/56943e8cc14b7eeeab67d1942fa5d8bcafe3e53f
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M cpus.c
    M exec.c
    M include/exec/exec-all.h
    M target-i386/cpu.c

  Log Message:
  -----------
  exec.c: Don't set cpu->as until cpu_address_space_init

Rather than setting cpu->as unconditionally in cpu_exec_init
(and then having target-i386 override this later), don't set
it until the first call to cpu_address_space_init.

This requires us to initialise the address space for
both TCG and KVM (KVM doesn't need the AS listener but
it does require cpu->as to be set).

For target CPUs which don't set up any address spaces (currently
everything except i386), add the default address_space_memory
in qemu_init_vcpu().

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>


  Commit: 12ebc9a76dd7702aef0a3618717a826c19c34ef4
      
https://github.com/qemu/qemu/commit/12ebc9a76dd7702aef0a3618717a826c19c34ef4
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M cpus.c
    M exec.c
    M include/exec/exec-all.h
    M include/qom/cpu.h
    M target-i386/cpu.c

  Log Message:
  -----------
  exec.c: Allow target CPUs to define multiple AddressSpaces

Allow multiple calls to cpu_address_space_init(); each
call adds an entry to the cpu->ases array at the specified
index. It is up to the target-specific CPU code to actually use
these extra address spaces.

Since this multiple AddressSpace support won't work with
KVM, add an assertion to avoid confusing failures.

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>


  Commit: 1787cc8ee55143b6071c87e59f08d56e7c22c1eb
      
https://github.com/qemu/qemu/commit/1787cc8ee55143b6071c87e59f08d56e7c22c1eb
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M include/exec/exec-all.h

  Log Message:
  -----------
  exec-all.h: Document tlb_set_page_with_attrs, tlb_set_page

Add documentation comments for tlb_set_page_with_attrs()
and tlb_set_page().

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>


  Commit: 1dc6fb1f5cc5cea5ba01010a19c6acefd0ae4b73
      
https://github.com/qemu/qemu/commit/1dc6fb1f5cc5cea5ba01010a19c6acefd0ae4b73
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M include/qom/cpu.h

  Log Message:
  -----------
  cpu: Add new get_phys_page_attrs_debug() method

Add a new optional method get_phys_page_attrs_debug() to CPUClass.
This is like the existing get_phys_page_debug(), but also returns
the memory transaction attributes to use for the access.
This will be necessary for CPUs which have multiple address
spaces and use the attributes to select the correct address
space.

We provide a wrapper function cpu_get_phys_page_attrs_debug()
which falls back to the existing get_phys_page_debug(), so we
don't need to change every target CPU.

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>


  Commit: d7f25a9e6a6b2c69a0be6033903b7d6087bcf47d
      
https://github.com/qemu/qemu/commit/d7f25a9e6a6b2c69a0be6033903b7d6087bcf47d
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M include/qom/cpu.h

  Log Message:
  -----------
  cpu: Add new asidx_from_attrs() method

Add a new method to CPUClass which the memory system core can
use to obtain the correct address space index to use for a memory
access with a given set of transaction attributes, together
with the wrapper function cpu_asidx_from_attrs() which implements
the default behaviour ("always use asidx 0") for CPU classes
which don't provide the method.

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>


  Commit: d7898cda81b6efa6b2d7a749882695cdcf280eaa
      
https://github.com/qemu/qemu/commit/d7898cda81b6efa6b2d7a749882695cdcf280eaa
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M cputlb.c
    M exec.c
    M include/exec/exec-all.h

  Log Message:
  -----------
  cputlb.c: Use correct address space when looking up MemoryRegionSection

When looking up the MemoryRegionSection for the new TLB entry in
tlb_set_page_with_attrs(), use cpu_asidx_from_attrs() to determine
the correct address space index for the lookup, and pass it into
address_space_translate_for_iotlb().

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>


  Commit: a54c87b68a0410d0cf6f8b84e42074a5cf463732
      
https://github.com/qemu/qemu/commit/a54c87b68a0410d0cf6f8b84e42074a5cf463732
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M cputlb.c
    M exec.c
    M include/exec/exec-all.h
    M softmmu_template.h

  Log Message:
  -----------
  exec.c: Pass MemTxAttrs to iotlb_to_region so it uses the right AS

Pass the MemTxAttrs for the memory access to iotlb_to_region(); this
allows it to determine the correct AddressSpace to use for the lookup.

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>


  Commit: 651a5bc03705102de519ebf079a40ecc1da991db
      
https://github.com/qemu/qemu/commit/651a5bc03705102de519ebf079a40ecc1da991db
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M exec.c
    M include/exec/exec-all.h

  Log Message:
  -----------
  exec.c: Add cpu_get_address_space()

Add a function to return the AddressSpace for a CPU based on
its numerical index. (Callers outside exec.c don't have access
to the CPUAddressSpace struct so can't just fish it out of the
CPUState struct directly.)

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>


  Commit: 5232e4c798ba7a46261d3157b73d08fc598e7dcb
      
https://github.com/qemu/qemu/commit/5232e4c798ba7a46261d3157b73d08fc598e7dcb
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M exec.c

  Log Message:
  -----------
  exec.c: Use cpu_get_phys_page_attrs_debug

Use cpu_get_phys_page_attrs_debug() when doing virtual-to-physical
conversions in debug related code, so that we can obtain the right
address space index and thus select the correct AddressSpace,
rather than always using cpu->as.

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>


  Commit: 79ed0416477440ccb6acf136d6808a4f5848bbdf
      
https://github.com/qemu/qemu/commit/79ed0416477440ccb6acf136d6808a4f5848bbdf
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M exec.c

  Log Message:
  -----------
  exec.c: Use correct AddressSpace in watch_mem_read and watch_mem_write

In the watchpoint access routines watch_mem_read and watch_mem_write,
find the correct AddressSpace to use from current_cpu and the memory
transaction attributes, rather than always assuming address_space_memory.

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>


  Commit: f0c02d15b57da6f5463e3768aa0cfeedccf4b8f4
      
https://github.com/qemu/qemu/commit/f0c02d15b57da6f5463e3768aa0cfeedccf4b8f4
  Author: Peter Crosthwaite <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M include/exec/memory.h
    M memory.c

  Log Message:
  -----------
  memory: Add address_space_init_shareable()

This will either create a new AS or return a pointer to an
already existing equivalent one, if we have already created
an AS for the specified root memory region.

The motivation is to reuse address spaces as much as possible.
It's going to be quite common that bus masters out in device land
have pointers to the same memory region for their mastering yet
each will need to create its own address space. Let the memory
API implement sharing for them.

Aside from the perf optimisations, this should reduce the amount
of redundant output on info mtree as well.

Thee returned value will be malloced, but the malloc will be
automatically freed when the AS runs out of refs.

Signed-off-by: Peter Crosthwaite <address@hidden>
[PMM: dropped check for NULL root as unused; added doc-comment;
 squashed Peter C's reference-counting patch into this one;
 don't compare name string when deciding if we can share ASes;
 read as->malloced before the unref of as->root to avoid possible
 read-after-free if as->root was the owner of as]
Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>


  Commit: 6731d864f80938e404dc3e5eb7f6b76b891e3e43
      
https://github.com/qemu/qemu/commit/6731d864f80938e404dc3e5eb7f6b76b891e3e43
  Author: Peter Crosthwaite <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M cpus.c
    M exec.c
    M include/qom/cpu.h

  Log Message:
  -----------
  qom/cpu: Add MemoryRegion property

Add a MemoryRegion property, which if set is used to construct
the CPU's initial (default) AddressSpace.

Signed-off-by: Peter Crosthwaite <address@hidden>
[PMM: code is moved from qom/cpu.c to exec.c to avoid having to
 make qom/cpu.o be a non-common object file; code to use the
 MemoryRegion and to default it to system_memory added.]
Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>


  Commit: 9e273ef2174d7cd5b14a16d8638812541d3eb6bb
      
https://github.com/qemu/qemu/commit/9e273ef2174d7cd5b14a16d8638812541d3eb6bb
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: Add QOM property for Secure memory region

Add QOM property to the ARM CPU which boards can use to tell us what
memory region to use for secure accesses. Nonsecure accesses
go via the memory region specified with the base CPU class 'memory'
property.

By default, if no secure region is specified it is the same as the
nonsecure region, and if no nonsecure region is specified we will use
address_space_memory.

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>


  Commit: 017518c1f6ed9939c7f390cb91078f0919b5494c
      
https://github.com/qemu/qemu/commit/017518c1f6ed9939c7f390cb91078f0919b5494c
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: Implement asidx_from_attrs

Implement the asidx_from_attrs CPU method to return the
Secure or NonSecure address space as appropriate.

(The function is inline so we can use it directly in target-arm
code to be added in later patches.)

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>


  Commit: 0faea0c7e6b729c64035b3591b184eeeeef6f1d4
      
https://github.com/qemu/qemu/commit/0faea0c7e6b729c64035b3591b184eeeeef6f1d4
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement cpu_get_phys_page_attrs_debug

Implement cpu_get_phys_page_attrs_debug instead of cpu_get_phys_page_debug.

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>


  Commit: 5ce4ff6502fc6ae01a30c3917996c6c41be1d176
      
https://github.com/qemu/qemu/commit/5ce4ff6502fc6ae01a30c3917996c6c41be1d176
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Support multiple address spaces in page table walks

If we have a secure address space, use it in page table walks:
when doing the physical accesses to read descriptors, make them
through the correct address space.

(The descriptor reads are the only direct physical accesses
made in target-arm/ for CPUs which might have TrustZone.)

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>


  Commit: 1d939a68afe1673441250b495ed2e5f9b568a2fb
      
https://github.com/qemu/qemu/commit/1d939a68afe1673441250b495ed2e5f9b568a2fb
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Wire up memory region to CPUs explicitly

Wire up the system memory region to the CPUs explicitly
by setting the QOM property. This doesn't change anything
over letting it default, but will be needed for adding
a secure memory region later.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>


  Commit: 3df708eb48180fcf11956b81fd6a036cd13ed5f1
      
https://github.com/qemu/qemu/commit/3df708eb48180fcf11956b81fd6a036cd13ed5f1
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M hw/arm/virt.c
    M include/hw/arm/virt.h

  Log Message:
  -----------
  hw/arm/virt: add secure memory region and UART

Add a secure memory region to the virt board, which is the
same as the nonsecure memory region except that it also has
a secure-only UART in it. This is only created if the
board is started with the '-machine secure=on' property.

Signed-off-by: Peter Maydell <address@hidden>

Acked-by: Edgar E. Iglesias <address@hidden>


  Commit: caa49adbccffb7d50cdd8d0faf0d88647901998b
      
https://github.com/qemu/qemu/commit/caa49adbccffb7d50cdd8d0faf0d88647901998b
  Author: Christoffer Dall <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Add always-on property to the virt board timer

The virt board has an arch timer, which is always on.  Emit the
"always-on" property to indicate to Linux that it can switch off the
periodic timer and reduces the amount of interrupts injected into a
guest.

Signed-off-by: Christoffer Dall <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3355c360534321f81d25afb1aeaab15ab6e43be8
      
https://github.com/qemu/qemu/commit/3355c360534321f81d25afb1aeaab15ab6e43be8
  Author: Alistair Francis <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M hw/intc/arm_gic.c

  Log Message:
  -----------
  arm_gic: Update ID registers based on revision

Update the GIC ID registers (registers above 0xfe0) based on the GIC
revision instead of using the sames values for all GIC implementations.

Signed-off-by: Alistair Francis <address@hidden>
Tested-by: Sören Brinkmann <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 446c81abf8e0572b8d5d23fe056516ac62af278d
      
https://github.com/qemu/qemu/commit/446c81abf8e0572b8d5d23fe056516ac62af278d
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: Properly support EL2 and EL3 in arm_el_is_aa64()

Support EL2 and EL3 in arm_el_is_aa64() by implementing the
logic for checking the SCR_EL3 and HCR_EL2 register-width bits
as appropriate to determine the register width of lower exception
levels.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: f3a9b6945cbbb23f3a70da14e9ffdf1e60c580a8
      
https://github.com/qemu/qemu/commit/f3a9b6945cbbb23f3a70da14e9ffdf1e60c580a8
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/helper-a64.c
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Move aarch64_cpu_do_interrupt() to helper.c

Move the aarch64_cpu_do_interrupt() function to helper.c. We want
to be able to call this from code that isn't AArch64-only, and
the move allows us to avoid awkward #ifdeffery at the callsite.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 966f758c49ff478c4757efa5970ce649161bff92
      
https://github.com/qemu/qemu/commit/966f758c49ff478c4757efa5970ce649161bff92
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/cpu64.c
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Use a single entry point for AArch64 and AArch32 exceptions

If EL2 or EL3 is present on an AArch64 CPU, then exceptions can be
taken to an exception level which is running AArch32 (if only EL0
and EL1 are present then EL1 must be AArch64 and all exceptions are
taken to AArch64). To support this we need to have a single
implementation of the CPU do_interrupt() method which can handle both
32 and 64 bit exception entry.

Pull the common parts of aarch64_cpu_do_interrupt() and
arm_cpu_do_interrupt() out into a new function which calls
either the AArch32 or AArch64 specific entry code once it has
worked out which one is needed.

We temporarily special-case the handling of EXCP_SEMIHOST to
avoid an assertion in arm_el_is_aa64(); the next patch will
pull all the semihosting handling out to the arm_cpu_do_interrupt()
level (since semihosting semantics depend on the register width
of the calling code, not on that of any higher EL).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 904c04de2e1b425e7bc8c4ce2fae3d652eeed242
      
https://github.com/qemu/qemu/commit/904c04de2e1b425e7bc8c4ce2fae3d652eeed242
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Pull semihosting handling out to arm_cpu_do_interrupt()

Handling of semihosting calls should depend on the register width
of the calling code, not on that of any higher exception level,
so we need to identify and handle semihosting calls before we
decide whether to deliver the exception as an entry to AArch32
or AArch64. (EXCP_SEMIHOST is also an "internal exception" so
it has no target exception level in the first place.)

This will allow AArch32 EL1 code to use semihosting calls when
running under an AArch64 EL3.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3d6f761713745dfed7d2ccfe98077d213a6a6eba
      
https://github.com/qemu/qemu/commit/3d6f761713745dfed7d2ccfe98077d213a6a6eba
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target

The entry offset when taking an exception to AArch64 from a lower
exception level may be 0x400 or 0x600. 0x400 is used if the
implemented exception level immediately lower than the target level
is using AArch64, and 0x600 if it is using AArch32. We were
incorrectly implementing this as checking the exception level
that the exception was taken from. (The two can be different if
for example we take an exception from EL0 to AArch64 EL3; we should
in this case be checking EL2 if EL2 is implemented, and EL1 if
EL2 is not implemented.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 3809951bf61605974b91578c582de4da28f8ed07
      
https://github.com/qemu/qemu/commit/3809951bf61605974b91578c582de4da28f8ed07
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Handle exception return from AArch64 to non-EL0 AArch32

Remove the assumptions that the AArch64 exception return code was
making about a return to AArch32 always being a return to EL0.
This includes pulling out the illegal-SPSR checks so we can apply
them for return to 32 bit as well as return to 64-bit.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: e393f339af87da7210f6c86902b321df6a2e8bf5
      
https://github.com/qemu/qemu/commit/e393f339af87da7210f6c86902b321df6a2e8bf5
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Implement remaining illegal return event checks

We already implement almost all the checks for the illegal
return events from AArch64 state described in the ARM ARM section
D1.11.2. Add the two missing ones:
 * return to EL2 when EL3 is implemented and SCR_EL3.NS is 0
 * return to Non-secure EL1 when EL2 is implemented and HCR_EL2.TGE is 1

(We don't implement external debug, so the case of "debug state exit
from EL0 using AArch64 state to EL0 using AArch32 state" doesn't apply
for QEMU.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: c1e0371442bf3a7e42ad53c2a3d816ed7099f81d
      
https://github.com/qemu/qemu/commit/c1e0371442bf3a7e42ad53c2a3d816ed7099f81d
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode

The architecture requires that for an exception return to AArch32 the
low bits of ELR_ELx are ignored when the PC is set from them:
 * if returning to Thumb mode, ignore ELR_ELx[0]
 * if returning to ARM mode, ignore ELR_ELx[1:0]

We were only squashing bit 0; also squash bit 1 if the SPSR T bit
indicates this is a return to ARM code.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 03fbf20f4da58f41998dc10ec7542f65d37ba759
      
https://github.com/qemu/qemu/commit/03fbf20f4da58f41998dc10ec7542f65d37ba759
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement FPEXC32_EL2 system register

The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3,
and allows those exception levels to read and write the FPEXC
register for a lower exception level that is using AArch32.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: 1a4f446f81c63151efc30f3ce60a749e8a4cf680
      
https://github.com/qemu/qemu/commit/1a4f446f81c63151efc30f3ce60a749e8a4cf680
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-21 (Thu, 21 Jan 2016)

  Changed paths:
    M cpus.c
    M cputlb.c
    M exec.c
    M hw/arm/pxa2xx.c
    M hw/arm/spitz.c
    M hw/arm/stellaris.c
    M hw/arm/strongarm.c
    M hw/arm/tosa.c
    M hw/arm/virt.c
    M hw/arm/xilinx_zynq.c
    M hw/arm/xlnx-ep108.c
    M hw/arm/xlnx-zynqmp.c
    M hw/arm/z2.c
    M hw/block/m25p80.c
    M hw/core/qdev.c
    M hw/display/ads7846.c
    M hw/display/ssd0323.c
    M hw/intc/arm_gic.c
    M hw/microblaze/petalogix_ml605_mmu.c
    M hw/misc/max111x.c
    M hw/misc/zynq-xadc.c
    M hw/sd/ssi-sd.c
    M hw/ssi/pl022.c
    M hw/ssi/ssi.c
    M hw/ssi/xilinx_spi.c
    M hw/ssi/xilinx_spips.c
    M include/exec/exec-all.h
    M include/exec/memory.h
    M include/hw/arm/virt.h
    M include/hw/arm/xlnx-zynqmp.h
    R include/hw/ssi.h
    A include/hw/ssi/ssi.h
    A include/hw/ssi/xilinx_spips.h
    M include/qom/cpu.h
    M memory.c
    M softmmu_template.h
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/cpu64.c
    M target-arm/helper-a64.c
    M target-arm/helper.c
    M target-arm/op_helper.c
    M target-i386/cpu.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160121' 
into staging

target-arm queue:
 * connect SPI devices in Xilinx Zynq platforms
 * multiple-address-space support
 * use multiple-address-space support for ARM TrustZone
 * arm_gic: return correct ID registers for 11MPCore/v1/v2 GICs
 * various fixes for (currently disabled) AArch64 EL2 and EL3 support
 * add 'always-on' property to the virt board timer DT entry

# gpg: Signature made Thu 21 Jan 2016 14:54:56 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20160121: (36 commits)
  target-arm: Implement FPEXC32_EL2 system register
  target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode
  target-arm: Implement remaining illegal return event checks
  target-arm: Handle exception return from AArch64 to non-EL0 AArch32
  target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target
  target-arm: Pull semihosting handling out to arm_cpu_do_interrupt()
  target-arm: Use a single entry point for AArch64 and AArch32 exceptions
  target-arm: Move aarch64_cpu_do_interrupt() to helper.c
  target-arm: Properly support EL2 and EL3 in arm_el_is_aa64()
  arm_gic: Update ID registers based on revision
  hw/arm/virt: Add always-on property to the virt board timer
  hw/arm/virt: add secure memory region and UART
  hw/arm/virt: Wire up memory region to CPUs explicitly
  target-arm: Support multiple address spaces in page table walks
  target-arm: Implement cpu_get_phys_page_attrs_debug
  target-arm: Implement asidx_from_attrs
  target-arm: Add QOM property for Secure memory region
  qom/cpu: Add MemoryRegion property
  memory: Add address_space_init_shareable()
  exec.c: Use correct AddressSpace in watch_mem_read and watch_mem_write
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/3c9331c47f22...1a4f446f81c6

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