[Qemu-commits] [qemu/qemu] e913ca: sun4u: split out NPT and INT_DIS into separate CPU...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: e913cac71bac85438b7199711ac3290cb593701a
      
https://github.com/qemu/qemu/commit/e913cac71bac85438b7199711ac3290cb593701a
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2016-01-07 (Thu, 07 Jan 2016)

  Changed paths:
    M hw/sparc64/sun4u.c
    M target-sparc/cpu.h

  Log Message:
  -----------
  sun4u: split out NPT and INT_DIS into separate CPUTimer fields

Currently there is confusion between use of these bits for the timer and timer
compare registers (while they both have the same value, the behaviour is
different). Split into two separate CPUTimer fields so we can always reference
the correct value.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-By: Artyom Tarasenko <address@hidden>
Signed-off-by: Mark Cave-Ayland <address@hidden>


  Commit: bf43330aa418908f7a5e2acda28ac1a8ed0d8ad6
      
https://github.com/qemu/qemu/commit/bf43330aa418908f7a5e2acda28ac1a8ed0d8ad6
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2016-01-07 (Thu, 07 Jan 2016)

  Changed paths:
    M hw/sparc64/sun4u.c

  Log Message:
  -----------
  sun4u: split NPT and INT_DIS accesses between timer and compare registers

Accesses to the timer register high bit should only set NPT, whilst accesses
to the timer compare register high bit should only set INT_DIS. This fixes
issues with the timer being unexpectedly disabled whilst trying to boot
FreeBSD SPARC64.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-By: Artyom Tarasenko <address@hidden>
Signed-off-by: Mark Cave-Ayland <address@hidden>


  Commit: c9a464420d7eb67dace1f630554245360b4c7c5b
      
https://github.com/qemu/qemu/commit/c9a464420d7eb67dace1f630554245360b4c7c5b
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2016-01-07 (Thu, 07 Jan 2016)

  Changed paths:
    M target-sparc/helper.c
    M target-sparc/helper.h
    M target-sparc/translate.c

  Log Message:
  -----------
  target-sparc: implement NPT timer bit

If the NPT bit is set in the timer register, all non-supervisor read accesses
to the register should fail with a privilege exception.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-By: Artyom Tarasenko <address@hidden>
Signed-off-by: Mark Cave-Ayland <address@hidden>


  Commit: 263699432c90dab31eb8ab6ee0671458322e3d1e
      
https://github.com/qemu/qemu/commit/263699432c90dab31eb8ab6ee0671458322e3d1e
  Author: Peter Maydell <address@hidden>
  Date:   2016-01-07 (Thu, 07 Jan 2016)

  Changed paths:
    M hw/sparc64/sun4u.c
    M target-sparc/cpu.h
    M target-sparc/helper.c
    M target-sparc/helper.h
    M target-sparc/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into 
staging

qemu-sparc update

# gpg: Signature made Thu 07 Jan 2016 13:20:13 GMT using RSA key ID AE0F321F
# gpg: Good signature from "Mark Cave-Ayland <address@hidden>"

* remotes/mcayland/tags/qemu-sparc-signed:
  target-sparc: implement NPT timer bit
  sun4u: split NPT and INT_DIS accesses between timer and compare registers
  sun4u: split out NPT and INT_DIS into separate CPUTimer fields

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/ac93a0678684...263699432c90