[Qemu-commits] [qemu/qemu] 5c629f: target-arm: Fix gdb singlestep handling in arm_deb...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 5c629f4ff4dc9ae79cc732f59a8df15ede796ff7
      
https://github.com/qemu/qemu/commit/5c629f4ff4dc9ae79cc732f59a8df15ede796ff7
  Author: Sergey Fedorov <address@hidden>
  Date:   2015-11-10 (Tue, 10 Nov 2015)

  Changed paths:
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Fix gdb singlestep handling in arm_debug_excp_handler()

Do not raise a CPU exception if no CPU breakpoint has fired, since
singlestep is also done by generating a debug internal exception. This
fixes a bug with singlestepping in gdbstub.

Signed-off-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b95690c9beaffd95edf91eb67829dc1e0a81e666
      
https://github.com/qemu/qemu/commit/b95690c9beaffd95edf91eb67829dc1e0a81e666
  Author: Wei Huang <address@hidden>
  Date:   2015-11-10 (Tue, 10 Nov 2015)

  Changed paths:
    M hw/intc/arm_gic.c

  Log Message:
  -----------
  hw/intc/arm_gic: Remove the definition of NUM_CPU

arm_gic.c retrieves CPU number using either NUM_CPU(s) or s->num_cpu.
Such mixed-uses make source code inconsistent. This patch removes
NUM_CPU(s), which was defined for MPCore tweak long ago, and instead
favors s->num_cpu. The source is more consistent after this small tweak.

Reviewed-by: Andreas Färber <address@hidden>
Signed-off-by: Wei Huang <address@hidden>
Reviewed-by: Michael Tokarev <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: baf6b6815ba9ae8255eefd1ddf15216d53da34b5
      
https://github.com/qemu/qemu/commit/baf6b6815ba9ae8255eefd1ddf15216d53da34b5
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-11-10 (Tue, 10 Nov 2015)

  Changed paths:
    M hw/arm/boot.c
    M include/hw/arm/arm.h

  Log Message:
  -----------
  arm: boot: Add secure_board_setup flag

Add a flag that when set, will cause the primary CPU to start in secure
mode, even if the overall boot is non-secure. This is useful for when
there is a board-setup blob that needs to run from secure mode, but
device and secondary CPU init should still be done as-normal for a non-
secure boot.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dca6eeed8c2a1c131d161139428dd18a35e58b03
      
https://github.com/qemu/qemu/commit/dca6eeed8c2a1c131d161139428dd18a35e58b03
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-11-10 (Tue, 10 Nov 2015)

  Changed paths:
    M hw/arm/highbank.c

  Log Message:
  -----------
  arm: highbank: Defeature CPU override

This board should not support CPU model override. This allows for
easier patching of the board with being able to rely on the CPU
type being correct.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 40340e5f221935723bffbca305f3090e8866c818
      
https://github.com/qemu/qemu/commit/40340e5f221935723bffbca305f3090e8866c818
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-11-10 (Tue, 10 Nov 2015)

  Changed paths:
    M hw/arm/highbank.c

  Log Message:
  -----------
  arm: highbank: Implement PSCI and dummy monitor

Firstly, enable monitor mode and PSCI, both of which are features of
this board.

In addition to PSCI, this board also uses SMC for cache maintenance
ops. This means we need a secure monitor to catch these and nop them.
Use the ARM boot board-setup feature to implement this. The SMC trap
implements the needed nop while all other traps will pen the CPU.

As a KVM CPU cannot run in secure mode, do not do the board-setup if
not running TCG. Report a warning explaining the limitation in this
case.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: faa811f6de44d58180f5d235787678dcdd4b2e9d
      
https://github.com/qemu/qemu/commit/faa811f6de44d58180f5d235787678dcdd4b2e9d
  Author: Andrew Jones <address@hidden>
  Date:   2015-11-10 (Tue, 10 Nov 2015)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: error_report cleanups

Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 577bf808958d06497928c639efaa473bf8c5e099
      
https://github.com/qemu/qemu/commit/577bf808958d06497928c639efaa473bf8c5e099
  Author: Sergey Fedorov <address@hidden>
  Date:   2015-11-10 (Tue, 10 Nov 2015)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Clean up DISAS_UPDATE usage in AArch32 translation code

AArch32 translation code does not distinguish between DISAS_UPDATE and
DISAS_JUMP. Thus, we cannot use any of them without first updating PC in
CPU state. Furthermore, it is too complicated to update PC in CPU state
before PC gets updated in disas context. So it is hardly possible to
correctly end TB early if is is not likely to be executed before calling
disas_*_insn(), e.g. just after calling breakpoint check helper.

Modify DISAS_UPDATE and DISAS_JUMP usage in AArch32 translation and
apply to them the same semantic as AArch64 translation does:
 - DISAS_UPDATE: update PC in CPU state when finishing translation
 - DISAS_JUMP:   preserve current PC value in CPU state when finishing
           translation

This patch fixes a bug in AArch32 breakpoint handling: when
check_breakpoints helper does not generate an exception, ending the TB
early with DISAS_UPDATE couldn't update PC in CPU state and execution
hangs.

Signed-off-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a1a88589dc982f9f8b6c717c2ac98dd71dd4353d
      
https://github.com/qemu/qemu/commit/a1a88589dc982f9f8b6c717c2ac98dd71dd4353d
  Author: Peter Maydell <address@hidden>
  Date:   2015-11-10 (Tue, 10 Nov 2015)

  Changed paths:
    M hw/arm/boot.c
    M hw/arm/highbank.c
    M hw/arm/virt.c
    M hw/intc/arm_gic.c
    M include/hw/arm/arm.h
    M target-arm/op_helper.c
    M target-arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20151110' 
into staging

target-arm queue:
 * fix bugs in gdb singlestep handling and breakpoints
 * minor code cleanup in arm_gic
 * clean up error messages in hw/arm/virt
 * fix highbank kernel booting by adding a board-setup blob

# gpg: Signature made Tue 10 Nov 2015 13:43:52 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20151110:
  target-arm: Clean up DISAS_UPDATE usage in AArch32 translation code
  hw/arm/virt: error_report cleanups
  arm: highbank: Implement PSCI and dummy monitor
  arm: highbank: Defeature CPU override
  arm: boot: Add secure_board_setup flag
  hw/intc/arm_gic: Remove the definition of NUM_CPU
  target-arm: Fix gdb singlestep handling in arm_debug_excp_handler()

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/a8b4f9585a0b...a1a88589dc98