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[Qemu-commits] [qemu/qemu] 7cd6de: target-arm: Fix "no 64-bit EL2" assum

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 7cd6de: target-arm: Fix "no 64-bit EL2" assumption in arm_...
Date: Wed, 28 Oct 2015 07:00:06 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 7cd6de3bb1ca55dfa8f53fb9894803eb33f497b3
      
https://github.com/qemu/qemu/commit/7cd6de3bb1ca55dfa8f53fb9894803eb33f497b3
  Author: Peter Maydell <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: Fix "no 64-bit EL2" assumption in arm_excp_unmasked()

The code in arm_excp_unmasked() suppresses the ability of PSTATE.AIF
to mask exceptions from a lower EL targeting EL2 or EL3 if the
CPU is 64-bit. This is correct for a target of EL3, but not correct
for targeting EL2. Further, we go to some effort to calculate
scr and hcr values which are not used at all for the 64-bit CPU
case.

Rearrange the code to correctly implement the 64-bit CPU logic
and keep the hcr/scr calculations in the 32-bit CPU codepath.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>


  Commit: 541ebcd401ee47f3c1a3ce503ef5466b75e9d20a
      
https://github.com/qemu/qemu/commit/541ebcd401ee47f3c1a3ce503ef5466b75e9d20a
  Author: Peter Maydell <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm/translate.c: Handle non-executable page-straddling Thumb insns

When the memory we're trying to translate code from is not executable we have
to turn this into a guest fault. In order to report the correct PC for this
fault, and to make sure it is not reported until after any other possible
faults for instructions earlier in execution, we must terminate TBs at
the end of a page, in case the next instruction is in a non-executable page.
This is simple for T16, A32 and A64 instructions, which are always aligned
to their size. However T32 instructions may be 32-bits but only 16-aligned,
so they can straddle a page boundary.

Correct the condition that checks whether the next instruction will touch
the following page, to ensure that if we're 2 bytes before the boundary
and this insn is T32 then we end the TB.

Reported-by: Pavel Dovgalyuk <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b876452507d0b719cff0b478efafb34ac41db683
      
https://github.com/qemu/qemu/commit/b876452507d0b719cff0b478efafb34ac41db683
  Author: Soren Brinkmann <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ)

Signed-off-by: Soren Brinkmann <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 24182fbc19cbc7c387bb350a72e6b55f63ea1747
      
https://github.com/qemu/qemu/commit/24182fbc19cbc7c387bb350a72e6b55f63ea1747
  Author: Pavel Fedin <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M hw/intc/arm_gic_kvm.c
    M include/hw/intc/arm_gic_common.h

  Log Message:
  -----------
  arm_gic_kvm: Disable live migration if not supported

Currently, if the kernel does not have live migration API, the migration
will still be attempted, but vGIC save/restore functions will just not do
anything. This will result in a broken machine state.

This patch fixes the problem by adding migration blocker if kernel API is
not supported.

Signed-off-by: Pavel Fedin <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4b280b726a329a97db03323d8d03ed554f7872b8
      
https://github.com/qemu/qemu/commit/4b280b726a329a97db03323d8d03ed554f7872b8
  Author: Andrew Jones <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: don't use a15memmap directly

We should always go through VirtBoardInfo when we need the memmap.
To avoid using a15memmap directly, in this case, we need to defer
the max-cpus check from class init time to instance init time. In
class init we now use MAX_CPUMASK_BITS for max_cpus initialization,
which is the maximum QEMU supports, and also, incidentally, the
maximum KVM/gicv3 currently supports. Also, a nice side-effect of
delaying the max-cpus check is that we now get more appropriate
error messages for gicv2 machines that try to configure more than
123 cpus. Before this patch it would complain that the requested
number of cpus was greater than 123, but for gicv2 configs, it
should complain that the number is greater than 8.

Signed-off-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8ccce77c04a23a1451b6e149930e66b6eef75926
      
https://github.com/qemu/qemu/commit/8ccce77c04a23a1451b6e149930e66b6eef75926
  Author: Jean-Christophe Dubois <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M hw/char/imx_serial.c

  Log Message:
  -----------
  i.MX: Standardize i.MX serial debug.

The goal is to have debug code always compiled during build.

We standardize all debug output on the following format:

[QOM_TYPE_NAME]reporting_function: debug message

We also replace IPRINTF with qemu_log_mask(). The qemu_log_mask() output
is following the same format as the above debug.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Message-id: address@hidden
[PMM: Drop attempt to print the ram_addr of a memory region in
 one DPRINTF, which (a) was using the wrong format string so
 didn't build on 32-bit and (b) was incorrectly looking at a
 private field of a MemoryRegion struct]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 564111257468bb772ad0b374dbbb0c969a554cfd
      
https://github.com/qemu/qemu/commit/564111257468bb772ad0b374dbbb0c969a554cfd
  Author: Jean-Christophe Dubois <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M hw/gpio/imx_gpio.c

  Log Message:
  -----------
  i.MX: Standardize i.MX GPIO debug

The goal is to have debug code always compiled during build.

We standardize all debug output on the following format:

[QOM_TYPE_NAME]reporting_function: debug message

The qemu_log_mask() outputis following the same format as
the above debug.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3afcbb01bc1227bc3a3bade1804c449daf74b262
      
https://github.com/qemu/qemu/commit/3afcbb01bc1227bc3a3bade1804c449daf74b262
  Author: Jean-Christophe Dubois <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M hw/i2c/imx_i2c.c

  Log Message:
  -----------
  i.MX: Standardize i.MX I2C debug

The goal is to have debug code always compiled during build.

We standardize all debug output on the following format:

[QOM_TYPE_NAME]reporting_function: debug message

The qemu_log_mask() output is following the same format as
the above debug.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f50ed7853ad658407382dfe1da29f3c88d604592
      
https://github.com/qemu/qemu/commit/f50ed7853ad658407382dfe1da29f3c88d604592
  Author: Jean-Christophe Dubois <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M hw/intc/imx_avic.c

  Log Message:
  -----------
  i.MX: Standardize i.MX AVIC debug

The goal is to have debug code always compiled during build.

We standardize all debug output on the following format:

[QOM_TYPE_NAME]reporting_function: debug message

We also replace IPRINTF with qemu_log_mask(). The qemu_log_mask() output
is following the same format as the above debug.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4a6aa0af8593ee135ef37867ae00109650b95638
      
https://github.com/qemu/qemu/commit/4a6aa0af8593ee135ef37867ae00109650b95638
  Author: Jean-Christophe Dubois <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M hw/misc/imx_ccm.c

  Log Message:
  -----------
  i.MX: Standardize i.MX CCM debug

The goal is to have debug code always compiled during build.

We standardize all debug output on the following format:

[QOM_TYPE_NAME]reporting_function: debug message

The qemu_log_mask() output is following the same format as the
above debug.

Adding some missing qemu_log_mask call for bad registers.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b72d8d257c187532194f2fca504afb568cd2a3bf
      
https://github.com/qemu/qemu/commit/b72d8d257c187532194f2fca504afb568cd2a3bf
  Author: Jean-Christophe Dubois <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M hw/net/imx_fec.c

  Log Message:
  -----------
  i.MX: Standardize i.MX FEC debug

The goal is to have debug code always compiled during build.

We standardize all debug output on the following format:

[QOM_TYPE_NAME]reporting_function: debug message

The qemu_log_mask() output is following the same format as the
above debug.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4929f6563c704dbd057524b38ee519b3a7c8dfe1
      
https://github.com/qemu/qemu/commit/4929f6563c704dbd057524b38ee519b3a7c8dfe1
  Author: Jean-Christophe Dubois <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M hw/timer/imx_epit.c

  Log Message:
  -----------
  i.MX: Standardize i.MX EPIT debug

The goal is to have debug code always compiled during build.

We standardize all debug output on the following format:

[QOM_TYPE_NAME]reporting_function: debug message

We also replace IPRINTF with qemu_log_mask(). The qemu_log_mask() output
is following the same format as the above debug.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 054535262fce994b942039b0a7c4c484c8026c5e
      
https://github.com/qemu/qemu/commit/054535262fce994b942039b0a7c4c484c8026c5e
  Author: Jean-Christophe Dubois <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M hw/timer/imx_gpt.c

  Log Message:
  -----------
  i.MX: Standardize i.MX GPT debug

The goal is to have debug code always compiled during build.

We standardize all debug output on the following format:

[QOM_TYPE_NAME]reporting_function: debug message

We also replace IPRINTF with qemu_log_mask(). The qemu_log_mask() output
is following the same format as the above debug.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 59e055307392fdf99b86c8cbcd33a7e261dcbdb1
      
https://github.com/qemu/qemu/commit/59e055307392fdf99b86c8cbcd33a7e261dcbdb1
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add HPFAR_EL2

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5c31a10d16c595d6a59e3e7fc1808c3b1d03e02f
      
https://github.com/qemu/qemu/commit/5c31a10d16c595d6a59e3e7fc1808c3b1d03e02f
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: lpae: Make t0sz and t1sz signed integers

Make t0sz and t1sz signed integers to match tsz and to make
it easier to implement support for AArch32 negative t0sz.
t1sz is changed for consistensy.

No functional change.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1f4c8c18a5b6f4fad13e13b7e3828124c6c8f34d
      
https://github.com/qemu/qemu/commit/1f4c8c18a5b6f4fad13e13b7e3828124c6c8f34d
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: lpae: Move declaration of t0sz and t1sz

Move declaration of t0sz and t1sz to the top of the function
avoiding a mix of code and variable declarations.

No functional change.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4ee38098010240e0b390061fdd0151ff62d80279
      
https://github.com/qemu/qemu/commit/4ee38098010240e0b390061fdd0151ff62d80279
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add support for AArch32 S2 negative t0sz

Add support for AArch32 S2 negative t0sz. In preparation for
using 40bit IPAs on AArch32.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4ca6a051758edf625a17dfc4ce4ab72edabac170
      
https://github.com/qemu/qemu/commit/4ca6a051758edf625a17dfc4ce4ab72edabac170
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: lpae: Replace tsz with computed inputsize

Remove the tsz variable and introduce inputsize.
This simplifies the code a little and makes it easier to
compare with the reference manuals.

No functional change.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 973a5434825c076995218868b5b3047e5de400c6
      
https://github.com/qemu/qemu/commit/973a5434825c076995218868b5b3047e5de400c6
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: lpae: Rename granule_sz to stride

Rename granule_sz to stride to better match the reference manuals.

No functional change.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1853d5a9dcac910322c6cc5b2fddec45fd052d25
      
https://github.com/qemu/qemu/commit/1853d5a9dcac910322c6cc5b2fddec45fd052d25
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M target-arm/helper.c
    M target-arm/internals.h

  Log Message:
  -----------
  target-arm: Add computation of starting level for S2 PTW

The starting level for S2 pagetable walks is computed
differently from the S1 starting level. Implement the S2
variant.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6ab1a5ee1c9d328cacf78805439ed4d3d132decd
      
https://github.com/qemu/qemu/commit/6ab1a5ee1c9d328cacf78805439ed4d3d132decd
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add support for S2 page-table protection bits

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: af51f566ec7106d5e834476e78681a7b354f3c7c
      
https://github.com/qemu/qemu/commit/af51f566ec7106d5e834476e78681a7b354f3c7c
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Avoid inline for get_phys_addr

Avoid inline for get_phys_addr() to prepare for future recursive use.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e14b5a23d8c83304559f31397f95d22ada60a19a
      
https://github.com/qemu/qemu/commit/e14b5a23d8c83304559f31397f95d22ada60a19a
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M target-arm/helper.c
    M target-arm/internals.h
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Add ARMMMUFaultInfo

Introduce ARMMMUFaultInfo to propagate MMU Fault information
across the MMU translation code path. This is in preparation for
adding Stage-2 translation.

No functional changes.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 37785977627295162bff58b1f8777d94e20f4c5b
      
https://github.com/qemu/qemu/commit/37785977627295162bff58b1f8777d94e20f4c5b
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M target-arm/helper.c
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Add S2 translation to 64bit S1 PTWs

Add support for applying S2 translation to 64bit S1
page-table walks.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a614e69854a2e601716ee44dfe15c09b8b88f620
      
https://github.com/qemu/qemu/commit/a614e69854a2e601716ee44dfe15c09b8b88f620
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add S2 translation to 32bit S1 PTWs

Add support for applying S2 translation to 32bit S1
page-table walks.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d759a457a144844bff259aafda093b24e92c116d
      
https://github.com/qemu/qemu/commit/d759a457a144844bff259aafda093b24e92c116d
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Route S2 MMU faults to EL2

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9b539263faa5c1b7fce2551092b5c7b6eea92081
      
https://github.com/qemu/qemu/commit/9b539263faa5c1b7fce2551092b5c7b6eea92081
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M target-arm/helper.c
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Add support for S1 + S2 MMU translations

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c012e1b7ad066f462ba1c3322fcb43cd8295eaff
      
https://github.com/qemu/qemu/commit/c012e1b7ad066f462ba1c3322fcb43cd8295eaff
  Author: Peter Maydell <address@hidden>
  Date:   2015-10-27 (Tue, 27 Oct 2015)

  Changed paths:
    M hw/arm/virt.c
    M hw/char/imx_serial.c
    M hw/gpio/imx_gpio.c
    M hw/i2c/imx_i2c.c
    M hw/intc/arm_gic_kvm.c
    M hw/intc/imx_avic.c
    M hw/misc/imx_ccm.c
    M hw/net/imx_fec.c
    M hw/timer/imx_epit.c
    M hw/timer/imx_gpt.c
    M include/hw/intc/arm_gic_common.h
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/internals.h
    M target-arm/op_helper.c
    M target-arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20151027-1' into staging

target-arm queue:
 * more EL2 preparation: handling for stage 2 translations
 * standardize debug macros in i.MX devices
 * improve error message in a corner case for virt board
 * disable live migration of KVM GIC if the kernel can't handle it
 * add SPSR_(ABT|UND|IRQ|FIQ) registers
 * handle non-executable page-straddling Thumb instructions
 * fix a "no 64-bit EL2" assumption in arm_excp_unmasked()

# gpg: Signature made Tue 27 Oct 2015 16:03:31 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20151027-1: (27 commits)
  target-arm: Add support for S1 + S2 MMU translations
  target-arm: Route S2 MMU faults to EL2
  target-arm: Add S2 translation to 32bit S1 PTWs
  target-arm: Add S2 translation to 64bit S1 PTWs
  target-arm: Add ARMMMUFaultInfo
  target-arm: Avoid inline for get_phys_addr
  target-arm: Add support for S2 page-table protection bits
  target-arm: Add computation of starting level for S2 PTW
  target-arm: lpae: Rename granule_sz to stride
  target-arm: lpae: Replace tsz with computed inputsize
  target-arm: Add support for AArch32 S2 negative t0sz
  target-arm: lpae: Move declaration of t0sz and t1sz
  target-arm: lpae: Make t0sz and t1sz signed integers
  target-arm: Add HPFAR_EL2
  i.MX: Standardize i.MX GPT debug
  i.MX: Standardize i.MX EPIT debug
  i.MX: Standardize i.MX FEC debug
  i.MX: Standardize i.MX CCM debug
  i.MX: Standardize i.MX AVIC debug
  i.MX: Standardize i.MX I2C debug
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/7e038b94e74e...c012e1b7ad06
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