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[Qemu-commits] [qemu/qemu] dd75d4: target-i386: allow any alignment for

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] dd75d4: target-i386: allow any alignment for SMBASE
Date: Fri, 23 Oct 2015 10:30:07 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: dd75d4fcb4a82c34d4f466e7fc166162b71ff740
      
https://github.com/qemu/qemu/commit/dd75d4fcb4a82c34d4f466e7fc166162b71ff740
  Author: Paolo Bonzini <address@hidden>
  Date:   2015-10-23 (Fri, 23 Oct 2015)

  Changed paths:
    M target-i386/smm_helper.c

  Log Message:
  -----------
  target-i386: allow any alignment for SMBASE

Processors up to the Pentium (says Bochs---I do not have old enough
manuals) require a 32KiB alignment for the SMBASE, but newer processors
do not need that, and Tiano Core will use non-aligned SMBASE values.

Reported-by: Michael D Kinney <address@hidden>
Cc: Laszlo Ersek <address@hidden>
Cc: Jordan Justen <address@hidden>
Cc: Eduardo Habkost <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
Reviewed-by: Laszlo Ersek <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: e265e3e48049fbece9eaf536aa00ca41aa3c54d0
      
https://github.com/qemu/qemu/commit/e265e3e48049fbece9eaf536aa00ca41aa3c54d0
  Author: Eduardo Habkost <address@hidden>
  Date:   2015-10-23 (Fri, 23 Oct 2015)

  Changed paths:
    M include/hw/i386/pc.h
    M target-i386/cpu.c

  Log Message:
  -----------
  target-i386: Disable cache info passthrough by default

The host cache information may not make sense for the guest if the VM
CPU topology doesn't match the host CPU topology. To make sure we won't
expose broken cache information to the guest, disable cache info
passthrough by default, and add a new "host-cache-info" property that
can be used to enable the old behavior for users that really need it.

Cc: Benoît Canet <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 93d00d0fbe4711061834730fb70525d167b6f908
      
https://github.com/qemu/qemu/commit/93d00d0fbe4711061834730fb70525d167b6f908
  Author: Richard Henderson <address@hidden>
  Date:   2015-10-23 (Fri, 23 Oct 2015)

  Changed paths:
    M target-i386/bpt_helper.c
    M target-i386/cpu.h
    M target-i386/machine.c
    M target-i386/seg_helper.c

  Log Message:
  -----------
  target-i386: Introduce cpu_x86_update_dr7

This moves the last of the iteration over breakpoints into
the bpt_helper.c file.  This also allows us to make several
breakpoint functions static.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 36eb6e096729f9aade3a6af7dbe4d0a990335d7e
      
https://github.com/qemu/qemu/commit/36eb6e096729f9aade3a6af7dbe4d0a990335d7e
  Author: Richard Henderson <address@hidden>
  Date:   2015-10-23 (Fri, 23 Oct 2015)

  Changed paths:
    M target-i386/bpt_helper.c

  Log Message:
  -----------
  target-i386: Re-introduce optimal breakpoint removal

Before the last patch, we had an efficient loop that disabled
local breakpoints on task switch.  Re-add that, but in a more
general way that handles changes to the global enable bits too.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 9055330ffbf5ca85f024c29874799d9c8bd17aa9
      
https://github.com/qemu/qemu/commit/9055330ffbf5ca85f024c29874799d9c8bd17aa9
  Author: Eduardo Habkost <address@hidden>
  Date:   2015-10-23 (Fri, 23 Oct 2015)

  Changed paths:
    M target-i386/bpt_helper.c

  Log Message:
  -----------
  target-i386: Ensure bit 10 on DR7 is never cleared

Bit 10 of DR7 is documented as always set to 1, so ensure that's
always the case.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 696ad9e4b27a49a9706010d00b31b17fe1f0d569
      
https://github.com/qemu/qemu/commit/696ad9e4b27a49a9706010d00b31b17fe1f0d569
  Author: Richard Henderson <address@hidden>
  Date:   2015-10-23 (Fri, 23 Oct 2015)

  Changed paths:
    M target-i386/bpt_helper.c
    M target-i386/cpu.h

  Log Message:
  -----------
  target-i386: Move hw_*breakpoint_* functions

They're only used from bpt_helper.c now.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 7525b55051277717329cf64a9e1d5cff840d6f38
      
https://github.com/qemu/qemu/commit/7525b55051277717329cf64a9e1d5cff840d6f38
  Author: Richard Henderson <address@hidden>
  Date:   2015-10-23 (Fri, 23 Oct 2015)

  Changed paths:
    M target-i386/bpt_helper.c

  Log Message:
  -----------
  target-i386: Optimize setting dr[0-3]

If the debug register is not enabled, we need
do nothing besides update the register.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 5223a9423c5fb9e32b0c3eaaa2c0bf8c5cfd6866
      
https://github.com/qemu/qemu/commit/5223a9423c5fb9e32b0c3eaaa2c0bf8c5cfd6866
  Author: Eduardo Habkost <address@hidden>
  Date:   2015-10-23 (Fri, 23 Oct 2015)

  Changed paths:
    M target-i386/bpt_helper.c
    M target-i386/cpu.h
    M target-i386/helper.h
    M target-i386/translate.c

  Log Message:
  -----------
  target-i386: Handle I/O breakpoints

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: d0052339236072bbf08c1d600c0906126b1ab258
      
https://github.com/qemu/qemu/commit/d0052339236072bbf08c1d600c0906126b1ab258
  Author: Richard Henderson <address@hidden>
  Date:   2015-10-23 (Fri, 23 Oct 2015)

  Changed paths:
    M target-i386/bpt_helper.c
    M target-i386/cpu.h
    M target-i386/helper.h
    M target-i386/translate.c

  Log Message:
  -----------
  target-i386: Check CR4[DE] for processing DR4/DR5

Introduce helper_get_dr so that we don't have to put CR4[DE]
into the scarce HFLAGS resource.  At the same time, rename
helper_movl_drN_T0 to helper_set_dr and set the helper flags.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 462f8ed1f1eac189ef50d9586eae8af90dbe426f
      
https://github.com/qemu/qemu/commit/462f8ed1f1eac189ef50d9586eae8af90dbe426f
  Author: Eduardo Habkost <address@hidden>
  Date:   2015-10-23 (Fri, 23 Oct 2015)

  Changed paths:
    M target-i386/bpt_helper.c

  Log Message:
  -----------
  target-i386: Ensure always-1 bits on DR6 can't be cleared

Bits 4-11 and 16-31 on DR6 are documented as always 1, so ensure they
can't be cleared by software.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: b6c5a6f021f485fc36bca678b2c867e9b6783924
      
https://github.com/qemu/qemu/commit/b6c5a6f021f485fc36bca678b2c867e9b6783924
  Author: Eduardo Habkost <address@hidden>
  Date:   2015-10-23 (Fri, 23 Oct 2015)

  Changed paths:
    M target-i386/cpu.c

  Log Message:
  -----------
  target-i386: Add DE to TCG_FEATURES

Now DE is supported by TCG so it can be enabled in CPUID bits.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 72370dc1149d7c90d2c2218e0d0658bee23a5bf7
      
https://github.com/qemu/qemu/commit/72370dc1149d7c90d2c2218e0d0658bee23a5bf7
  Author: Eduardo Habkost <address@hidden>
  Date:   2015-10-23 (Fri, 23 Oct 2015)

  Changed paths:
    M target-i386/cpu.c

  Log Message:
  -----------
  target-i386: Use 1UL for bit shift

Fix undefined behavior detected by clang runtime check:

  qemu/target-i386/cpu.c:1494:15: runtime error:
    left shift of 1 by 31 places cannot be represented in type 'int'

While doing that, add extra parenthesis for clarity.

Reported-by: Peter Maydell <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 31bfa2a40004204aee503c6417fbafb5d17e0a51
      
https://github.com/qemu/qemu/commit/31bfa2a40004204aee503c6417fbafb5d17e0a51
  Author: Andrew Jones <address@hidden>
  Date:   2015-10-23 (Fri, 23 Oct 2015)

  Changed paths:
    M vl.c

  Log Message:
  -----------
  vl: trivial: minor tweaks to a max-cpu error msg

Signed-off-by: Andrew Jones <address@hidden>


  Commit: bc79082e4cd12c1241fa03b0abceacf45f537740
      
https://github.com/qemu/qemu/commit/bc79082e4cd12c1241fa03b0abceacf45f537740
  Author: Peter Maydell <address@hidden>
  Date:   2015-10-23 (Fri, 23 Oct 2015)

  Changed paths:
    M include/hw/i386/pc.h
    M target-i386/bpt_helper.c
    M target-i386/cpu.c
    M target-i386/cpu.h
    M target-i386/helper.h
    M target-i386/machine.c
    M target-i386/seg_helper.c
    M target-i386/smm_helper.c
    M target-i386/translate.c
    M vl.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into 
staging

X86 queue, 2015-10-23

# gpg: Signature made Fri 23 Oct 2015 16:30:58 BST using RSA key ID 984DC5A6
# gpg: Good signature from "Eduardo Habkost <address@hidden>"

* remotes/ehabkost/tags/x86-pull-request:
  vl: trivial: minor tweaks to a max-cpu error msg
  target-i386: Use 1UL for bit shift
  target-i386: Add DE to TCG_FEATURES
  target-i386: Ensure always-1 bits on DR6 can't be cleared
  target-i386: Check CR4[DE] for processing DR4/DR5
  target-i386: Handle I/O breakpoints
  target-i386: Optimize setting dr[0-3]
  target-i386: Move hw_*breakpoint_* functions
  target-i386: Ensure bit 10 on DR7 is never cleared
  target-i386: Re-introduce optimal breakpoint removal
  target-i386: Introduce cpu_x86_update_dr7
  target-i386: Disable cache info passthrough by default
  target-i386: allow any alignment for SMBASE

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/1e700f4c6cdd...bc79082e4cd1
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