[Qemu-commits] [qemu/qemu] 116dc1: kvm_ppc: remove kvmppc_timer_hack

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 116dc18db6854cc38c6abff799019b7237365a36
      
https://github.com/qemu/qemu/commit/116dc18db6854cc38c6abff799019b7237365a36
  Author: Paolo Bonzini <address@hidden>
  Date:   2015-09-20 (Sun, 20 Sep 2015)

  Changed paths:
    M hw/ppc/e500.c
    M hw/ppc/ppc440_bamboo.c
    M target-ppc/Makefile.objs
    R target-ppc/kvm_ppc.c
    M target-ppc/kvm_ppc.h

  Log Message:
  -----------
  kvm_ppc: remove kvmppc_timer_hack

QEMU does have an I/O thread now, that can be interrupted at any time
because the VCPU thread runs outside the iothread mutex.

Therefore, the kvmppc_timer_hack is obsolete.  Remove it.

Signed-off-by: Paolo Bonzini <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 1cde732d88af34849343dc1f0e68072eab0841b9
      
https://github.com/qemu/qemu/commit/1cde732d88af34849343dc1f0e68072eab0841b9
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2015-09-20 (Sun, 20 Sep 2015)

  Changed paths:
    M hw/misc/macio/mac_dbdma.c

  Log Message:
  -----------
  mac_dbdma: always clear FLUSH bit once DBDMA channel flush is complete

The code to flush the DBDMA channel was effectively duplicated in
dbdma_control_write(), except for the fact that the copy executed outside of a
RUN bit transition was broken by not clearing the FLUSH bit once the flush was
complete.

Newer PPC Linux kernels would timeout waiting for the FLUSH bit to clear again
after submitting a FLUSH command. Fix this by always clearing the FLUSH bit
once the channel flush is complete and removing the repeated code.

Reported-by: Aurelien Jarno <address@hidden>
Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: e7f08320f055e1093007b3f1d55b145d5f4daaa1
      
https://github.com/qemu/qemu/commit/e7f08320f055e1093007b3f1d55b145d5f4daaa1
  Author: Rudolf Marek <address@hidden>
  Date:   2015-09-20 (Sun, 20 Sep 2015)

  Changed paths:
    M hw/pci-host/ppce500.c

  Log Message:
  -----------
  PPC: e500 pci host: Fix ATMUs register reads

There is a bug in the register mask when reading
the ATMUs registers. As the result some registers
cannot be read, and read is aliased to the other
registers. Fix it.

Signed-off-by: Rudolf Marek <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6bb9a0a9ef9b9b1c2434a52d1c1d066ce179adf8
      
https://github.com/qemu/qemu/commit/6bb9a0a9ef9b9b1c2434a52d1c1d066ce179adf8
  Author: Anton Blanchard <address@hidden>
  Date:   2015-09-20 (Sun, 20 Sep 2015)

  Changed paths:
    M linux-user/main.c
    M target-ppc/excp_helper.c

  Log Message:
  -----------
  target-ppc: Fix SRR0 when taking unaligned exceptions

We are setting SRR0 to the instruction before the one causing the
unaligned exception. A quick testcase:

. = 0x100
.globl _start
_start:
        /* Cause a 0x600 */
        li      3,0x1
        stwcx.  3,0,3
1:      b       1b

. = 0x600
1:      b       1b

Built into something we can load as a BIOS image:

gcc -mbig -c test.S
ld -EB -Ttext 0x0 -o test test.o
objcopy -O binary test test.bin

Run with:

qemu-system-ppc64 -nographic -bios test.bin

Shows an incorrect SRR0 (points at the li):

SRR0 0000000000000100

With the patch we get the correct SRR0:

SRR0 0000000000000104

Signed-off-by: Anton Blanchard <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: d4574435a6530bbd96ae130eddfe5b676f91367a
      
https://github.com/qemu/qemu/commit/d4574435a6530bbd96ae130eddfe5b676f91367a
  Author: Alexander Graf <address@hidden>
  Date:   2015-09-20 (Sun, 20 Sep 2015)

  Changed paths:
    M pc-bios/u-boot.e500

  Log Message:
  -----------
  PPC: E500: Update u-boot to commit 79c884d7e4

The current U-Boot binary in QEMU has a bug where it fails to support
dynamic CCSR addressing. Without this support, u-boot can not boot the
ppce500 machine anymore. This has been fixed upstream in u-boot commit
e834975b.

Update the u-boot blob we carry in QEMU to the latest u-boot upstream,
so that we can successfully run u-boot with the ppce500 machine again.

CC: address@hidden
Signed-off-by: Alexander Graf <address@hidden>
Tested-by: Thomas Huth <address@hidden>


  Commit: 65cf1f65be0fc4883edbd66feeab3ddaceb11c00
      
https://github.com/qemu/qemu/commit/65cf1f65be0fc4883edbd66feeab3ddaceb11c00
  Author: Aurelien Jarno <address@hidden>
  Date:   2015-09-20 (Sun, 20 Sep 2015)

  Changed paths:
    M target-ppc/int_helper.c

  Log Message:
  -----------
  target-ppc: fix vcipher, vcipherlast, vncipherlast and vpermxor

For vector instructions, the helpers get pointers to the vector register
in arguments. Some operands might point to the same register, including
the operand holding the result.

When emulating instructions which access the vector elements in a
non-linear way, we need to store the result in an temporary variable.

This fixes openssl when emulating a POWER8 CPU.

Signed-off-by: Aurelien Jarno <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 8f60f8e2e574f341709128ff7637e685fd640254
      
https://github.com/qemu/qemu/commit/8f60f8e2e574f341709128ff7637e685fd640254
  Author: Aurelien Jarno <address@hidden>
  Date:   2015-09-20 (Sun, 20 Sep 2015)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: fix xscmpodp and xscmpudp decoding

The xscmpodp and xscmpudp instructions only have the AX, BX bits in
there encoding, the lowest bit (usually TX) is marked as an invalid
bit. We therefore can't decode them with GEN_XX2FORM, which decodes
the two lowest bit.

Introduce a new form GEN_XX2FORM, which decodes AX and BX and mark
the lowest bit as invalid.

Signed-off-by: Aurelien Jarno <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Tested-by: Richard W.M. Jones <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: d345e0d7b755591da379b23c628613d0a5cd2566
      
https://github.com/qemu/qemu/commit/d345e0d7b755591da379b23c628613d0a5cd2566
  Author: Peter Maydell <address@hidden>
  Date:   2015-09-21 (Mon, 21 Sep 2015)

  Changed paths:
    M hw/misc/macio/mac_dbdma.c
    M hw/pci-host/ppce500.c
    M hw/ppc/e500.c
    M hw/ppc/ppc440_bamboo.c
    M linux-user/main.c
    M pc-bios/u-boot.e500
    M target-ppc/Makefile.objs
    M target-ppc/excp_helper.c
    M target-ppc/int_helper.c
    R target-ppc/kvm_ppc.c
    M target-ppc/kvm_ppc.h
    M target-ppc/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' 
into staging

Patch queue for ppc - 2015-09-20

Highlights this time around:

  - e500: Fix u-boot boot with -M virt by updating to new version
  - e500: fix ATMU reads
  - book3s: Fixes (unaligned exceptions, vector instructions)
  - yet another dbdma ide fix

I'm out taking care of my son for the next 2 months. During that time
please consider David Gibson the interim ppc queue maintainer. I'm sure
Aurelien will be more than happy to help him review patches as well ;-).

# gpg: Signature made Sun 20 Sep 2015 21:51:16 BST using RSA key ID 03FEDC60
# gpg: Good signature from "Alexander Graf <address@hidden>"
# gpg:                 aka "Alexander Graf <address@hidden>"

* remotes/agraf/tags/signed-ppc-for-upstream:
  target-ppc: fix xscmpodp and xscmpudp decoding
  target-ppc: fix vcipher, vcipherlast, vncipherlast and vpermxor
  PPC: E500: Update u-boot to commit 79c884d7e4
  target-ppc: Fix SRR0 when taking unaligned exceptions
  PPC: e500 pci host: Fix ATMUs register reads
  mac_dbdma: always clear FLUSH bit once DBDMA channel flush is complete
  kvm_ppc: remove kvmppc_timer_hack

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/18640989a9f5...d345e0d7b755