[Qemu-commits] [qemu/qemu] 52c16b: arm: xlnx-zynqmp: Fix up GIC region s

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[Qemu-commits] [qemu/qemu] 52c16b: arm: xlnx-zynqmp: Fix up GIC region s

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 52c16b: arm: xlnx-zynqmp: Fix up GIC region size
Date:	Mon, 14 Sep 2015 08:30:05 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 52c16b458ab2f8766867bc5fc099b0a604a36f77
      
https://github.com/qemu/qemu/commit/52c16b458ab2f8766867bc5fc099b0a604a36f77
  Author: Nathan Rossi <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  arm: xlnx-zynqmp: Fix up GIC region size

The GIC in ZynqMP cover a 64K address space, however the actual
registers are decoded within a 4K address space and mirrored at the 4K
boundaries. This change fixes the defined size for these regions as it
was set to 0x4000/16K incorrectly.

Signed-off-by: Nathan Rossi <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 24cfc8dc583db57303137fd41f9f42806ea315a0
      
https://github.com/qemu/qemu/commit/24cfc8dc583db57303137fd41f9f42806ea315a0
  Author: Alistair Francis <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c

  Log Message:
  -----------
  xlnx-zynqmp: Remove unnecessary brackets around error messages

The errp and err variable have unnecessary brackets around them,
so remove the brackets.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 78bcaa3e37afbd0c5316634f917c13487384b6ca
      
https://github.com/qemu/qemu/commit/78bcaa3e37afbd0c5316634f917c13487384b6ca
  Author: Richard Henderson <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: Share all common TCG temporaries

This is a bug fix for aarch64.  At present, we have branches using
the 32-bit (translate.c) versions of cpu_[NZCV]F, but we set the flags
using the 64-bit (translate-a64.c) versions of cpu_[NZCV]F.  From
the view of the TCG code generator, these are unrelated variables.

The bug is hard to see because we currently only read these variables
from branches, and upon reaching a branch TCG will first spill live
variables and then reload the arguments of the branch.  Since the
32-bit versions were never live until reaching the branch, we'd re-read
the data that had just been spilled from the 64-bit versions.

There is currently no such problem with the cpu_exclusive_* variables,
but there's no point in tempting fate.

Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6c2c63d3a02c79e9035ca0370cc549d0f938a4dd
      
https://github.com/qemu/qemu/commit/6c2c63d3a02c79e9035ca0370cc549d0f938a4dd
  Author: Richard Henderson <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: Introduce DisasCompare

Split arm_gen_test_cc into 3 functions, so that it can be reused
for non-branch TCG comparisons.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9305eac09e61d857c9cc11e20db754dfc25a82db
      
https://github.com/qemu/qemu/commit/9305eac09e61d857c9cc11e20db754dfc25a82db
  Author: Richard Henderson <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Handle always condition codes within arm_test_cc

Handling this with TCG_COND_ALWAYS will allow these unlikely
cases to be handled without special cases in the rest of the
translator.  The TCG optimizer ought to be able to reduce
these ALWAYS conditions completely.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 259cb68491ab36427e7e5d820fe543d53b006ec6
      
https://github.com/qemu/qemu/commit/259cb68491ab36427e7e5d820fe543d53b006ec6
  Author: Richard Henderson <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: Use setcond and movcond for csel

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7dd03d773e0dafae9271318fc8d6b2b14de74403
      
https://github.com/qemu/qemu/commit/7dd03d773e0dafae9271318fc8d6b2b14de74403
  Author: Richard Henderson <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: Implement ccmp branchless

This can allow much of a ccmp to be elided when particular
flags are subsequently dead.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6e061029d74455d83f6fa070ac33de7a356cf60d
      
https://github.com/qemu/qemu/commit/6e061029d74455d83f6fa070ac33de7a356cf60d
  Author: Richard Henderson <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: Implement fcsel with movcond

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ef60151bee9a95e3a5cc98b345a19ed7eb435ddb
      
https://github.com/qemu/qemu/commit/ef60151bee9a95e3a5cc98b345a19ed7eb435ddb
  Author: Richard Henderson <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: Recognize SXTB, SXTH, SXTW, ASR

These are all special case aliases of SBFM.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9924e85829fe21b5f38a5d267c9aea44c5d478ac
      
https://github.com/qemu/qemu/commit/9924e85829fe21b5f38a5d267c9aea44c5d478ac
  Author: Richard Henderson <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: Recognize UXTB, UXTH, LSR, LSL

These are all special case aliases of UBFM.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d3a77b42decd0cbfa62a5526e67d1d6d380c83a9
      
https://github.com/qemu/qemu/commit/d3a77b42decd0cbfa62a5526e67d1d6d380c83a9
  Author: Richard Henderson <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: Eliminate unnecessary zero-extend in disas_bitfield

For !SF, this initial ext32u can't be optimized away by the
current TCG code generator.  (It would require backward bit
liveness propagation.)

But since the range of bits for !SF are already constrained by
unallocated_encoding, we'll never reference the high bits anyway.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8fb0ad8e16ab3d03433244a1a03e1df757342ad8
      
https://github.com/qemu/qemu/commit/8fb0ad8e16ab3d03433244a1a03e1df757342ad8
  Author: Richard Henderson <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: Recognize ROR

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7cb36e18b2f1c1f971ebdc2121de22a8c2e94fd6
      
https://github.com/qemu/qemu/commit/7cb36e18b2f1c1f971ebdc2121de22a8c2e94fd6
  Author: Richard Henderson <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: Use tcg_gen_extrh_i64_i32

Usually, eliminate an operation from the translator by combining
a shift with an extract.

In the case of gen_set_NZ64, we don't need a boolean value for cpu_ZF,
merely a non-zero value.  Given that we can extract both halves of a
64-bit input in one call, this simplifies the code.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f4427280977902273f98280b2572d88b6ed53144
      
https://github.com/qemu/qemu/commit/f4427280977902273f98280b2572d88b6ed53144
  Author: Jean-Christophe Dubois <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M hw/gpio/Makefile.objs
    A hw/gpio/imx_gpio.c
    A include/hw/gpio/imx_gpio.h

  Log Message:
  -----------
  i.MX: Add GPIO device

Signed-off-by: Jean-Christophe Dubois <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dde0c4ca6b849eb5c376f255767c019bb45a1d57
      
https://github.com/qemu/qemu/commit/dde0c4ca6b849eb5c376f255767c019bb45a1d57
  Author: Jean-Christophe Dubois <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M hw/arm/fsl-imx31.c
    M include/hw/arm/fsl-imx31.h

  Log Message:
  -----------
  i.MX: Add GPIO devices to i.MX31 SOC

Signed-off-by: Jean-Christophe Dubois <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6abc7158cb62e559ce7b3a99e116e3ec051a0c45
      
https://github.com/qemu/qemu/commit/6abc7158cb62e559ce7b3a99e116e3ec051a0c45
  Author: Jean-Christophe Dubois <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M hw/arm/fsl-imx25.c
    M include/hw/arm/fsl-imx25.h

  Log Message:
  -----------
  i.MX: Add GPIO devices to i.MX25 SOC

Signed-off-by: Jean-Christophe Dubois <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6533a1fcc2efa08570aa6d85851638783dddf2c6
      
https://github.com/qemu/qemu/commit/6533a1fcc2efa08570aa6d85851638783dddf2c6
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M hw/cpu/a15mpcore.c
    M hw/cpu/a9mpcore.c

  Log Message:
  -----------
  hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully

Handle missing CPU support for EL3 gracefully.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 68e9c2fe65bca7fc1bdc2411923333c3e87544a3
      
https://github.com/qemu/qemu/commit/68e9c2fe65bca7fc1bdc2411923333c3e87544a3
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add VTCR_EL2

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: fixed typo in comment]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b698e9cfd282b228b36d426b75facb83e07a1072
      
https://github.com/qemu/qemu/commit/b698e9cfd282b228b36d426b75facb83e07a1072
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add VTTBR_EL2

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1edee4708a0e3163cbf20fac325be456abd960bb
      
https://github.com/qemu/qemu/commit/1edee4708a0e3163cbf20fac325be456abd960bb
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Suppress TBI for S2 translations

Stage-2 MMU translations do not have configurable TBI as
the top byte is always 0 (48-bit IPAs).

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0c5fbf3b4c1e5210354de71a3dc2ebc8c8a01f31
      
https://github.com/qemu/qemu/commit/0c5fbf3b4c1e5210354de71a3dc2ebc8c8a01f31
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Suppress EPD for S2, EL2 and EL3 translations

Stage-2 translations, EL2 and EL3 regimes don't have the
EPD control.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 731de9e60074620aa7d565f01f989adacd493514
      
https://github.com/qemu/qemu/commit/731de9e60074620aa7d565f01f989adacd493514
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add VPIDR_EL2

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 06a7e6477c129ceaa72bd400cf281d44c456be43
      
https://github.com/qemu/qemu/commit/06a7e6477c129ceaa72bd400cf281d44c456be43
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Break out mpidr_read_val()

Break out mpidr_read_val() to allow future sharing of the
code that conditionally sets the M and U bits of MPIDR.

No functional changes.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f0d574d63f4603ec431f16ad535a555bf7548b94
      
https://github.com/qemu/qemu/commit/f0d574d63f4603ec431f16ad535a555bf7548b94
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add VMPIDR_EL2

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7e4804dafd4689312ef1172b549927a973bb5414
      
https://github.com/qemu/qemu/commit/7e4804dafd4689312ef1172b549927a973bb5414
  Author: Peter Maydell <address@hidden>
  Date:   2015-09-14 (Mon, 14 Sep 2015)

  Changed paths:
    M hw/arm/fsl-imx25.c
    M hw/arm/fsl-imx31.c
    M hw/arm/xlnx-zynqmp.c
    M hw/cpu/a15mpcore.c
    M hw/cpu/a9mpcore.c
    M hw/gpio/Makefile.objs
    A hw/gpio/imx_gpio.c
    M include/hw/arm/fsl-imx25.h
    M include/hw/arm/fsl-imx31.h
    M include/hw/arm/xlnx-zynqmp.h
    A include/hw/gpio/imx_gpio.h
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150914' 
into staging

target-arm queue:
 * fix GIC region size in xlnx-zynqmp
 * xlnx-zynqmp: Remove unnecessary brackets
 * improve A64 generated TCG code
 * add GPIO devices to i.MX25 and i.MX31
 * more missing pieces for EL2 support

# gpg: Signature made Mon 14 Sep 2015 14:51:12 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20150914: (24 commits)
  target-arm: Add VMPIDR_EL2
  target-arm: Break out mpidr_read_val()
  target-arm: Add VPIDR_EL2
  target-arm: Suppress EPD for S2, EL2 and EL3 translations
  target-arm: Suppress TBI for S2 translations
  target-arm: Add VTTBR_EL2
  target-arm: Add VTCR_EL2
  hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully
  i.MX: Add GPIO devices to i.MX25 SOC
  i.MX: Add GPIO devices to i.MX31 SOC
  i.MX: Add GPIO device
  target-arm: Use tcg_gen_extrh_i64_i32
  target-arm: Recognize ROR
  target-arm: Eliminate unnecessary zero-extend in disas_bitfield
  target-arm: Recognize UXTB, UXTH, LSR, LSL
  target-arm: Recognize SXTB, SXTH, SXTW, ASR
  target-arm: Implement fcsel with movcond
  target-arm: Implement ccmp branchless
  target-arm: Use setcond and movcond for csel
  target-arm: Handle always condition codes within arm_test_cc
  ...

Signed-off-by: Peter Maydell <address@hidden>


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