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[Qemu-commits] [qemu/qemu] b45c03: arm: Use g_new() & friends where that
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[Qemu-commits] [qemu/qemu] b45c03: arm: Use g_new() & friends where that makes obviou... |
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Date: |
Mon, 07 Sep 2015 03:30:08 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: b45c03f585ea9bb1af76c73e82195418c294919d
https://github.com/qemu/qemu/commit/b45c03f585ea9bb1af76c73e82195418c294919d
Author: Markus Armbruster <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M hw/arm/omap1.c
M hw/arm/omap2.c
M hw/arm/pxa2xx.c
M hw/arm/stellaris.c
M hw/arm/strongarm.c
M hw/char/omap_uart.c
M hw/display/omap_dss.c
M hw/display/omap_lcdc.c
M hw/dma/omap_dma.c
M hw/gpio/omap_gpio.c
M hw/input/stellaris_input.c
M hw/misc/omap_clk.c
M hw/misc/omap_gpmc.c
M hw/misc/omap_sdrc.c
M hw/sd/omap_mmc.c
M hw/ssi/omap_spi.c
M hw/timer/omap_gptimer.c
Log Message:
-----------
arm: Use g_new() & friends where that makes obvious sense
g_new(T, n) is neater than g_malloc(sizeof(T) * n). It's also safer,
for two reasons. One, it catches multiplication overflowing size_t.
Two, it returns T * rather than void *, which lets the compiler catch
more type errors.
This commit only touches allocations with size arguments of the form
sizeof(T).
Coccinelle semantic patch:
@@
type T;
@@
-g_malloc(sizeof(T))
+g_new(T, 1)
@@
type T;
@@
-g_try_malloc(sizeof(T))
+g_try_new(T, 1)
@@
type T;
@@
-g_malloc0(sizeof(T))
+g_new0(T, 1)
@@
type T;
@@
-g_try_malloc0(sizeof(T))
+g_try_new0(T, 1)
@@
type T;
expression n;
@@
-g_malloc(sizeof(T) * (n))
+g_new(T, n)
@@
type T;
expression n;
@@
-g_try_malloc(sizeof(T) * (n))
+g_try_new(T, n)
@@
type T;
expression n;
@@
-g_malloc0(sizeof(T) * (n))
+g_new0(T, n)
@@
type T;
expression n;
@@
-g_try_malloc0(sizeof(T) * (n))
+g_try_new0(T, n)
@@
type T;
expression p, n;
@@
-g_realloc(p, sizeof(T) * (n))
+g_renew(T, p, n)
@@
type T;
expression p, n;
@@
-g_try_realloc(p, sizeof(T) * (n))
+g_try_renew(T, p, n)
@@
type T;
expression n;
@@
-(T *)g_new(T, n)
+g_new(T, n)
@@
type T;
expression n;
@@
-(T *)g_new0(T, n)
+g_new0(T, n)
@@
type T;
expression p, n;
@@
-(T *)g_renew(T, p, n)
+g_renew(T, p, n)
Signed-off-by: Markus Armbruster <address@hidden>
Reviewed-by: Eric Blake <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 857b55adb77004d9ec9202078b7f1f3a1a076112
https://github.com/qemu/qemu/commit/857b55adb77004d9ec9202078b7f1f3a1a076112
Author: Peter Maydell <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M target-arm/arm-semi.c
Log Message:
-----------
target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb
A spurious trailing "\n" in the gdb syscall format string used
for SYS_WRITE0 meant that gdb would reject the remote syscall,
with the effect that the output from the guest was silently dropped.
Remove the newline so that gdb accepts the packet.
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 205ace55ffff77964e50af08c99639ec47db53f6
https://github.com/qemu/qemu/commit/205ace55ffff77964e50af08c99639ec47db53f6
Author: Christopher Covington <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M target-arm/helper.c
Log Message:
-----------
target-arm: Improve semihosting debug prints
Print semihosting debugging information before the
do_arm_semihosting() call so that angel_SWIreason_ReportException,
which causes the function to not return, gets the same debug prints as
other semihosting calls. Also print out the semihosting call number.
Signed-off-by: Christopher Covington <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Tested-by: Christopher Covington <address@hidden>
Message-id: address@hidden
Commit: 19239b39e7501dedec8d92f0eca79c187685bcce
https://github.com/qemu/qemu/commit/19239b39e7501dedec8d92f0eca79c187685bcce
Author: Peter Maydell <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M gdbstub.c
M include/exec/gdbstub.h
Log Message:
-----------
gdbstub: Implement gdb_do_syscallv()
Implement a variant of the existing gdb_do_syscall() which
takes a va_list.
Signed-off-by: Peter Maydell <address@hidden>
Tested-by: Christopher Covington <address@hidden>
Message-id: address@hidden
Commit: bb19cbc95ada89ce5e02c132bc6f3268b1a1bfa3
https://github.com/qemu/qemu/commit/bb19cbc95ada89ce5e02c132bc6f3268b1a1bfa3
Author: Peter Maydell <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M target-arm/arm-semi.c
Log Message:
-----------
target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]'
Factor out a repeated pattern in the semihosting code:
gdb_do_syscall(arm_semi_cb, "system,%s", arg0, (int)arg1+1);
/* arm_semi_cb sets env->regs[0] to the syscall return value */
return env->regs[0];
For A64 the return value will go in a different register; pull
the sequence out into its own function that passes the return
value in a static variable rather than overloading regs[0]
for the purpose, so the code will work on both A32/T32 and A64.
Note that the lack-of-synchronization bug noted in the FIXME
comment is not introduced by this commit, but was already present.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Christopher Covington <address@hidden>
Tested-by: Christopher Covington <address@hidden>
Message-id: address@hidden
Commit: 44d4a499b79d12d5c29f32bf2070c89335573c03
https://github.com/qemu/qemu/commit/44d4a499b79d12d5c29f32bf2070c89335573c03
Author: Peter Maydell <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M include/exec/softmmu-semi.h
Log Message:
-----------
include/exec/softmmu-semi.h: Add support for 64-bit values
Add support for getting and setting 64-bit values in the
softmmu semihosting support functions. This will be needed
for 64-bit ARM semihosting.
Signed-off-by: Peter Maydell <address@hidden>
Tested-by: Christopher Covington <address@hidden>
Message-id: address@hidden
Commit: faacc041619581c566c21ed87aa1933420731282
https://github.com/qemu/qemu/commit/faacc041619581c566c21ed87aa1933420731282
Author: Peter Maydell <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M target-arm/arm-semi.c
M target-arm/cpu.h
Log Message:
-----------
target-arm/arm-semi.c: Support widening APIs to 64 bits
The 64-bit A64 semihosting API has some pervasive changes from
the 32-bit version:
* all parameter blocks are arrays of 64-bit values, not 32-bit
* the semihosting call number is passed in W0
* the return value is a 64-bit value in X0
Implement the necessary handling for this widening.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Christopher Covington <address@hidden>
Tested-by: Christopher Covington <address@hidden>
Message-id: address@hidden
Commit: e9ebfbfcf31c11fb3bd2fc436fa17ce45a4e7086
https://github.com/qemu/qemu/commit/e9ebfbfcf31c11fb3bd2fc436fa17ce45a4e7086
Author: Peter Maydell <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M target-arm/arm-semi.c
Log Message:
-----------
target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call
The A64 semihosting ABI defines a new call SyncCacheRange
for doing a 'clean D-cache and invalidate I-cache' sequence.
Since QEMU doesn't implement caches, we can implement this as a nop.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Christopher Covington <address@hidden>
Tested-by: Christopher Covington <address@hidden>
Message-id: address@hidden
Commit: 7446d35e1dd69e1da8241277eae09e293741b362
https://github.com/qemu/qemu/commit/7446d35e1dd69e1da8241277eae09e293741b362
Author: Peter Maydell <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M target-arm/arm-semi.c
Log Message:
-----------
target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block
The A64 semihosting API changes the interface for SYS_EXIT so
that instead of taking a single exception type in a register,
it takes a parameter block containing the exception type and
a sub-code. Implement this.
Signed-off-by: Peter Maydell <address@hidden>
Tested-by: Christopher Covington <address@hidden>
Message-id: address@hidden
Commit: 8012c84ff92a36d05dfe61af9b24dd01a7ea25e4
https://github.com/qemu/qemu/commit/8012c84ff92a36d05dfe61af9b24dd01a7ea25e4
Author: Peter Maydell <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M linux-user/main.c
M target-arm/cpu.h
M target-arm/helper-a64.c
M target-arm/internals.h
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
For the A64 instruction set, the semihosting call instruction
is 'HLT 0xf000'. Wire this up to call do_arm_semihosting()
if semihosting is enabled.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Christopher Covington <address@hidden>
Tested-by: Christopher Covington <address@hidden>
Message-id: address@hidden
Commit: 86299120060f734a2f7c1137a46de0b8c78135b7
https://github.com/qemu/qemu/commit/86299120060f734a2f7c1137a46de0b8c78135b7
Author: Wei Huang <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/smbios/smbios.c
M include/hw/smbios/smbios.h
M tests/bios-tables-test.c
Log Message:
-----------
smbios: add smbios 3.0 support
This patch adds support for SMBIOS 3.0 entry point. When caller invokes
smbios_set_defaults(), it can specify entry point as 2.1 or 3.0. Then
smbios_get_tables() will return the entry point table in right format.
Acked-by: Gabriel Somlo <address@hidden>
Tested-by: Gabriel Somlo <address@hidden>
Tested-by: Leif Lindholm <address@hidden>
Signed-off-by: Wei Huang <address@hidden>
Reviewed-by: Laszlo Ersek <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: c30e15658b1b3dc9c241a515322ca5dc6fa6b4fe
https://github.com/qemu/qemu/commit/c30e15658b1b3dc9c241a515322ca5dc6fa6b4fe
Author: Wei Huang <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M default-configs/arm-softmmu.mak
M hw/arm/virt.c
M qemu-options.hx
Log Message:
-----------
smbios: implement smbios support for mach-virt
This patch generates smbios tables for ARM mach-virt. Also add
CONFIG_SMBIOS=y for ARM default config.
Acked-by: Gabriel Somlo <address@hidden>
Tested-by: Gabriel Somlo <address@hidden>
Reviewed-by: Laszlo Ersek <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Leif Lindholm <address@hidden>
Signed-off-by: Wei Huang <address@hidden>
Message-id: address@hidden
[PMM: Added missing braces around an if().]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: f128bf297ba100877313cb3e9c0da845da0bb58c
https://github.com/qemu/qemu/commit/f128bf297ba100877313cb3e9c0da845da0bb58c
Author: Peter Crosthwaite <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M target-arm/cpu.c
Log Message:
-----------
arm: cpu: assert() on no-EL2 virt IRQ error condition.
Replace the hw_error() for no-EL2 VIRQ with an assert.
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 8f6fd322f6e25995629a1a07b56bc5b91fb947ca
https://github.com/qemu/qemu/commit/8f6fd322f6e25995629a1a07b56bc5b91fb947ca
Author: Peter Crosthwaite <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M target-arm/cpu.c
M target-arm/helper.c
Log Message:
-----------
arm: Remove hw_error() usages.
All of these hw_errors are fatal and indicate something wrong with
QEMU implementation.
Convert to g_assert_not_reached.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 3a9148d0bdcee990fbe86759b9b1f5723c1d7fbc
https://github.com/qemu/qemu/commit/3a9148d0bdcee990fbe86759b9b1f5723c1d7fbc
Author: Sergey Sorokin <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M target-arm/helper.c
Log Message:
-----------
target-arm: Fix AArch32:AArch64 general-purpose register mapping
There is an error in functions aarch64_sync_32_to_64() and
aarch64_sync_64_to_32() with mapping of registers between AArch32 and
AArch64. This commit fixes the mapping to match the v8 ARM ARM
section D1.20.1 (table D1-77).
Signed-off-by: Sergey Sorokin <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: tidied commit message a bit]
Signed-off-by: Peter Maydell <address@hidden>
Commit: 5125f9cd2532f0aca25d966ecd27d0e30d4af7c9
https://github.com/qemu/qemu/commit/5125f9cd2532f0aca25d966ecd27d0e30d4af7c9
Author: Pavel Fedin <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M include/hw/arm/virt-acpi-build.h
M include/hw/arm/virt.h
Log Message:
-----------
hw/arm/virt: Add high MMIO PCI region, 512G in size
This large region is necessary for some devices like ivshmem and video cards
32-bit kernels can be built without LPAE support. In this case such a kernel
will not be able to use PCI controller which has windows in high addresses.
In order to work around the problem, "highmem" option is introduced. It
defaults to on on, but can be manually set to off in order to be able to run
those old 32-bit guests.
Signed-off-by: Pavel Fedin <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
[PMM: Added missing ULL suffixes and a comment to the a15memmap[] entry]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 771842585f3119f69641ed90a97d56eb9ed6f5ae
https://github.com/qemu/qemu/commit/771842585f3119f69641ed90a97d56eb9ed6f5ae
Author: Sergey Sorokin <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M target-arm/cpu.h
Log Message:
-----------
target-arm: Fix arm_excp_unmasked() function
There is an error in arm_excp_unmasked() function:
bitwise operator & is used with integer and bool operands
causing an incorrect zeroed result.
The patch fixes it.
Signed-off-by: Sergey Sorokin <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 558df83db778dc2e839353357a508349b180d79b
https://github.com/qemu/qemu/commit/558df83db778dc2e839353357a508349b180d79b
Author: Jean-Christophe Dubois <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M default-configs/arm-softmmu.mak
M hw/arm/Makefile.objs
A hw/arm/fsl-imx31.c
A include/hw/arm/fsl-imx31.h
Log Message:
-----------
i.MX: Add SOC support for i.MX31
For now we support the following devices:
* CPU: ARM1136
* Interrupt Controller: AVIC
* CCM
* UART x 2
* EPIT x 2
* GPT
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f044ac4980922e23b608afc2f35648ebadb42950
https://github.com/qemu/qemu/commit/f044ac4980922e23b608afc2f35648ebadb42950
Author: Jean-Christophe Dubois <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M hw/arm/kzm.c
M hw/char/imx_serial.c
M hw/timer/imx_epit.c
M hw/timer/imx_gpt.c
R include/hw/arm/imx.h
Log Message:
-----------
i.MX: KZM: use standalone i.MX31 SOC support
Convert the KZM board to use the i.MX31 SoC defintition instead of
redefining the entire SoC on the machine level. Major rewrite of the
machine init code.
While touching the memory map comment de-indent to the correct level
of indentation.
This obsoletes the legacy i.MX device device creation helpers which are removed.
Tested by booting a minimal Linux system on the emulated platform
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 20d0f9cf6a41bad52baba3ebc485849617cc42cf
https://github.com/qemu/qemu/commit/20d0f9cf6a41bad52baba3ebc485849617cc42cf
Author: Jean-Christophe Dubois <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M default-configs/arm-softmmu.mak
M hw/i2c/Makefile.objs
A hw/i2c/imx_i2c.c
A include/hw/i2c/imx_i2c.h
Log Message:
-----------
i.MX: Add I2C controller emulator
The slave mode is not implemented.
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: fcbd8018e645f3ab1ef9af94dc88a0d3272926d3
https://github.com/qemu/qemu/commit/fcbd8018e645f3ab1ef9af94dc88a0d3272926d3
Author: Jean-Christophe Dubois <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M default-configs/arm-softmmu.mak
M hw/net/Makefile.objs
A hw/net/imx_fec.c
A include/hw/net/imx_fec.h
Log Message:
-----------
i.MX: Add FEC Ethernet Emulator
This is based on mcf_fec.c FEC implementation for Coldfire
* A generic PHY was added (borrowwed from LAN9118)
* The buffer management is also modified as buffers are
slightly different between Coldfire and i.MX
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: ee708c999d45e3f742d2f1287694a1b9da87044b
https://github.com/qemu/qemu/commit/ee708c999d45e3f742d2f1287694a1b9da87044b
Author: Jean-Christophe Dubois <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M default-configs/arm-softmmu.mak
M hw/arm/Makefile.objs
A hw/arm/fsl-imx25.c
A include/hw/arm/fsl-imx25.h
Log Message:
-----------
i.MX: Add SOC support for i.MX25
For now we support the following devices:
* CPU: ARM926
* Interrupt Controller: AVIC
* CCM
* UART x 5
* EPIT x 2
* GPT x 4
* FEC
* I2C x 3
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 65f57c43632b102f8b1ef20baf1fc218c6b8d9cd
https://github.com/qemu/qemu/commit/65f57c43632b102f8b1ef20baf1fc218c6b8d9cd
Author: Jean-Christophe Dubois <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M hw/arm/Makefile.objs
A hw/arm/imx25_pdk.c
Log Message:
-----------
i.MX: Add the i.MX25 PDK platform
Tested by booting a minimal Linux system on the emulated platform
Tested by booting the Xvisor hypervisor on the emulated platform
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7f3986278b0bc214e83111ea55c8d12bac79c4fa
https://github.com/qemu/qemu/commit/7f3986278b0bc214e83111ea55c8d12bac79c4fa
Author: Jean-Christophe Dubois <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M include/hw/arm/fsl-imx31.h
M tests/Makefile
A tests/ds1338-test.c
A tests/libqos/i2c-imx.c
M tests/libqos/i2c.h
Log Message:
-----------
i.MX: Add qtest support for I2C device emulator.
This is using a ds1338 RTC chip on the I2C bus. This RTC chip is
not present on the real 3DS PDK board.
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Acked-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d4e26d106a1ea35a81176cb5398406b08316adc7
https://github.com/qemu/qemu/commit/d4e26d106a1ea35a81176cb5398406b08316adc7
Author: Jean-Christophe Dubois <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M hw/arm/fsl-imx31.c
M include/hw/arm/fsl-imx31.h
Log Message:
-----------
i.MX: Add i2C devices to i.MX31 SOC
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 0f4a9e45ec35811ee250ac232d84d3c6d4fcd7fc
https://github.com/qemu/qemu/commit/0f4a9e45ec35811ee250ac232d84d3c6d4fcd7fc
Author: Pavel Fedin <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M target-arm/cpu-qom.h
M target-arm/cpu.c
M target-arm/kvm32.c
M target-arm/kvm64.c
Log Message:
-----------
target-arm: Refactor CPU affinity handling
Introduces reusable definitions for CPU affinity masks/shifts and gets rid
of hardcoded magic numbers.
Signed-off-by: Pavel Fedin <address@hidden>
Message-id: address@hidden
[PMM: folded overlong line]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 8d45c54d4fd3612bd616afcc5c278394f312927b
https://github.com/qemu/qemu/commit/8d45c54d4fd3612bd616afcc5c278394f312927b
Author: Pavel Fedin <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
arm/virt: Add full-sized CPU affinity handling
At least with KVM, currently there's no reason why QEMU would not be
capable of handling Aff3 != 0. This commit fixes up FDT creation in such
a case.
Signed-off-by: Pavel Fedin <address@hidden>
Message-id: address@hidden
[PMM: folded two overlong lines]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 298fae38972cc0165415ead04b64bfcae55640d9
https://github.com/qemu/qemu/commit/298fae38972cc0165415ead04b64bfcae55640d9
Author: Peter Maydell <address@hidden>
Date: 2015-09-07 (Mon, 07 Sep 2015)
Changed paths:
M default-configs/arm-softmmu.mak
M gdbstub.c
M hw/arm/Makefile.objs
A hw/arm/fsl-imx25.c
A hw/arm/fsl-imx31.c
A hw/arm/imx25_pdk.c
M hw/arm/kzm.c
M hw/arm/omap1.c
M hw/arm/omap2.c
M hw/arm/pxa2xx.c
M hw/arm/stellaris.c
M hw/arm/strongarm.c
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M hw/char/imx_serial.c
M hw/char/omap_uart.c
M hw/display/omap_dss.c
M hw/display/omap_lcdc.c
M hw/dma/omap_dma.c
M hw/gpio/omap_gpio.c
M hw/i2c/Makefile.objs
A hw/i2c/imx_i2c.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/input/stellaris_input.c
M hw/misc/omap_clk.c
M hw/misc/omap_gpmc.c
M hw/misc/omap_sdrc.c
M hw/net/Makefile.objs
A hw/net/imx_fec.c
M hw/sd/omap_mmc.c
M hw/smbios/smbios.c
M hw/ssi/omap_spi.c
M hw/timer/imx_epit.c
M hw/timer/imx_gpt.c
M hw/timer/omap_gptimer.c
M include/exec/gdbstub.h
M include/exec/softmmu-semi.h
A include/hw/arm/fsl-imx25.h
A include/hw/arm/fsl-imx31.h
R include/hw/arm/imx.h
M include/hw/arm/virt-acpi-build.h
M include/hw/arm/virt.h
A include/hw/i2c/imx_i2c.h
A include/hw/net/imx_fec.h
M include/hw/smbios/smbios.h
M linux-user/main.c
M qemu-options.hx
M target-arm/arm-semi.c
M target-arm/cpu-qom.h
M target-arm/cpu.c
M target-arm/cpu.h
M target-arm/helper-a64.c
M target-arm/helper.c
M target-arm/internals.h
M target-arm/kvm32.c
M target-arm/kvm64.c
M target-arm/translate-a64.c
M tests/Makefile
M tests/bios-tables-test.c
A tests/ds1338-test.c
A tests/libqos/i2c-imx.c
M tests/libqos/i2c.h
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150907'
into staging
target-arm queue:
* cleanup to use g_new() and friends
* support semihosting in A64
* add SMBIOS support to mach-virt
* remove hw_error() usages
* fix bug in the AArch32:AArch64 register mapping
* add a second PCI memory window in highmem on virt board
* fix bug in arm_excp_unmasked()
* add i.MX31 SoC
* remove restriction on handling affinity values in virt board
# gpg: Signature made Mon 07 Sep 2015 10:40:48 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
* remotes/pmaydell/tags/pull-target-arm-20150907: (27 commits)
arm/virt: Add full-sized CPU affinity handling
target-arm: Refactor CPU affinity handling
i.MX: Add i2C devices to i.MX31 SOC
i.MX: Add qtest support for I2C device emulator.
i.MX: Add the i.MX25 PDK platform
i.MX: Add SOC support for i.MX25
i.MX: Add FEC Ethernet Emulator
i.MX: Add I2C controller emulator
i.MX: KZM: use standalone i.MX31 SOC support
i.MX: Add SOC support for i.MX31
target-arm: Fix arm_excp_unmasked() function
hw/arm/virt: Add high MMIO PCI region, 512G in size
target-arm: Fix AArch32:AArch64 general-purpose register mapping
arm: Remove hw_error() usages.
arm: cpu: assert() on no-EL2 virt IRQ error condition.
smbios: implement smbios support for mach-virt
smbios: add smbios 3.0 support
target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block
target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/b597aa037dbd...298fae38972c
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