[Qemu-commits] [qemu/qemu] aff2bc: target-mips: update mips32r5-generic into P5600

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: aff2bc6dc6d839caf6df0900437cc2cc9e180605
      
https://github.com/qemu/qemu/commit/aff2bc6dc6d839caf6df0900437cc2cc9e180605
  Author: Yongbok Kim <address@hidden>
  Date:   2015-08-13 (Thu, 13 Aug 2015)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: update mips32r5-generic into P5600

As full specification of P5600 is available, mips32r5-generic should
be renamed to P5600 and corrected as its intention.
Correct PRid and detail of configuration.
Features which are not currently supported are described as FIXME.

Fix Config.MM bit location

Signed-off-by: Yongbok Kim <address@hidden>
address@hidden: correct cache line sizes and LLAddr shift]
Signed-off-by: Leon Alrae <address@hidden>


  Commit: eb02cc3f89013612cb05df23b5441741e902bbd2
      
https://github.com/qemu/qemu/commit/eb02cc3f89013612cb05df23b5441741e902bbd2
  Author: Aurelien Jarno <address@hidden>
  Date:   2015-08-13 (Thu, 13 Aug 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: simplify LWL/LDL mask generation

The LWL/LDL instructions mask the GPR with a mask depending on the
address alignement. It is currently computed by doing:

    mask = 0x7fffffffffffffffull >> (t1 ^ 63)

It's simpler to generate it by doing:

    mask = ~(-1 << t1)

It uses one TCG instruction less, and it avoids a 32/64-bit constant
loading which can take a few instructions on RISC hosts.

Cc: Leon Alrae <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 58d479786b11a7e982419c1e0905b8490ef9a787
      
https://github.com/qemu/qemu/commit/58d479786b11a7e982419c1e0905b8490ef9a787
  Author: Peter Maydell <address@hidden>
  Date:   2015-08-13 (Thu, 13 Aug 2015)

  Changed paths:
    M hw/pci-host/bonito.c

  Log Message:
  -----------
  hw/pci-host/bonito: Avoid buffer overrun for bad LDMA/COP accesses

The LDMA and COP memory regions represent four 32 bit registers
each, but the memory regions themselves are 0x100 bytes large.
Add guards to the read and write accessors so that bogus accesses
beyond the four defined registers don't just run off the end of
the bonldma and boncop structs and into whatever lies beyond.

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: c85570163bdf1ba29cb52a63f22ff1c48f1b9398
      
https://github.com/qemu/qemu/commit/c85570163bdf1ba29cb52a63f22ff1c48f1b9398
  Author: Richard Henderson <address@hidden>
  Date:   2015-08-13 (Thu, 13 Aug 2015)

  Changed paths:
    M target-mips/helper.c
    M target-mips/op_helper.c

  Log Message:
  -----------
  target-mips: Use CPU_LOG_INT for logging related to interrupts

There are now no unconditional uses of qemu_log in the subdirectory.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: be1f13ac9d9fc21908975460652a72f5f0c018c5
      
https://github.com/qemu/qemu/commit/be1f13ac9d9fc21908975460652a72f5f0c018c5
  Author: Peter Maydell <address@hidden>
  Date:   2015-08-13 (Thu, 13 Aug 2015)

  Changed paths:
    M hw/pci-host/bonito.c
    M target-mips/cpu.h
    M target-mips/helper.c
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150813' into staging

MIPS patches 2015-08-13

Changes:
* mips32r5-generic CPU updated and renamed to P5600
* improvements in LWL/LDL, logging and fulong2e

# gpg: Signature made Thu 13 Aug 2015 17:10:59 BST using RSA key ID 0B29DA6B
# gpg: Good signature from "Leon Alrae <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4  4FC0 5211 8E3C 0B29 DA6B

* remotes/lalrae/tags/mips-20150813:
  target-mips: Use CPU_LOG_INT for logging related to interrupts
  hw/pci-host/bonito: Avoid buffer overrun for bad LDMA/COP accesses
  target-mips: simplify LWL/LDL mask generation
  target-mips: update mips32r5-generic into P5600

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/5c314a2eb713...be1f13ac9d9f