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[Qemu-commits] [qemu/qemu] 4dc89b: target-mips: fix MIPS64R6-generic con

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 4dc89b: target-mips: fix MIPS64R6-generic configuration
Date: Thu, 16 Jul 2015 04:00:05 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 4dc89b782095d7a0b919fafd7b1322b3cb1279f1
      
https://github.com/qemu/qemu/commit/4dc89b782095d7a0b919fafd7b1322b3cb1279f1
  Author: Yongbok Kim <address@hidden>
  Date:   2015-07-15 (Wed, 15 Jul 2015)

  Changed paths:
    M target-mips/mips-defs.h
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: fix MIPS64R6-generic configuration

Fix core configuration for MIPS64R6-generic to make it as close as
I6400.
I6400 core has 48-bit of Virtual Address available (SEGBITS).
MIPS SIMD Architecture is available.
Rearrange order of bits to match the specification.

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: d4f4f0d5d9e74c19614479592c8bc865d92773d0
      
https://github.com/qemu/qemu/commit/d4f4f0d5d9e74c19614479592c8bc865d92773d0
  Author: Yongbok Kim <address@hidden>
  Date:   2015-07-15 (Wed, 15 Jul 2015)

  Changed paths:
    M target-mips/msa_helper.c

  Log Message:
  -----------
  target-mips: fix to clear MSACSR.Cause

MSACSR.Cause bits are needed to be cleared before a vector floating-point
instructions.
FEXDO.df, FEXUPL.df and FEXUPR.df were missed out.

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 6b9c26fb5eed2345398daca4eef601da2f3d7867
      
https://github.com/qemu/qemu/commit/6b9c26fb5eed2345398daca4eef601da2f3d7867
  Author: Yongbok Kim <address@hidden>
  Date:   2015-07-15 (Wed, 15 Jul 2015)

  Changed paths:
    M disas/mips.c

  Log Message:
  -----------
  disas/mips: fix disassembling R6 instructions

In the Release 6 of the MIPS Architecture, LL, SC, LLD, SCD, PREF
and CACHE instructions have 9 bits offsets.

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 6a973e6b6584221bed89a01e755b88e58b496652
      
https://github.com/qemu/qemu/commit/6a973e6b6584221bed89a01e755b88e58b496652
  Author: Aurelien Jarno <address@hidden>
  Date:   2015-07-15 (Wed, 15 Jul 2015)

  Changed paths:
    M target-mips/op_helper.c

  Log Message:
  -----------
  target-mips: fix ASID synchronisation for MIPS MT

When syncing the task ASID with EntryHi, correctly or the value instead
of assigning it.

Reported-by: "Dr. David Alan Gilbert" <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Cc: Leon Alrae <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: fe87c2b36ae9c1c9a5279f3891f3bce1b573baa0
      
https://github.com/qemu/qemu/commit/fe87c2b36ae9c1c9a5279f3891f3bce1b573baa0
  Author: Leon Alrae <address@hidden>
  Date:   2015-07-15 (Wed, 15 Jul 2015)

  Changed paths:
    M target-mips/op_helper.c

  Log Message:
  -----------
  target-mips: correct DERET instruction

Fix Debug Mode flag clearing, and when DERET is placed between LL and SC
do not make SC fail.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: 47ada0ad3431b39863918dc80386634693d317b5
      
https://github.com/qemu/qemu/commit/47ada0ad3431b39863918dc80386634693d317b5
  Author: Leon Alrae <address@hidden>
  Date:   2015-07-15 (Wed, 15 Jul 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: fix logically dead code reported by Coverity

Make use of CMPOP in floating-point compare instructions.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: 26e7e982b267e71d40cd20e9e234fedef6770a90
      
https://github.com/qemu/qemu/commit/26e7e982b267e71d40cd20e9e234fedef6770a90
  Author: Leon Alrae <address@hidden>
  Date:   2015-07-15 (Wed, 15 Jul 2015)

  Changed paths:
    M target-mips/mips-semi.c

  Log Message:
  -----------
  target-mips: fix resource leak reported by Coverity

UHI assert and link operations call lock_user_string() twice to obtain two
strings pointed by gpr[4] and gpr[5]. If the second lock_user_string()
fails, then the first one won't get freed. Fix this by introducing another
macro responsible for obtaining two strings and handling allocation
failure.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: f01a361bfcce4bd0c439b0e051ef2a1e56727a44
      
https://github.com/qemu/qemu/commit/f01a361bfcce4bd0c439b0e051ef2a1e56727a44
  Author: Andrew Bennett <address@hidden>
  Date:   2015-07-15 (Wed, 15 Jul 2015)

  Changed paths:
    M linux-user/main.c

  Log Message:
  -----------
  linux-user: Fix MIPS N64 trap and break instruction bug

For the MIPS N64 ABI when QEMU reads the break/trap instruction so that
it can inspect the break/trap code it reads 8 rather than 4 bytes
which means it finds the code field from the instruction after the
break/trap instruction.  This then causes the break/trap handling
code to fail because it does not understand the code number.

The fix forces QEMU to always read 4 bytes of instruction data rather
than deciding how much to read based on the ABI.

Signed-off-by: Andrew Bennett <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 908680c6441ac468f4871d513f42be396ea0d264
      
https://github.com/qemu/qemu/commit/908680c6441ac468f4871d513f42be396ea0d264
  Author: Aurelien Jarno <address@hidden>
  Date:   2015-07-15 (Wed, 15 Jul 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: fix page fault address for LWL/LWR/LDL/LDR

When a LWL, LWR, LDL or LDR instruction triggers a page fault, QEMU
currently reports the aligned address in CP0 BadVAddr, while the Windows
NT kernel expects the unaligned address.

This patch adds a byte access with the unaligned address at the
beginning of the LWL/LWR/LDL/LDR instructions to possibly trigger a page
fault and fill the QEMU TLB.

Cc: Leon Alrae <address@hidden>
Reported-by: Hervé Poussineau <address@hidden>
Tested-by: Hervé Poussineau <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 2d5ee9e7a7dd495d233cf9613a865f63f88e3375
      
https://github.com/qemu/qemu/commit/2d5ee9e7a7dd495d233cf9613a865f63f88e3375
  Author: Peter Maydell <address@hidden>
  Date:   2015-07-16 (Thu, 16 Jul 2015)

  Changed paths:
    M disas/mips.c
    M linux-user/main.c
    M target-mips/mips-defs.h
    M target-mips/mips-semi.c
    M target-mips/msa_helper.c
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150716' into staging

MIPS patches 2015-07-16

Changes:
* bug fixes

# gpg: Signature made Thu Jul 16 09:04:56 2015 BST using RSA key ID 0B29DA6B
# gpg: Good signature from "Leon Alrae <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4  4FC0 5211 8E3C 0B29 DA6B

* remotes/lalrae/tags/mips-20150716:
  target-mips: fix page fault address for LWL/LWR/LDL/LDR
  linux-user: Fix MIPS N64 trap and break instruction bug
  target-mips: fix resource leak reported by Coverity
  target-mips: fix logically dead code reported by Coverity
  target-mips: correct DERET instruction
  target-mips: fix ASID synchronisation for MIPS MT
  disas/mips: fix disassembling R6 instructions
  target-mips: fix to clear MSACSR.Cause
  target-mips: fix MIPS64R6-generic configuration

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/3749c11a7206...2d5ee9e7a7dd
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