[Qemu-commits] [qemu/qemu] 9f6f7c: include/softmmu-semi.h: Make semihost

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[Qemu-commits] [qemu/qemu] 9f6f7c: include/softmmu-semi.h: Make semihost

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 9f6f7c: include/softmmu-semi.h: Make semihosting support 6...
Date:	Fri, 26 Jun 2015 05:30:06 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 9f6f7ca1490563d98003149e6de32caf25c670da
      
https://github.com/qemu/qemu/commit/9f6f7ca1490563d98003149e6de32caf25c670da
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M include/exec/softmmu-semi.h

  Log Message:
  -----------
  include/softmmu-semi.h: Make semihosting support 64-bit clean

Correct addresses passed around in semihosting to use a data type suitable
for both 32-bit and 64-bit targets.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: d6ca4277eee98b3c561e21ac105199891d346d79
      
https://github.com/qemu/qemu/commit/d6ca4277eee98b3c561e21ac105199891d346d79
  Author: Matthew Fortune <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M hw/mips/mips_malta.c

  Log Message:
  -----------
  hw/mips: Do not clear BEV for MIPS malta kernel load

The BEV flag controls whether the boot exception vector is still
in place when starting a kernel.  When cleared the exception vector
at EBASE (or hard coded address of 0x80000000) is used instead.

The early stages of the linux kernel would benefit from BEV still
being set to ensure any faults get handled by the boot rom exception
handlers.  This is a moot point for system qemu as there aren't really
any BEV handlers, but there are other good reasons to change this...

The UHI (semi-hosting interface) defines special behaviours depending
on whether an application starts in an environment with BEV set or
cleared. When BEV is set then UHI assumes that a bootloader is
relatively dumb and has no advanced exception handling logic.
However, when BEV is cleared then UHI assumes that the bootloader
has the ability to handle UHI exceptions with its exception handlers
and will unwind and forward UHI SYSCALL exceptions to the exception
vector that was installed prior to running the application.

Signed-off-by: Matthew Fortune <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: ff334767728011218c62f7476232d260cb5b28e6
      
https://github.com/qemu/qemu/commit/ff334767728011218c62f7476232d260cb5b28e6
  Author: Leon Alrae <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: remove identical code in different branch

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: 3b3c1694cfd394b73de426edebdbf90c28f664fd
      
https://github.com/qemu/qemu/commit/3b3c1694cfd394b73de426edebdbf90c28f664fd
  Author: Leon Alrae <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M hw/mips/mips_malta.c
    M qemu-options.hx
    M target-mips/Makefile.objs
    M target-mips/helper.h
    A target-mips/mips-semi.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add Unified Hosting Interface (UHI) support

Add UHI semihosting support for MIPS. QEMU run with "-semihosting" option
will alter the behaviour of SDBBP 1 instruction -- UHI operation will be
called instead of generating a debug exception.

Also tweak Malta's pseudo-bootloader. On CPU reset the $4 register is set
to -1 if semihosting arguments are passed to indicate that the UHI
operations should be used to obtain input arguments.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: 2c44b19c199f4ce2f1721120744d3d6e5d01d274
      
https://github.com/qemu/qemu/commit/2c44b19c199f4ce2f1721120744d3d6e5d01d274
  Author: Leon Alrae <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M target-mips/mips-semi.c

  Log Message:
  -----------
  target-mips: convert host to MIPS errno values when required

Convert only errno values which can be returned by system calls in
mips-semi.c and are not generic to all archs.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: 1bf5902de03732d4067c4e90171a1741d6542c45
      
https://github.com/qemu/qemu/commit/1bf5902de03732d4067c4e90171a1741d6542c45
  Author: Yongbok Kim <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: fix {RD, WR}PGPR in microMIPS

rt, rs were swapped

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: e60ec06357470db5a0f25901ca19b6237e6da927
      
https://github.com/qemu/qemu/commit/e60ec06357470db5a0f25901ca19b6237e6da927
  Author: Yongbok Kim <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add microMIPS TLBINV, TLBINVF

Add microMIPS TLBINV, TLBINVF

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: f60eeb0c5ddd8ceb8ca6b3ba032159027afab67a
      
https://github.com/qemu/qemu/commit/f60eeb0c5ddd8ceb8ca6b3ba032159027afab67a
  Author: Yongbok Kim <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: remove an unused argument

Remove an unused argument from decode_micromips32_opc()

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 1f1b4c008e250f870719ed38fbd0bcc14322fc01
      
https://github.com/qemu/qemu/commit/1f1b4c008e250f870719ed38fbd0bcc14322fc01
  Author: Yongbok Kim <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAP

Refactor those instructions in order to reuse them for microMIPS32
Release 6.
Rearrange gen_move_low32().

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 6893f07466b045c5faf314ab9e57ef3b4a6f9e49
      
https://github.com/qemu/qemu/commit/6893f07466b045c5faf314ab9e57ef3b4a6f9e49
  Author: Yongbok Kim <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: rearrange gen_compute_compact_branch

The function will be also used for microMIPS Release 6.

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: e29c962804c4dd3fabd44e703aa87eec555ed910
      
https://github.com/qemu/qemu/commit/e29c962804c4dd3fabd44e703aa87eec555ed910
  Author: Yongbok Kim <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: raise RI exceptions when FIR.PS = 0

64-bit paired-single (PS) floating point data type is optional in the
pre-Release 6.
It has to raise RI exception when PS type is not implemented. (FIR.PS = 0)
(The PS data type is removed in the Release 6.)
Loongson-2E and Loongson-2F don't have any implementation field in
FCSR0(FIR) but do support PS data format, therefore for these cores RI will
not be signalled regardless of PS bit.

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 9e8f441a7e094c0dc33a1c8f521d9e5bcfc1b4da
      
https://github.com/qemu/qemu/commit/9e8f441a7e094c0dc33a1c8f521d9e5bcfc1b4da
  Author: Yongbok Kim <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: signal RI for removed instructions in microMIPS R6

Signal a Reserved Instruction exception for removed instruction encoding
in microMIPS Release 6.

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 3a1f426828cd8ffeec1a4fa8ca6ca3ed4f800edb
      
https://github.com/qemu/qemu/commit/3a1f426828cd8ffeec1a4fa8ca6ca3ed4f800edb
  Author: Yongbok Kim <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add microMIPS32 R6 opcode enum

Add microMIPS32 Release 6 opcode enum.
Remove RI checking for pre-R6 reserved opcode.

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 65935f070aa710cf340e96ae7ee36d2c1d5c8d15
      
https://github.com/qemu/qemu/commit/65935f070aa710cf340e96ae7ee36d2c1d5c8d15
  Author: Yongbok Kim <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: microMIPS32 R6 branches and jumps

Add new microMIPS32 Release 6 branch and jump instructions.

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: e03320958305a68f2bc6a32c87d7ed48303438f9
      
https://github.com/qemu/qemu/commit/e03320958305a68f2bc6a32c87d7ed48303438f9
  Author: Yongbok Kim <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: microMIPS32 R6 POOL32A{XF} instructions

Add new microMIPS32 Release 6 pool32a/pool32axf instructions.

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 2a24a7badeb6ad3ba72e7984f299623035d564d6
      
https://github.com/qemu/qemu/commit/2a24a7badeb6ad3ba72e7984f299623035d564d6
  Author: Yongbok Kim <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: microMIPS32 R6 POOL32F instructions

Add new microMIPS32 Release 6 POOL32F instructions

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 3b4a5489447e7ed17cc504572cf729833853e7ab
      
https://github.com/qemu/qemu/commit/3b4a5489447e7ed17cc504572cf729833853e7ab
  Author: Yongbok Kim <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: microMIPS32 R6 POOL32{I, C} instructions

Add new microMIPS32 Release 6 POOL32I/POOL32C type instructions

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: ab39ee452d74855adec91056812b8e1e5166302c
      
https://github.com/qemu/qemu/commit/ab39ee452d74855adec91056812b8e1e5166302c
  Author: Yongbok Kim <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: microMIPS32 R6 Major instructions

Add new microMIPS32 Release 6 Major opcode instructions

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: ed7ce6c0f9d4370826557ce33d652beb88ccb3e6
      
https://github.com/qemu/qemu/commit/ed7ce6c0f9d4370826557ce33d652beb88ccb3e6
  Author: Yongbok Kim <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: microMIPS32 R6 POOL16{A, C} instructions

microMIPS32 Release 6 POOL16A/ POOL16C instructions

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 4b3bcd016d83cc75f6a495c1db54b6c77f037adc
      
https://github.com/qemu/qemu/commit/4b3bcd016d83cc75f6a495c1db54b6c77f037adc
  Author: Yongbok Kim <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: add mips32r6-generic CPU definition

Define a new CPU definition supporting MIPS32 Release 6 ISA and
microMIPS32 Release 6 ISA.

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: ccb0c7e122db72d3a5da798c6414d4912bba828f
      
https://github.com/qemu/qemu/commit/ccb0c7e122db72d3a5da798c6414d4912bba828f
  Author: Peter Maydell <address@hidden>
  Date:   2015-06-26 (Fri, 26 Jun 2015)

  Changed paths:
    M hw/mips/mips_malta.c
    M include/exec/softmmu-semi.h
    M qemu-options.hx
    M target-mips/Makefile.objs
    M target-mips/helper.h
    A target-mips/mips-semi.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150626' into staging

MIPS patches 2015-06-26

Changes:
* MIPS UHI semihosting support
* microMIPS32 R6 support

# gpg: Signature made Fri Jun 26 10:42:33 2015 BST using RSA key ID 0B29DA6B
# gpg: Good signature from "Leon Alrae <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4  4FC0 5211 8E3C 0B29 DA6B

* remotes/lalrae/tags/mips-20150626:
  target-mips: add mips32r6-generic CPU definition
  target-mips: microMIPS32 R6 POOL16{A, C} instructions
  target-mips: microMIPS32 R6 Major instructions
  target-mips: microMIPS32 R6 POOL32{I, C} instructions
  target-mips: microMIPS32 R6 POOL32F instructions
  target-mips: microMIPS32 R6 POOL32A{XF} instructions
  target-mips: microMIPS32 R6 branches and jumps
  target-mips: add microMIPS32 R6 opcode enum
  target-mips: signal RI for removed instructions in microMIPS R6
  target-mips: raise RI exceptions when FIR.PS = 0
  target-mips: rearrange gen_compute_compact_branch
  target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAP
  target-mips: remove an unused argument
  target-mips: add microMIPS TLBINV, TLBINVF
  target-mips: fix {RD, WR}PGPR in microMIPS
  target-mips: convert host to MIPS errno values when required
  target-mips: add Unified Hosting Interface (UHI) support
  target-mips: remove identical code in different branch
  hw/mips: Do not clear BEV for MIPS malta kernel load
  include/softmmu-semi.h: Make semihosting support 64-bit clean

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/0a4a0312bf8b...ccb0c7e122db
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