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[Qemu-commits] [qemu/qemu] 8c52f0: m68k: implement more ColdFire 5208 in


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 8c52f0: m68k: implement more ColdFire 5208 interrupt contr...
Date: Mon, 22 Jun 2015 08:30:08 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 8c52f0cbba76310ad626e54996dbce08c7a8a820
      
https://github.com/qemu/qemu/commit/8c52f0cbba76310ad626e54996dbce08c7a8a820
  Author: Greg Ungerer <address@hidden>
  Date:   2015-06-22 (Mon, 22 Jun 2015)

  Changed paths:
    M hw/m68k/mcf_intc.c

  Log Message:
  -----------
  m68k: implement more ColdFire 5208 interrupt controller functionality

Implement the SIMR and CIMR registers of the 5208 interrupt controller.
These are used by modern versions of Linux running on ColdFire (not sure
of the exact version they were introduced, but they have been in for quite
a while now).

Without this change when attempting to run a linux-3.5 kernel you will
see:

  qemu: hardware error: mcf_intc_write: Bad write offset 28

and execution will stop and dump out.

Signed-off-by: Greg Ungerer <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Tested-by: Laurent Vivier <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2a8327e8a8288e301a2f01bc3ca2d465a3a4ca78
      
https://github.com/qemu/qemu/commit/2a8327e8a8288e301a2f01bc3ca2d465a3a4ca78
  Author: Greg Ungerer <address@hidden>
  Date:   2015-06-22 (Mon, 22 Jun 2015)

  Changed paths:
    M target-m68k/translate.c

  Log Message:
  -----------
  m68k: implement move to/from usp register instruction

Fill out the code support for the move to/from usp instructions. They are
being decoded, but there is no code to support there actions. So add it.

Current versions of Linux running on the ColdFire 5208 use these instructions.

Signed-off-by: Greg Ungerer <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Tested-by: Laurent Vivier <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0c8ff723bd29e5c8b2ca989f857ae5c37ec49c4e
      
https://github.com/qemu/qemu/commit/0c8ff723bd29e5c8b2ca989f857ae5c37ec49c4e
  Author: Greg Ungerer <address@hidden>
  Date:   2015-06-22 (Mon, 22 Jun 2015)

  Changed paths:
    M target-m68k/op_helper.c

  Log Message:
  -----------
  m68k: fix usp processing on interrupt entry and exception exit

The action to potentially switch sp register is not occurring at the correct
point in the interrupt entry or exception exit sequences.

For the interrupt entry case the sp on entry is used to create the stack
exception frame - but this may well be the user stack pointer, since we
haven't done the switch yet. Re-order the flow to switch the sp regs then
use the current sp to create the exception frame.

For the return from exception case the code is unwinding the sp after
switching sp registers. But it should always unwind the supervisor sp
first, then carry out any required sp switch.

Note that these problems don't effect operation unless the user sp bit is
set in the CACR register. Only a single sp is used in the default power up
state. Previously Linux only used this single sp mode. But modern versions
of Linux use the user sp mode now, so we need correct behavior for Linux
to work.

Signed-off-by: Greg Ungerer <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Tested-by: Laurent Vivier <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/0a3346f5dea0...0c8ff723bd29

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