[Qemu-commits] [qemu/qemu] fc1891: target-arm: Handle "extended small pa

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[Qemu-commits] [qemu/qemu] fc1891: target-arm: Handle "extended small pa

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] fc1891: target-arm: Handle "extended small page" descripto...
Date:	Tue, 16 Jun 2015 01:30:08 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: fc1891c74ae122a9dc7854f38bae7db03cd911e6
      
https://github.com/qemu/qemu/commit/fc1891c74ae122a9dc7854f38bae7db03cd911e6
  Author: Peter Maydell <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Handle "extended small page" descriptors correctly

The old ARMv5-style page table format includes a kind of second level
descriptor named the "extended small page" format, whose primary purpose
is to allow specification of the TEX memory attribute bits on a 4K page.
This exists on ARMv6 and also (as an implementation extension) on XScale
CPUs; it's UNPREDICTABLE on v5.

We were mishandling this in two ways:
 (1) we weren't implementing it for v6 (probably never noticed because
Linux will use the new-style v6 page table format there)
 (2) we were not correctly setting the page_size, which is 4K, not 1K

The latter bug went unnoticed for years because the only thing which
the page_size affects is which TLB entries get flushed when the guest
does a TLB invalidate on an address in the page, and prior to commit
2f0d8631b7 we were doing a full TLB flush very frequently due to Linux's
habit of writing the SCTLR pointlessly a lot.

(We can assume that after commit 2f0d8631b7 the bug went unnoticed
for a year because nobody's actually using the Zaurus/XScale emulation...)

Report the correct page size for these descriptors, and permit them
on ARMv6 CPUs. This fixes a problem where a kernel image for Zaurus
can boot the kernel OK but gets random segfaults when it tries to
run userspace programs.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 4e42a6ca37e39e56725518851f4388e46bd91129
      
https://github.com/qemu/qemu/commit/4e42a6ca37e39e56725518851f4388e46bd91129
  Author: Sergey Fedorov <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: use extended address bits from supersection short descriptor

Since ARMv7 with LPAE support, a supersection short translation table
descriptor has had extended base address fields which hold bits 39:32 of
translated address. These fields are IMPDEF in ARMv6 and ARMv7 without
LPAE support.

Signed-off-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 235069a380147e31236b94c31528fc5170c3a421
      
https://github.com/qemu/qemu/commit/235069a380147e31236b94c31528fc5170c3a421
  Author: Johan Karlsson <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M hw/intc/arm_gic.c

  Log Message:
  -----------
  arm_gic: gic_update should always update all cores

This patch fixes so that gic_update always updates all the cores with
new pending irq states.  If the function returns early it is possible
to get interrupts that has already been acknowledged.

Signed-off-by: Johan Karlsson <address@hidden>
[PMM: rebased to apply to current master]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 644ead5be1a851abff16886240c5c6fc1c5137c0
      
https://github.com/qemu/qemu/commit/644ead5be1a851abff16886240c5c6fc1c5137c0
  Author: Peter Maydell <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M hw/display/exynos4210_fimd.c

  Log Message:
  -----------
  hw/display/exynos4210_fimd: Fix bit-swapping code

fimd_swap_data() includes code to reverse the bits in a
64-bit integer, but an off-by-one error meant that it would
try to shift off the top of the integer. Correct the bug
(spotted by Coverity).

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: a79e0218e0ae27c9cdd2648bd46e5a916c903cc2
      
https://github.com/qemu/qemu/commit/a79e0218e0ae27c9cdd2648bd46e5a916c903cc2
  Author: Alex Bennée <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm/cpu.h: remove pending_exception

This isn't used by any of the code. In fact it looks like it was never
used as it came in with ARMv7 support.

Signed-off-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7525465e6def0ef878741087b36e4657016dce80
      
https://github.com/qemu/qemu/commit/7525465e6def0ef878741087b36e4657016dce80
  Author: Shannon Zhao <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M target-arm/cpu64.c
    M target-arm/kvm-consts.h

  Log Message:
  -----------
  target-arm/kvm64: Add cortex-a53 cpu support

Since commit e353102(target-arm: cpu64: Add support for Cortex-A53) has
added Cortex-A53 cpu support for target-arm, this patch just enables it
for kvm-arm.

Here adding XGENE_POTENZA just makes the enum continuous.

Signed-off-by: Shannon Zhao <address@hidden>
Signed-off-by: Shannon Zhao <address@hidden>
Message-id: address@hidden
[PMM: Don't add the CPU types to cpus_to_try[]; this array only
 lists old CPUs which were supported in pre-PREFERRED_TARGET kernels]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8772de2c53b44c75f18140646aa928e6d77cb9d8
      
https://github.com/qemu/qemu/commit/8772de2c53b44c75f18140646aa928e6d77cb9d8
  Author: Shannon Zhao <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Add cortex-a53 cpu support in machine virt

Add cortex-a53 cpu support in machine virt, so it can be used for TCG
and KVM.

Signed-off-by: Shannon Zhao <address@hidden>
Signed-off-by: Shannon Zhao <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 13b72b2b9aa7ab7ee129e38e9587acd6a1b9a932
      
https://github.com/qemu/qemu/commit/13b72b2b9aa7ab7ee129e38e9587acd6a1b9a932
  Author: Sergey Fedorov <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/cpu64.c
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Fix REVIDR reset value

According to ARM Cortex-A53/A57 TRM, REVIDR reset value should be zero. So let
REVIDR reset value be specified by CPU model and correct it for Cortex-A53/A57.

Signed-off-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ac00c79ff6635ae9fd732ff357ada0d05e795500
      
https://github.com/qemu/qemu/commit/ac00c79ff6635ae9fd732ff357ada0d05e795500
  Author: Sergey Fedorov <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: add AArch32 MIDR aliases in ARMv8

According to ARMv8 ARM, there are additional aliases to MIDR system register in
AArch32 state. So add them to the list.

Signed-off-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8f4d260e70aff7c3796d97c78ba0663696e2d503
      
https://github.com/qemu/qemu/commit/8f4d260e70aff7c3796d97c78ba0663696e2d503
  Author: Shannon Zhao <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add myself as ARM ACPI Subsystem maintainer

Add Shannon Zhao as the maintainer for the ARM ACPI Subsystem.

Signed-off-by: Shannon Zhao <address@hidden>
Signed-off-by: Shannon Zhao <address@hidden>
Reviewed-by: Claudio Fontana <address@hidden>
Acked-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: eb5e1d3c85dffe677da2550d211f9304a7d5ba3b
      
https://github.com/qemu/qemu/commit/eb5e1d3c85dffe677da2550d211f9304a7d5ba3b
  Author: Pavel Fedin <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M hw/arm/virt.c
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/helper.c
    M target-arm/kvm32.c
    M target-arm/kvm64.c
    M target-arm/psci.c

  Log Message:
  -----------
  target-arm: Use the kernel's idea of MPIDR if we're using KVM

When we're using KVM, the kernel's internal idea of the MPIDR
affinity fields must match the values we tell it for the guest
vcpu cluster configuration in the device tree. Since at the moment
the kernel doesn't support letting userspace tell it the correct
affinity fields to use, we must read the kernel's view and
reflect that back in the device tree.

Signed-off-by: Shlomo Pongratz <address@hidden>
Signed-off-by: Pavel Fedin <address@hidden>
Message-id: address@hidden
[PMM: Use a local #define rather than a global variable for
 the TCG ARM_CPUS_PER_CLUSTER setting. Tweak a comment. Update the
 commit message.]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 14c3032a7ebd5a354381465453c0c0690b7342d1
      
https://github.com/qemu/qemu/commit/14c3032a7ebd5a354381465453c0c0690b7342d1
  Author: Peter Maydell <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M hw/arm/pxa2xx.c
    M hw/arm/pxa2xx_pic.c

  Log Message:
  -----------
  hw/arm/pxa2xx: Mark coprocessor registers as ARM_CP_IO

The pxa2xx custom coprocessor registers in cp6 and cp14 do device
accesses, so mark the non-constant regs as ARM_CP_IO so that
icount works correctly and doesn't abort.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden


  Commit: 1fd9f2df241554b68b3a19ad1c94c475c7bb85ea
      
https://github.com/qemu/qemu/commit/1fd9f2df241554b68b3a19ad1c94c475c7bb85ea
  Author: Peter Maydell <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M hw/arm/pxa2xx.c

  Log Message:
  -----------
  hw/arm/pxa2xx: Convert pxa2xx-fir to QOM and VMState

Convert the pxa2xx-fir device to QOM, including using a
VMState for its migration info.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden


  Commit: ce3203464bee89d2ae958717222981326a37775e
      
https://github.com/qemu/qemu/commit/ce3203464bee89d2ae958717222981326a37775e
  Author: Peter Maydell <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M hw/arm/pxa2xx.c

  Log Message:
  -----------
  hw/arm/pxa2xx: Add reset method for pxa2xx_ssp

The pxa2xx_ssp device was missing a reset method; add one.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden


  Commit: 8e079caf82c3658ee64bca37c91953b38296d427
      
https://github.com/qemu/qemu/commit/8e079caf82c3658ee64bca37c91953b38296d427
  Author: Peter Maydell <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M hw/arm/pxa2xx.c

  Log Message:
  -----------
  hw/arm/pxa2xx: Convert pxa2xx-ssp to VMState

The pxa2xx-ssp device is already a QOM device but is still
using the old-style register_savevm(); convert to VMState.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden


  Commit: 13e1e476b4bc111d36fffaea025f90d8db52b697
      
https://github.com/qemu/qemu/commit/13e1e476b4bc111d36fffaea025f90d8db52b697
  Author: Peter Maydell <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M hw/sd/pxa2xx_mmci.c

  Log Message:
  -----------
  hw/sd/pxa2xx_mmci: Stop using old_mmio in MemoryRegionOps

Update the pxa2xx_mmci device to stop using the old_mmio read
and write callbacks in its MemoryRegionOps. This actually
simplifies the code because the separate byte/halfword/word
access functions were all calling into a single function to
do the work anyway.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden


  Commit: 62b44f059a84d1ac580a653fc4110dfabaef6b83
      
https://github.com/qemu/qemu/commit/62b44f059a84d1ac580a653fc4110dfabaef6b83
  Author: Aurelio C. Remonda <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Add the THUMB_DSP feature

Create an ARM_FEATURE_THUMB_DSP controlling the Thumb encodings of
the 85 DSP instructions (these are all Thumb2). This is enabled for
all non-M-profile CPUs with Thumb2 support, as the instructions are
mandatory for R and A profiles. On M profile they are optional and
not present in the Cortex-M3 (though they are in the M4).

The effect of this commit is that we will now treat the DSP
encodings as illegal instructions on M3, when previously we
incorrectly implemented them.

Signed-off-by: Aurelio C. Remonda <address@hidden>
Message-id: address@hidden
[PMM: added clz/crc32/crc32c and default case to the early-decode switch;
 minor format/spacing fixups; reworded commit message a bit]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8085ce63c5967d200f1241b6c0a189371993c5df
      
https://github.com/qemu/qemu/commit/8085ce63c5967d200f1241b6c0a189371993c5df
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  arm: Do not define TLBTR in PMSA systems

If doing a PMSA (MPU) system do not define the VMSA specific TLBTR CP.
The def is done separately from VMSA registers group as it is affected
by both the OMAP/STRONGARM RW errata and the MIDR backgrounding.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5e5cf9e35f25f9f932a6ce25107c11b67b426a43
      
https://github.com/qemu/qemu/commit/5e5cf9e35f25f9f932a6ce25107c11b67b426a43
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  arm: Don't add v7mp registers in MPU systems

These registers are VMSA specific so they should be conditional on
VMSA (i.e. !MPU).

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8e5d75c950a1241f6e1243c37f28cd58f68fedc9
      
https://github.com/qemu/qemu/commit/8e5d75c950a1241f6e1243c37f28cd58f68fedc9
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  arm: helper: Factor out CP regs common to [pv]msa

V6+ PMSA and VMSA share some common registers that are currently
in the VMSA definition block. Split them out into a new def that can
be shared to PMSA.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889
      
https://github.com/qemu/qemu/commit/b7cc4e82f04a1c5b218a657f677a2fdd1e1c2889
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M target-arm/helper.c
    M target-arm/internals.h
    M target-arm/op_helper.c

  Log Message:
  -----------
  arm: Refactor get_phys_addr FSR return mechanism

Currently, the return code for get_phys_addr is overloaded for both
success/fail and FSR value return. This doesn't handle the case where
there is an error with a 0 FSR. This case exists in PMSAv7.

So rework get_phys_addr and friends to return a success/failure boolean
return code and populate the FSR via a caller provided uint32_t
pointer.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a8e81b319d1ae1224cc7059877dcdf04a5aad59d
      
https://github.com/qemu/qemu/commit/a8e81b319d1ae1224cc7059877dcdf04a5aad59d
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/helper.c

  Log Message:
  -----------
  arm: Implement uniprocessor with MP config

Add a boolean for indicating uniprocessors with MP extensions. This
drives the U bit in MPIDR. Prepares support for Cortex-R5.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8f325f568fbd0158cd413e7d637573ba90b3eaab
      
https://github.com/qemu/qemu/commit/8f325f568fbd0158cd413e7d637573ba90b3eaab
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/cpu.c

  Log Message:
  -----------
  arm: Add has-mpu property

For processors that support MPUs, add a property to de-feature it. This
is similar to the implementation of the EL3 feature.

The processor definition in init sets ARM_FEATURE_MPU if it can support
an MPU. post_init exposes the property, defaulting to true. If cleared
by the instantiator, ARM_FEATURE_MPU is then removed at realize time.

This is to support R profile processors that may or may-not have an MPU
configured.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 13689d43646482f7305282de1bdd662c0d2b8b77
      
https://github.com/qemu/qemu/commit/13689d43646482f7305282de1bdd662c0d2b8b77
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  arm: helper: rename get_phys_addr_mpu

This get_phys_addr is really for pmsav5. Rename it accordingly.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 63a183ed0eac2956574745c84faffa042d99afb8
      
https://github.com/qemu/qemu/commit/63a183ed0eac2956574745c84faffa042d99afb8
  Author: Eric Auger <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  hw/arm/boot: fix rom_reset notifier registration order

commit ac9d32e39664e060cd1b538ff190980d57ad69e4 had the consequence to
register the do_cpu_reset after the rom_reset one. Hence they get
executed in the wrong order. This commit restores the registration of
do_cpu_reset in arm_load_kernel.

Signed-off-by: Eric Auger <address@hidden>
Reported-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Tested-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3977ee5d7a9f2e3664dd8b233f3224694e23b62b
      
https://github.com/qemu/qemu/commit/3977ee5d7a9f2e3664dd8b233f3224694e23b62b
  Author: Peter Maydell <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Correct "preferred return address" for cpreg access exceptions

The architecture defines that when taking an exception trying to
access a coprocessor register, the "preferred return address" for
the exception is the address of the instruction that caused the
exception. Correct an off-by-4 error which meant we were returning
the address after the instruction for traps which happened because
of a failure of a runtime access-check function on an AArch32
register. (Traps caused by translate-time checkable permissions
failures had the correct address, as did traps on AArch64 registers.)

This fixes https://bugs.launchpad.net/qemu/+bug/1463338

Reported-by: Robert Buhren <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: b8a0d75ef85b8f24c92a6c50817fa9579b4a98d9
      
https://github.com/qemu/qemu/commit/b8a0d75ef85b8f24c92a6c50817fa9579b4a98d9
  Author: Andrew Jones <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M include/hw/acpi/acpi-defs.h

  Log Message:
  -----------
  ACPI: Add definitions for the SPCR table

SPCR is the Serial Port Console Redirection Table. See the document
linked from http://uefi.org/acpi. For serial port types, "Interface
Type", see the documentation for the Debug Port Table 2 (DBG2).

Signed-off-by: Andrew Jones <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f264d51d8ad939d7fb339d61a8cf680ed0cb21a2
      
https://github.com/qemu/qemu/commit/f264d51d8ad939d7fb339d61a8cf680ed0cb21a2
  Author: Andrew Jones <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M hw/arm/virt-acpi-build.c

  Log Message:
  -----------
  hw/arm/virt-acpi-build: Add SPCR table

Signed-off-by: Andrew Jones <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1dfe73b94de5a75038a725b17dc7d08a23a977ec
      
https://github.com/qemu/qemu/commit/1dfe73b94de5a75038a725b17dc7d08a23a977ec
  Author: Peter Maydell <address@hidden>
  Date:   2015-06-15 (Mon, 15 Jun 2015)

  Changed paths:
    M MAINTAINERS
    M hw/arm/boot.c
    M hw/arm/pxa2xx.c
    M hw/arm/pxa2xx_pic.c
    M hw/arm/virt-acpi-build.c
    M hw/arm/virt.c
    M hw/display/exynos4210_fimd.c
    M hw/intc/arm_gic.c
    M hw/sd/pxa2xx_mmci.c
    M include/hw/acpi/acpi-defs.h
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/cpu64.c
    M target-arm/helper.c
    M target-arm/internals.h
    M target-arm/kvm-consts.h
    M target-arm/kvm32.c
    M target-arm/kvm64.c
    M target-arm/op_helper.c
    M target-arm/psci.c
    M target-arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150615' 
into staging

target-arm queue:
 * Handle "extended small page" descriptors correctly
 * Use extended address bits from supersection short descriptors
 * Update interrupt status for all cores in gic_update
 * Fix off-by-one in exynos4210_fimd bit-swap code
 * Remove stray unused 'pending_exception' field
 * Add Cortex-A53 KVM support
 * Fix reset value of REVIDR
 * Add AArch32 MIDR aliases for ARMv8 cores
 * MAINTAINERS update for ARM ACPI code
 * Trust the kernel's value of MPIDR if we're using KVM
 * Various pxa2xx device updates to avoid old APIs
 * Mark pxa2xx copro registers as ARM_CP_IO so -icount works
 * Correctly UNDEF Thumb2 DSP insns on Cortex-M3
 * Initial work towards implementing PMSAv7
 * Fix a reset order bug introduced recently
 * Correct "preferred return address" for cpreg access exceptions
 * Add ACPI SPCR table for the virt board

# gpg: Signature made Mon Jun 15 18:19:34 2015 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20150615: (28 commits)
  hw/arm/virt-acpi-build: Add SPCR table
  ACPI: Add definitions for the SPCR table
  target-arm: Correct "preferred return address" for cpreg access exceptions
  hw/arm/boot: fix rom_reset notifier registration order
  arm: helper: rename get_phys_addr_mpu
  arm: Add has-mpu property
  arm: Implement uniprocessor with MP config
  arm: Refactor get_phys_addr FSR return mechanism
  arm: helper: Factor out CP regs common to [pv]msa
  arm: Don't add v7mp registers in MPU systems
  arm: Do not define TLBTR in PMSA systems
  target-arm: Add the THUMB_DSP feature
  hw/sd/pxa2xx_mmci: Stop using old_mmio in MemoryRegionOps
  hw/arm/pxa2xx: Convert pxa2xx-ssp to VMState
  hw/arm/pxa2xx: Add reset method for pxa2xx_ssp
  hw/arm/pxa2xx: Convert pxa2xx-fir to QOM and VMState
  hw/arm/pxa2xx: Mark coprocessor registers as ARM_CP_IO
  target-arm: Use the kernel's idea of MPIDR if we're using KVM
  MAINTAINERS: Add myself as ARM ACPI Subsystem maintainer
  target-arm: add AArch32 MIDR aliases in ARMv8
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/b500e4db8e3e...1dfe73b94de5
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