[Qemu-commits] [qemu/qemu] eab994: target-mips: move group of functions

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[Qemu-commits] [qemu/qemu] eab994: target-mips: move group of functions

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] eab994: target-mips: move group of functions above gen_loa...
Date:	Fri, 12 Jun 2015 07:00:07 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: eab9944c7801525737626fa45cddaf00932dd2c8
      
https://github.com/qemu/qemu/commit/eab9944c7801525737626fa45cddaf00932dd2c8
  Author: Leon Alrae <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: move group of functions above gen_load_fpr32()

Move the "Tests" group of functions so that gen_load_fpr32() and
gen_store_fpr32() can use generate_exception().

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 7c979afd11b09a16634699dd6344e3ba10c9677e
      
https://github.com/qemu/qemu/commit/7c979afd11b09a16634699dd6344e3ba10c9677e
  Author: Leon Alrae <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: add Config5.FRE support allowing Status.FR=0 emulation

This relatively small architectural feature adds the following:

FIR.FREP: Read-only. If FREP=1, then Config5.FRE and Config5.UFE are
    available.

Config5.FRE: When enabled all single-precision FP arithmetic instructions,
       LWC1/LWXC1/MTC1, SWC1/SWXC1/MFC1 cause a Reserved Instructions
       exception.

Config5.UFE: Allows user to write/read Config5.FRE using CTC1/CFC1
       instructions.

Enable the feature in MIPS64R6-generic CPU.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 71c199c81d290b2077ee7cf5400332a342de3a97
      
https://github.com/qemu/qemu/commit/71c199c81d290b2077ee7cf5400332a342de3a97
  Author: Paul Burton <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M hw/mips/mips_malta.c

  Log Message:
  -----------
  mips_malta: provide ememsize env variable to kernels

Commit 94c2b6aff43c (mips_malta: support up to 2GiB RAM) provided
support for using over 256MB of RAM with the MIPS Malta board, including
capping the memsize variable that QEMUs pseudo-bootloader provides to
the kernel at 256MB in order to match YAMON. It didn't however provide
the ememsize variable which kernels supporting memory outside of the
unmapped address spaces (ie. EVA or highmem) may use to determine the
true size of the RAM present in the system.

Set ememsize to the size of RAM so that such kernels may use all
available memory without the user having to manually specifying its size
& location.

Signed-off-by: Paul Burton <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Cc: Leon Alrae <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: be3a8c53b4f18bcc51a462d977cc61a0f46ebb1c
      
https://github.com/qemu/qemu/commit/be3a8c53b4f18bcc51a462d977cc61a0f46ebb1c
  Author: Yongbok Kim <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: Misaligned memory accesses for R6

Release 6 requires misaligned memory access support for all ordinary memory
access instructions (for example, LW/SW, LWC1/SWC1).
However misaligned support is not provided for certain special memory accesses
such as atomics (for example, LL/SC).

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 3b4afc9e75ab1a95f33e41f462921093f8a109c4
      
https://github.com/qemu/qemu/commit/3b4afc9e75ab1a95f33e41f462921093f8a109c4
  Author: Yongbok Kim <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M include/exec/exec-all.h
    M softmmu_template.h

  Log Message:
  -----------
  softmmu: Add probe_write()

Probe for whether the specified guest write access is permitted.
If it is not permitted then an exception will be taken in the same
way as if this were a real write access (and we will not return).
Otherwise the function will return, and there will be a valid
entry in the TLB for this access.

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: adc370a48fd26b92188fa4848dfb088578b1936c
      
https://github.com/qemu/qemu/commit/adc370a48fd26b92188fa4848dfb088578b1936c
  Author: Yongbok Kim <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M target-mips/helper.h
    M target-mips/op_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Misaligned memory accesses for MSA

MIPS SIMD Architecture vector loads and stores require misalignment support.
MSA Memory access should work as an atomic operation. Therefore, it has to
check validity of all addresses for a vector store access if it is spanning
into two pages.

Separating helper functions for each data format as format is known in
translation.
To use mmu_idx from cpu_mmu_index() instead of calculating it from hflag.
Removing save_cpu_state() call in translation because it is able to use
cpu_restore_state() on fault as GETRA() is passed.

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
address@hidden: remove unused do_* functions]
Signed-off-by: Leon Alrae <address@hidden>


  Commit: ce9782f40ac16660ea9437bfaa2c9c34d5ed8110
      
https://github.com/qemu/qemu/commit/ce9782f40ac16660ea9437bfaa2c9c34d5ed8110
  Author: Leon Alrae <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M disas/mips.c
    M target-mips/cpu.h
    M target-mips/helper.h
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: add ERETNC instruction and Config5.LLB bit

ERETNC is identical to ERET except that an ERETNC will not clear the LLbit
that is set by execution of an LL instruction, and thus when placed between
an LL and SC sequence, will never cause the SC to fail.

Presence of ERETNC is denoted by the Config5.LLB.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: 9b1d21c53b73c8f8f79e4aae69c4eb7a5270d6d4
      
https://github.com/qemu/qemu/commit/9b1d21c53b73c8f8f79e4aae69c4eb7a5270d6d4
  Author: Hervé Poussineau <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M default-configs/mips-softmmu.mak
    M default-configs/mips64-softmmu.mak
    M default-configs/mips64el-softmmu.mak
    M default-configs/mipsel-softmmu.mak
    M hw/mips/Makefile.objs
    M hw/mips/mips_jazz.c
    M tests/endianness-test.c

  Log Message:
  -----------
  mips jazz: compile only in 64 bit

Remove now useless device models from other MIPS configurations

We're now compiling 12 files less than before.

Signed-off-by: Hervé Poussineau <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: a3d586f704609a45b6037534cb2f34da5dfd8895
      
https://github.com/qemu/qemu/commit/a3d586f704609a45b6037534cb2f34da5dfd8895
  Author: Hervé Poussineau <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M hw/dma/rc4030.c

  Log Message:
  -----------
  dma/rc4030: create custom DMA address space

Add a new memory region in system address space where DMA address space
definition (the 'translation table') belongs, so we can update on the fly
the DMA address space.

Signed-off-by: Hervé Poussineau <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: dd8205130bab277a27889b6d3c0c6c7651585732
      
https://github.com/qemu/qemu/commit/dd8205130bab277a27889b6d3c0c6c7651585732
  Author: Hervé Poussineau <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M hw/dma/rc4030.c
    M hw/mips/mips_jazz.c
    M hw/net/dp8393x.c
    M include/hw/mips/mips.h

  Log Message:
  -----------
  dma/rc4030: use AddressSpace and address_space_rw in users

Now that rc4030 internally uses an AddressSpace for DMA handling, make its root
memory region public. This is especially usefull for dp8393x netcard, which now
uses well known QEMU types and methods.

Signed-off-by: Hervé Poussineau <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: b421f3f52aed306ecc69221a13fac22d03905956
      
https://github.com/qemu/qemu/commit/b421f3f52aed306ecc69221a13fac22d03905956
  Author: Hervé Poussineau <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M hw/dma/rc4030.c

  Log Message:
  -----------
  dma/rc4030: do not use old_mmio accesses

Signed-off-by: Hervé Poussineau <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: dc6e3e1e1aef2e6b2ed2ddf80c9559c91f685ecd
      
https://github.com/qemu/qemu/commit/dc6e3e1e1aef2e6b2ed2ddf80c9559c91f685ecd
  Author: Hervé Poussineau <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M hw/dma/rc4030.c

  Log Message:
  -----------
  dma/rc4030: document register at offset 0x210

Signed-off-by: Hervé Poussineau <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 95c357bc461b00785284403bf56567657d42e915
      
https://github.com/qemu/qemu/commit/95c357bc461b00785284403bf56567657d42e915
  Author: Hervé Poussineau <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M hw/dma/rc4030.c
    M trace-events

  Log Message:
  -----------
  dma/rc4030: use trace events instead of custom logging

Remove also unneeded debug logs.

Signed-off-by: Hervé Poussineau <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: d791d60f1cf944f578aa26ca9f8903ce5dda1c78
      
https://github.com/qemu/qemu/commit/d791d60f1cf944f578aa26ca9f8903ce5dda1c78
  Author: Hervé Poussineau <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M hw/dma/rc4030.c
    M hw/mips/mips_jazz.c
    M include/hw/mips/mips.h

  Log Message:
  -----------
  dma/rc4030: convert to QOM

Signed-off-by: Hervé Poussineau <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: f2f62c4db244f392381c9061c4185ced98f9be57
      
https://github.com/qemu/qemu/commit/f2f62c4db244f392381c9061c4185ced98f9be57
  Author: Hervé Poussineau <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M hw/net/dp8393x.c

  Log Message:
  -----------
  net/dp8393x: always calculate proper checksums

Signed-off-by: Hervé Poussineau <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 84689cbb97d2f8c7bb1ebe069f887eaaaddb0902
      
https://github.com/qemu/qemu/commit/84689cbb97d2f8c7bb1ebe069f887eaaaddb0902
  Author: Hervé Poussineau <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M hw/net/dp8393x.c

  Log Message:
  -----------
  net/dp8393x: do not use old_mmio accesses

Signed-off-by: Hervé Poussineau <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 3df5de64f06f6b288b1cf30ce2bad7878a96454b
      
https://github.com/qemu/qemu/commit/3df5de64f06f6b288b1cf30ce2bad7878a96454b
  Author: Hervé Poussineau <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M hw/net/dp8393x.c

  Log Message:
  -----------
  net/dp8393x: use dp8393x_ prefix for all functions

Signed-off-by: Hervé Poussineau <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 104655a5c818ea8de1329cef50d1cc8defc524f3
      
https://github.com/qemu/qemu/commit/104655a5c818ea8de1329cef50d1cc8defc524f3
  Author: Hervé Poussineau <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M hw/mips/mips_jazz.c
    M hw/net/dp8393x.c
    M include/hw/mips/mips.h

  Log Message:
  -----------
  net/dp8393x: QOM'ify

Signed-off-by: Laurent Vivier <address@hidden>
Signed-off-by: Hervé Poussineau <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 89ae0ff9b73ee74c9ba707a09a07ad77b9fdccb4
      
https://github.com/qemu/qemu/commit/89ae0ff9b73ee74c9ba707a09a07ad77b9fdccb4
  Author: Hervé Poussineau <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M hw/mips/mips_jazz.c
    M hw/net/dp8393x.c

  Log Message:
  -----------
  net/dp8393x: add PROM to store MAC address

Signed-off-by: Laurent Vivier <address@hidden>
Signed-off-by: Hervé Poussineau <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 1670735dd7087224cf8fabd37c78fc2aa1f0b22f
      
https://github.com/qemu/qemu/commit/1670735dd7087224cf8fabd37c78fc2aa1f0b22f
  Author: Hervé Poussineau <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M hw/net/dp8393x.c

  Log Message:
  -----------
  net/dp8393x: add load/save support

Signed-off-by: Hervé Poussineau <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 409b52bfe199d8106dadf7c5ff3d88d2228e89b5
      
https://github.com/qemu/qemu/commit/409b52bfe199d8106dadf7c5ff3d88d2228e89b5
  Author: Hervé Poussineau <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M hw/net/dp8393x.c

  Log Message:
  -----------
  net/dp8393x: correctly reset in_use field

Don't write more than the field width, which is always 16 bit.
Fixes network in NetBSD 5.1/arc

Signed-off-by: Hervé Poussineau <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: bd8f1ebce430eb6c1dd92e34baf7bc35aa600464
      
https://github.com/qemu/qemu/commit/bd8f1ebce430eb6c1dd92e34baf7bc35aa600464
  Author: Hervé Poussineau <address@hidden>
  Date:   2015-06-11 (Thu, 11 Jun 2015)

  Changed paths:
    M hw/net/dp8393x.c

  Log Message:
  -----------
  net/dp8393x: fix hardware reset

Documentation is not clear of what happens when doing a hardware reset,
but firmware expect all registers to be zero unless specified otherwise.

This fixes reboot on MIPS Magnum.

Signed-off-by: Hervé Poussineau <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: b435f3f3d174721382b55bbd0c785ec50c1796a9
      
https://github.com/qemu/qemu/commit/b435f3f3d174721382b55bbd0c785ec50c1796a9
  Author: Leon Alrae <address@hidden>
  Date:   2015-06-12 (Fri, 12 Jun 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: correct MFC0 for CP0.EntryLo in MIPS64

CP0.EntryLo bits 31:30 have to be cleared.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: 284b731a6ae47b9ebabb9613e753c4d83cf75dd3
      
https://github.com/qemu/qemu/commit/284b731a6ae47b9ebabb9613e753c4d83cf75dd3
  Author: Leon Alrae <address@hidden>
  Date:   2015-06-12 (Fri, 12 Jun 2015)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/machine.c
    M target-mips/op_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: extend selected CP0 registers to 64-bits in MIPS32

Extend EntryLo0, EntryLo1, LLAddr and TagLo from 32 to 64 bits in MIPS32.

Introduce gen_move_low32() function which moves low 32 bits from 64-bit
temp to GPR; it sign extends 32-bit value on MIPS64 and truncates on
MIPS32.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: cd0d45c40133ef8b409aede5ad8a99aeaf6a70fe
      
https://github.com/qemu/qemu/commit/cd0d45c40133ef8b409aede5ad8a99aeaf6a70fe
  Author: Leon Alrae <address@hidden>
  Date:   2015-06-12 (Fri, 12 Jun 2015)

  Changed paths:
    M target-mips/op_helper.c

  Log Message:
  -----------
  target-mips: support Page Frame Number Extension field

Update tlb->PFN to contain PFN concatenated with PFNX. PFNX is 0 if large
physical address is not supported.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: e117f52636d04502fab28bd3abe93347c29f39a5
      
https://github.com/qemu/qemu/commit/e117f52636d04502fab28bd3abe93347c29f39a5
  Author: Leon Alrae <address@hidden>
  Date:   2015-06-12 (Fri, 12 Jun 2015)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/machine.c
    M target-mips/mips-defs.h
    M target-mips/op_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add CP0.PageGrain.ELPA support

CP0.PageGrain.ELPA enables support for large physical addresses. This field
is encoded as follows:
0: Large physical address support is disabled.
1: Large physical address support is enabled.

If this bit is a 1, the following changes occur to coprocessor 0 registers:
- The PFNX field of the EntryLo0 and EntryLo1 registers is writable and
  concatenated with the PFN field to form the full page frame number.
- Access to optional COP0 registers with PA extension, LLAddr, TagLo is
  defined.

P5600 can operate in 32-bit or 40-bit Physical Address Mode. Therefore if
XPA is disabled (CP0.PageGrain.ELPA = 0) then assume 32-bit Address Mode.
In MIPS64 assume 36 as default PABITS (when CP0.PageGrain.ELPA = 0).

env->PABITS value is constant and indicates maximum PABITS available on
a core, whereas env->PAMask is calculated from env->PABITS and is also
affected by CP0.PageGrain.ELPA.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: 5204ea79ea739b557f47fc4db96c94edcb33a5d6
      
https://github.com/qemu/qemu/commit/5204ea79ea739b557f47fc4db96c94edcb33a5d6
  Author: Leon Alrae <address@hidden>
  Date:   2015-06-12 (Fri, 12 Jun 2015)

  Changed paths:
    M disas/mips.c
    M target-mips/cpu.h
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add MTHC0 and MFHC0 instructions

Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access
upper word of extended to 64-bits CP0 registers.

In MIPS64, when CP0 destination register specified is the EntryLo0 or
EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or
EntryLo1. This is to compensate for RI and XI, which were shifted to bits
63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate
functions for EntryLo0 and EntryLo1.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: 28b027d5b63c7550c7390041d6dd50948c8f55b8
      
https://github.com/qemu/qemu/commit/28b027d5b63c7550c7390041d6dd50948c8f55b8
  Author: Leon Alrae <address@hidden>
  Date:   2015-06-12 (Fri, 12 Jun 2015)

  Changed paths:
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: remove misleading comments in translate_init.c

PABITS are not hardcoded to 36 bits and we do not model 59 PABITS (which is
the architectural limit) in QEMU.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: 6773f9b687e0a8ab4b638ef88d075fb233fb7669
      
https://github.com/qemu/qemu/commit/6773f9b687e0a8ab4b638ef88d075fb233fb7669
  Author: Leon Alrae <address@hidden>
  Date:   2015-06-12 (Fri, 12 Jun 2015)

  Changed paths:
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: enable XPA and LPA features

Enable XPA in MIPS32R5-generic and LPA in MIPS64R6-generic.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: 4cb618abc1818586c08011ff0a84a015787b1672
      
https://github.com/qemu/qemu/commit/4cb618abc1818586c08011ff0a84a015787b1672
  Author: Peter Maydell <address@hidden>
  Date:   2015-06-12 (Fri, 12 Jun 2015)

  Changed paths:
    M default-configs/mips-softmmu.mak
    M default-configs/mips64-softmmu.mak
    M default-configs/mips64el-softmmu.mak
    M default-configs/mipsel-softmmu.mak
    M disas/mips.c
    M hw/dma/rc4030.c
    M hw/mips/Makefile.objs
    M hw/mips/mips_jazz.c
    M hw/mips/mips_malta.c
    M hw/net/dp8393x.c
    M include/exec/exec-all.h
    M include/hw/mips/mips.h
    M softmmu_template.h
    M target-mips/cpu.h
    M target-mips/helper.h
    M target-mips/machine.c
    M target-mips/mips-defs.h
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c
    M tests/endianness-test.c
    M trace-events

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150612' into staging

MIPS patches 2015-06-12

Changes:
* improve dp8393x network card and rc4030 chipset emulation
* support misaligned R6 and MSA memory accesses
* support MIPS eXtended and Large Physical Addressing
* add Config5.FRE bit and ERETNC instruction (Config5.LLB)
* support ememsize on MALTA

# gpg: Signature made Fri Jun 12 09:38:11 2015 BST using RSA key ID 0B29DA6B
# gpg: Good signature from "Leon Alrae <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4  4FC0 5211 8E3C 0B29 DA6B

* remotes/lalrae/tags/mips-20150612: (29 commits)
  target-mips: enable XPA and LPA features
  target-mips: remove misleading comments in translate_init.c
  target-mips: add MTHC0 and MFHC0 instructions
  target-mips: add CP0.PageGrain.ELPA support
  target-mips: support Page Frame Number Extension field
  target-mips: extend selected CP0 registers to 64-bits in MIPS32
  target-mips: correct MFC0 for CP0.EntryLo in MIPS64
  net/dp8393x: fix hardware reset
  net/dp8393x: correctly reset in_use field
  net/dp8393x: add load/save support
  net/dp8393x: add PROM to store MAC address
  net/dp8393x: QOM'ify
  net/dp8393x: use dp8393x_ prefix for all functions
  net/dp8393x: do not use old_mmio accesses
  net/dp8393x: always calculate proper checksums
  dma/rc4030: convert to QOM
  dma/rc4030: use trace events instead of custom logging
  dma/rc4030: document register at offset 0x210
  dma/rc4030: do not use old_mmio accesses
  dma/rc4030: use AddressSpace and address_space_rw in users
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/a4ef02fd9b3d...4cb618abc181
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