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[Qemu-commits] [qemu/qemu] ee8042: target-arm: cpu64: generalise name of

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] ee8042: target-arm: cpu64: generalise name of A57 regs
Date: Tue, 19 May 2015 01:00:06 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: ee804264ddc4d3cd36a5183a09847e391da0fc66
      
https://github.com/qemu/qemu/commit/ee804264ddc4d3cd36a5183a09847e391da0fc66
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M target-arm/cpu64.c

  Log Message:
  -----------
  target-arm: cpu64: generalise name of A57 regs

Rename some A57 CP register variables in preparation for support for
Cortex A53. Use "a57_a53" to describe the shareable features. Some of
the CP15 registers (such as ACTLR) are specific to implementation, but
we currently just RAZ them so continue with that as the policy for both
A57 and A53 processors under a shared definition.

Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e35310260ec57d20301c65a5714ca55369e971cc
      
https://github.com/qemu/qemu/commit/e35310260ec57d20301c65a5714ca55369e971cc
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M target-arm/cpu64.c

  Log Message:
  -----------
  target-arm: cpu64: Add support for Cortex-A53

Add the ARM Cortex-A53 processor definition. Similar to A57, but with
different L1 I cache policy, phys addr size and different cache
geometries. The cache sizes is implementation configurable, but use
these values (from Xilinx Zynq MPSoC) as a default until cache size
configurability is added.

Acked-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f0a902f76452211cadbdf1d25ef9b94732b096e8
      
https://github.com/qemu/qemu/commit/f0a902f76452211cadbdf1d25ef9b94732b096e8
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M default-configs/aarch64-softmmu.mak
    M hw/arm/Makefile.objs
    A hw/arm/xlnx-zynqmp.c
    A include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  arm: Introduce Xilinx ZynqMP SoC

With quad Cortex-A53 CPUs.

Use SMC PSCI, with the standard policy of secondaries starting in
power-off.

Tested-by: Alistair Francis <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7729e1f4b3c670eca38cc0ee0d96c1177efbc1e3
      
https://github.com/qemu/qemu/commit/7729e1f4b3c670eca38cc0ee0d96c1177efbc1e3
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  arm: xlnx-zynqmp: Add GIC

Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are
under-decoded through a 64k address region so implement aliases
accordingly.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bf4cb10966a7685bba3aeaf14434902889ef535d
      
https://github.com/qemu/qemu/commit/bf4cb10966a7685bba3aeaf14434902889ef535d
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c

  Log Message:
  -----------
  arm: xlnx-zynqmp: Connect CPU Timers to GIC

Connect the GPIO outputs from the individual CPUs for the timers to the
GIC.

Tested-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 448f19e23155021e42878e7effc3da895921ad4e
      
https://github.com/qemu/qemu/commit/448f19e23155021e42878e7effc3da895921ad4e
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M hw/net/cadence_gem.c

  Log Message:
  -----------
  net: cadence_gem: Clean up variable names

Cleanup some variable names in preparation for migrating the state
struct and type cast macro to a public header. The acronym "GEM" on
its own is not specific enough to be used in a more global namespace
so preface with "cadence". Fix the capitalisation of "gem" in the
state type while touching the typename. Also preface the GEM_MAXREG
macro as this will need to migrate to public header.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f49856d4e65703e347ee3e2277a87282ce601bcd
      
https://github.com/qemu/qemu/commit/f49856d4e65703e347ee3e2277a87282ce601bcd
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M hw/net/cadence_gem.c
    A include/hw/net/cadence_gem.h

  Log Message:
  -----------
  net: cadence_gem: Split state struct and type into header

Create a new header for Cadence GEM to allow using the device with
modern SoC programming conventions. The state struct needs to be
visible to embed the device in SoC containers.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 14ca2e462ee137974d81729b1d88d9d39cf2f22c
      
https://github.com/qemu/qemu/commit/14ca2e462ee137974d81729b1d88d9d39cf2f22c
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  arm: xlnx-zynqmp: Add GEM support

There are 4x Cadence GEMs in ZynqMP. Add them.

Reviewed-by: Peter Maydell <address@hidden>
Tested-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e86da3cb40d6f70ce99d8e64952c49df8ad78848
      
https://github.com/qemu/qemu/commit/e86da3cb40d6f70ce99d8e64952c49df8ad78848
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M hw/char/cadence_uart.c

  Log Message:
  -----------
  char: cadence_uart: Clean up variable names

Clean up some variable names in preparation for migrating the state struct
and type cast macro to a public header. The acronym "UART" on it's own is
not specific enough to be used in a more global namespace so preface with
"cadence". Fix the capitalisation of "uart" in the state type while touching
the typename. Preface macros used by the state struct itself with CADENCE_UART
so they don't conflict in namespace either.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8ae57b2fa35dae9aa4b50db5e632156eded9bec0
      
https://github.com/qemu/qemu/commit/8ae57b2fa35dae9aa4b50db5e632156eded9bec0
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M hw/char/cadence_uart.c
    A include/hw/char/cadence_uart.h

  Log Message:
  -----------
  char: cadence_uart: Split state struct and type into header

Create a new header for Cadence UART to allow using the device with
modern SoC programming conventions. The state struct needs to be
visible to embed the device in SoC containers.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3bade2a9e6336e0eb7cc5ad7425994f1143c5cfa
      
https://github.com/qemu/qemu/commit/3bade2a9e6336e0eb7cc5ad7425994f1143c5cfa
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  arm: xlnx-zynqmp: Add UART support

There are 2x Cadence UARTs in Zynq MP. Add them.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Tested-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 859a0c5b5fb8be0c1ed78d96695a162c9210e1e6
      
https://github.com/qemu/qemu/commit/859a0c5b5fb8be0c1ed78d96695a162c9210e1e6
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M hw/arm/Makefile.objs
    A hw/arm/xlnx-ep108.c

  Log Message:
  -----------
  arm: Add xlnx-ep108 machine

Add a machine model for the Xilinx ZynqMP SoC EP108 board.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b79b9d28f6b8f7879c50b6c053b4e3796de5b7d0
      
https://github.com/qemu/qemu/commit/b79b9d28f6b8f7879c50b6c053b4e3796de5b7d0
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M hw/arm/xlnx-ep108.c

  Log Message:
  -----------
  arm: xlnx-ep108: Add external RAM

Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model.

Reviewed-by: Alistair Francis <address@hidden>
Tested-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 082587b741efc5329380b4a156d86f2bdbfa2d70
      
https://github.com/qemu/qemu/commit/082587b741efc5329380b4a156d86f2bdbfa2d70
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M hw/arm/xlnx-ep108.c

  Log Message:
  -----------
  arm: xlnx-ep108: Add bootloading

Add bootloader support using standard ARM bootloader.

Reviewed-by: Alistair Francis <address@hidden>
Tested-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d82322e175d58c0c8951cbc905da1ca9ee2e008c
      
https://github.com/qemu/qemu/commit/d82322e175d58c0c8951cbc905da1ca9ee2e008c
  Author: Timothy Baldwin <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M linux-user/arm/syscall_nr.h

  Log Message:
  -----------
  linux-user/arm: Correct TARGET_NR_timerfd to TARGET_NR_timerfd_create

Misspelled system call name in macro was causing timerfd_create not
to be supported for the ARM target.

Signed-off-by: Timothy Edward Baldwin <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: aef878be4e7ab1bdb30b408007320400b0a29c83
      
https://github.com/qemu/qemu/commit/aef878be4e7ab1bdb30b408007320400b0a29c83
  Author: Greg Bellows <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add TTBR regime function and use

Add a utility function for choosing the correct TTBR system register based on
the specified MMU index. Add use of function on physical address lookup.

Signed-off-by: Greg Bellows <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
[PMM: fixed regime_ttbr() return type to be uint64_t]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 88e8add8b6656c349a96b447b074688d02dc5415
      
https://github.com/qemu/qemu/commit/88e8add8b6656c349a96b447b074688d02dc5415
  Author: Greg Bellows <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add EL3 and EL2 TCR checking

Updated get_phys_addr_lpae to check the appropriate TTBCR/TCR depending on the
current EL. Support includes using the different TCR format as well as checks to
insure TTBR1 is not used when in EL2 or EL3.

Signed-off-by: Greg Bellows <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 06fbb2fdf7a7ac468d62c66cfe4537d3c71f7bb9
      
https://github.com/qemu/qemu/commit/06fbb2fdf7a7ac468d62c66cfe4537d3c71f7bb9
  Author: Greg Bellows <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M target-arm/internals.h

  Log Message:
  -----------
  target-arm: Add WFx syndrome function

Adds a utility function for creating a WFx exception syndrome

Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 12cde08aaf571de65d3fbbdf93c83f0a4321267f
      
https://github.com/qemu/qemu/commit/12cde08aaf571de65d3fbbdf93c83f0a4321267f
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Correct accessfn for CNTP_{CT}VAL_EL0

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b65c08ee1a05760c1c5a786a6cedf240f924c53e
      
https://github.com/qemu/qemu/commit/b65c08ee1a05760c1c5a786a6cedf240f924c53e
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Correct accessfn for CNTV_TVAL_EL0

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 18084b2f71b22b3ec3bf4828b8cb83d1d39e8502
      
https://github.com/qemu/qemu/commit/18084b2f71b22b3ec3bf4828b8cb83d1d39e8502
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Remove unneeded '+'

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 62bf3df432d93fa6eb0f355c460d6d784b7cbc1a
      
https://github.com/qemu/qemu/commit/62bf3df432d93fa6eb0f355c460d6d784b7cbc1a
  Author: Peter Maydell <address@hidden>
  Date:   2015-05-18 (Mon, 18 May 2015)

  Changed paths:
    M default-configs/aarch64-softmmu.mak
    M hw/arm/Makefile.objs
    A hw/arm/xlnx-ep108.c
    A hw/arm/xlnx-zynqmp.c
    M hw/char/cadence_uart.c
    M hw/net/cadence_gem.c
    A include/hw/arm/xlnx-zynqmp.h
    A include/hw/char/cadence_uart.h
    A include/hw/net/cadence_gem.h
    M linux-user/arm/syscall_nr.h
    M target-arm/cpu64.c
    M target-arm/helper.c
    M target-arm/internals.h

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20150518-3' into staging

target-arm:
 * New board model: xlnx-ep108
 * Some more preparation for AArch64 EL2/EL3
 * Fix bugs in access checking for generic counter registers
 * Remove a stray '+' sign

# gpg: Signature made Mon May 18 20:13:05 2015 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20150518-3: (21 commits)
  target-arm: Remove unneeded '+'
  target-arm: Correct accessfn for CNTV_TVAL_EL0
  target-arm: Correct accessfn for CNTP_{CT}VAL_EL0
  target-arm: Add WFx syndrome function
  target-arm: Add EL3 and EL2 TCR checking
  target-arm: Add TTBR regime function and use
  linux-user/arm: Correct TARGET_NR_timerfd to TARGET_NR_timerfd_create
  arm: xlnx-ep108: Add bootloading
  arm: xlnx-ep108: Add external RAM
  arm: Add xlnx-ep108 machine
  arm: xlnx-zynqmp: Add UART support
  char: cadence_uart: Split state struct and type into header
  char: cadence_uart: Clean up variable names
  arm: xlnx-zynqmp: Add GEM support
  net: cadence_gem: Split state struct and type into header
  net: cadence_gem: Clean up variable names
  arm: xlnx-zynqmp: Connect CPU Timers to GIC
  arm: xlnx-zynqmp: Add GIC
  arm: Introduce Xilinx ZynqMP SoC
  target-arm: cpu64: Add support for Cortex-A53
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/385057cbec9b...62bf3df432d9
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