[Qemu-commits] [qemu/qemu] 165cda: armv7m_nvic: systick: Reload the RELOAD value and ...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 165cdaf857dc850f676fff0b5b873a51865baa9c
      
https://github.com/qemu/qemu/commit/165cdaf857dc850f676fff0b5b873a51865baa9c
  Author: Adrian Huang <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  armv7m_nvic: systick: Reload the RELOAD value and count down only if ENABLE 
bit is set

Consider the following pseudo code to configure SYSTICK (The
recommended programming sequence from "the definitive guide to the
arm cortex-m3"):
    SYSTICK Reload Value Register = 0xffff
    SYSTICK Current Value Register = 0
    SYSTICK Control and Status Register = 0x7

The pseudo code "SYSTICK Current Value Register = 0" leads to invoking
systick_reload(). As a consequence, the systick.tick member is updated
and the systick timer starts to count down when the ENABLE bit of
SYSTICK Control and Status Register is cleared.

The worst case is that: during the system initialization, the reset
value of the SYSTICK Control and Status Register is 0x00000000.
When the code "SYSTICK Current Value Register = 0" is executed, the
systick.tick member is accumulated with "(s->systick.reload + 1) *
systick_scale(s)". The systick_scale() gets the external_ref_clock
scale because the CLKSOURCE bit of the SYSTICK Control and Status
Register is cleared. This is the incorrect behavior because of the
code "SYSTICK Control and Status Register = 0x7". Actually, we want
the processor clock instead of the external reference clock.

This incorrect behavior defers the generation of the first interrupt.

The patch fixes the above-mentioned issue by setting the systick.tick
member and modifying the systick timer only if the ENABLE bit of
the SYSTICK Control and Status Register is set.

In addition, the Cortex-M3 Devices Generic User Guide mentioned that
"When ENABLE is set to 1, the counter loads the RELOAD value from the
SYST RVR register and then counts down". This patch adheres to the
statement of the user guide.

Signed-off-by: Adrian Huang <address@hidden>
Reviewed-by: Jim Huang <address@hidden>
[PMM: minor tweak to comment text]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 16b781aaef69c90d5f4f5456615f0c26a4f45740
      
https://github.com/qemu/qemu/commit/16b781aaef69c90d5f4f5456615f0c26a4f45740
  Author: Peter Maydell <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/sd/sd.c

  Log Message:
  -----------
  hw/sd: Don't pass BlockBackend to sd_reset()

The only valid BlockBackend to pass to sd_reset() is the one for
the SD card, which is sd->blk. Drop the second argument from this
function in favour of having it just use sd->blk.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Message-id: address@hidden


  Commit: 44f552964714a41ccd41b5e8ac4cbd2478249db1
      
https://github.com/qemu/qemu/commit/44f552964714a41ccd41b5e8ac4cbd2478249db1
  Author: Fabian Aggeler <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_kvm.c
    M include/hw/intc/arm_gic_common.h

  Log Message:
  -----------
  hw/intc/arm_gic: Create outbound FIQ lines

Create the outbound FIQ lines from the GIC to the CPUs; these are
used if the GIC has security extensions or grouping support.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
[PMM: added FIQ lines to kvm-arm-gic so its interface is the same;
tweaked commit message]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5543d1abb6e218a9d3b8887b777fd3947c86c4cf
      
https://github.com/qemu/qemu/commit/5543d1abb6e218a9d3b8887b777fd3947c86c4cf
  Author: Fabian Aggeler <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_common.c
    M hw/intc/arm_gic_kvm.c
    M include/hw/intc/arm_gic_common.h

  Log Message:
  -----------
  hw/intc/arm_gic: Add Security Extensions property

Add a QOM property which allows the GIC Security Extensions to be
enabled. These are an optional part of the GICv1 and GICv2 architecture.
This commit just adds the property and some sanity checks that it
is only enabled on GIC revisions that support it.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
[PMM: changed property name, added checks that it isn't set for
 older GIC revisions or if using the KVM VGIC; reworded commit message]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a9d853533cc1a27dc09b10c7ab89677f9c5dd8f4
      
https://github.com/qemu/qemu/commit/a9d853533cc1a27dc09b10c7ab89677f9c5dd8f4
  Author: Peter Maydell <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/intc/arm_gic.c

  Log Message:
  -----------
  hw/intc/arm_gic: Switch to read/write callbacks with tx attributes

Switch the GIC's MMIO callback functions to the read_with_attrs
and write_with_attrs functions which provide MemTxAttrs. This will
allow the GIC to correctly handle secure and nonsecure register
accesses.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: c27a5ba94874cb3a29e21b3ad4bd5e504aea93b2
      
https://github.com/qemu/qemu/commit/c27a5ba94874cb3a29e21b3ad4bd5e504aea93b2
  Author: Fabian Aggeler <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_common.c
    M hw/intc/gic_internal.h
    M include/hw/intc/arm_gic_common.h

  Log Message:
  -----------
  hw/intc/arm_gic: Add Interrupt Group Registers

The Interrupt Group Registers allow the guest to configure interrupts
into one of two groups, where Group0 are higher priority and may
be routed to IRQ or FIQ, and Group1 are lower priority and always
routed to IRQ. (In a GIC with the security extensions Group0 is
Secure interrupts and Group 1 is NonSecure.)
The GICv2 always supports interrupt grouping; the GICv1 does only
if it implements the security extensions.

This patch implements the ability to read and write the registers;
the actual functionality the bits control will be added in a
subsequent patch.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
[PMM: bring GIC_*_GROUP macros into line with the others, ie a
 simple SET/CLEAR/TEST rather than GROUP0/GROUP1;
 utility gic_has_groups() function;
 minor style fixes;
 bump vmstate version]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: eb8b9530b0c618d4f2e728eae10d89239d35b0c0
      
https://github.com/qemu/qemu/commit/eb8b9530b0c618d4f2e728eae10d89239d35b0c0
  Author: Peter Maydell <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/intc/arm_gic_kvm.c

  Log Message:
  -----------
  hw/intc/arm_gic_kvm.c: Save and restore GICD_IGROUPRn state

Now that the GIC base class has state fields for the GICD_IGROUPRn
registers, make kvm_arm_gic_get() and kvm_arm_gic_put() write and
read them. This allows us to remove the check that made us
fail migration if the guest had set any of the group register bits.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 679aa175e84f5f80b32b307fce5a6b92729e0e61
      
https://github.com/qemu/qemu/commit/679aa175e84f5f80b32b307fce5a6b92729e0e61
  Author: Fabian Aggeler <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_common.c
    M hw/intc/arm_gic_kvm.c
    M hw/intc/armv7m_nvic.c
    M hw/intc/gic_internal.h
    M include/hw/intc/arm_gic_common.h

  Log Message:
  -----------
  hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked

ICDDCR/GICD_CTLR is banked if the GIC has the security extensions,
and the S (or only) copy has separate enable bits for Group0 and
Group1 enable if the GIC implements interrupt groups.

EnableGroup0 (Bit [1]) in GICv1 is architecturally IMPDEF. Since this
bit (Enable Non-secure) is present in the integrated GIC of the Cortex-A9
MPCore, we support this bit in our GICv1 implementation too.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
[PMM: rewritten to store the state in a single s->ctlr uint32,
 with the NS register handled as an alias of bit 1 in that value;
 added vmstate version bump]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 822e9cc310484f77e0b1c16fbef763a5d0eec80a
      
https://github.com/qemu/qemu/commit/822e9cc310484f77e0b1c16fbef763a5d0eec80a
  Author: Fabian Aggeler <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/intc/arm_gic.c
    M include/hw/intc/arm_gic_common.h

  Log Message:
  -----------
  hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked

This register is banked in GICs with Security Extensions. Storing the
non-secure copy of BPR in the abpr, which is an alias to the non-secure
copy for secure access. ABPR itself is only accessible from secure state
if the GIC implements Security Extensions.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
[PMM: rewrote to fix style issues and correct handling of GICv2
 without security extensions]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 32951860834f09d1c1a0b81d8d7d5529e2d0e074
      
https://github.com/qemu/qemu/commit/32951860834f09d1c1a0b81d8d7d5529e2d0e074
  Author: Fabian Aggeler <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_common.c
    M hw/intc/arm_gic_kvm.c
    M hw/intc/armv7m_nvic.c
    M hw/intc/gic_internal.h
    M include/hw/intc/arm_gic_common.h

  Log Message:
  -----------
  hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked

ICCICR/GICC_CTLR is banked in GICv1 implementations with Security
Extensions or in GICv2 in independent from Security Extensions.
This makes it possible to enable forwarding of interrupts from
the CPU interfaces to the connected processors for Group0 and Group1.

We also allow to set additional bits like AckCtl and FIQEn by changing
the type from bool to uint32. Since the field does not only store the
enable bit anymore and since we are touching the vmstate, we use the
opportunity to rename the field to cpu_ctlr.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
[PMM: rewrote to store state in a single uint32_t rather than
 keeping the NS and S banked variants separate; this considerably
 simplifies the get/set functions]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 08efa9f2d1bb27d64fbedcc2879ca45ae6832c20
      
https://github.com/qemu/qemu/commit/08efa9f2d1bb27d64fbedcc2879ca45ae6832c20
  Author: Fabian Aggeler <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/intc/arm_gic.c

  Log Message:
  -----------
  hw/intc/arm_gic: Implement Non-secure view of RPR

For GICs with Security Extensions Non-secure reads have a restricted
view on the current running priority.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
[PMM: make function static, minor comment tweak]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8150847061f8d2606101bfff77cc6ec86b081ab0
      
https://github.com/qemu/qemu/commit/8150847061f8d2606101bfff77cc6ec86b081ab0
  Author: Fabian Aggeler <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_kvm.c
    M hw/intc/gic_internal.h

  Log Message:
  -----------
  hw/intc/arm_gic: Restrict priority view

GICs with Security Extensions restrict the non-secure view of the
interrupt priority and priority mask registers.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
[PMM: minor code tweaks; fixed missing masking in gic_set_priority_mask
and gic_set_priority]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7c0fa108d918ab818e49c4588ab290004d6b532e
      
https://github.com/qemu/qemu/commit/7c0fa108d918ab818e49c4588ab290004d6b532e
  Author: Fabian Aggeler <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/intc/arm_gic.c

  Log Message:
  -----------
  hw/intc/arm_gic: Handle grouping for GICC_HPPIR

Grouping (GICv2) and Security Extensions change the behaviour of reads
of the highest priority pending interrupt register (ICCHPIR/GICC_HPPIR).

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
[PMM: make utility fn static; coding style fixes; AckCtl has an effect
 for GICv2 without security extensions as well; removed checks on enable
 bits because these are done when we set current_pending[cpu]]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f9c6a7f1395c6d88a3bb1a0cb48811994709966e
      
https://github.com/qemu/qemu/commit/f9c6a7f1395c6d88a3bb1a0cb48811994709966e
  Author: Fabian Aggeler <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/intc/arm_gic.c
    M hw/intc/armv7m_nvic.c
    M hw/intc/gic_internal.h

  Log Message:
  -----------
  hw/intc/arm_gic: Change behavior of EOIR writes

Grouping (GICv2) and Security Extensions change the behavior of EOIR
writes. Completing Group0 interrupts is only allowed from Secure state.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
[PMM: Rather than go to great lengths to ignore the UNPREDICTABLE case
 of a Secure EOI of a Group1 (NS) irq with AckCtl == 0, we just let
 it fall through; add a comment about it.]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c5619bf9e8935aeb972c0bd935549e9ee0a739f2
      
https://github.com/qemu/qemu/commit/c5619bf9e8935aeb972c0bd935549e9ee0a739f2
  Author: Fabian Aggeler <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/intc/arm_gic.c
    M hw/intc/armv7m_nvic.c
    M hw/intc/gic_internal.h

  Log Message:
  -----------
  hw/intc/arm_gic: Change behavior of IAR writes

Grouping (GICv2) and Security Extensions change the behavior of IAR
reads. Acknowledging Group0 interrupts is only allowed from Secure
state and acknowledging Group1 interrupts from Secure state is only
allowed if AckCtl bit is set.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
[PMM: simplify significantly by reusing the existing
 gic_get_current_pending_irq() rather than reimplementing the
 same logic here]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dadbb58f5955053c5f5dc2252a4b183f90d7bfce
      
https://github.com/qemu/qemu/commit/dadbb58f5955053c5f5dc2252a4b183f90d7bfce
  Author: Peter Maydell <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/intc/arm_gic.c

  Log Message:
  -----------
  hw/intc/arm_gic: Add grouping support to gic_update()

Add support to gic_update() for determining the current IRQ
and FIQ status when interrupt grouping is supported. This
simply requires that instead of always raising IRQ we
check the group of the highest priority pending interrupt
and the GICC_CTLR.FIQEn bit to see whether we should raise
IRQ or FIQ.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden


  Commit: 8e7b4ca08b968c9e195bcae9c6cb827c8564871a
      
https://github.com/qemu/qemu/commit/8e7b4ca08b968c9e195bcae9c6cb827c8564871a
  Author: Greg Bellows <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt.c: Wire FIQ between CPU <> GIC

Connect FIQ output of the GIC CPU interfaces to the CPUs.

Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
[PMM: minor format tweak]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 27192e390d064489dcb23d5fcceb21cabf86d789
      
https://github.com/qemu/qemu/commit/27192e390d064489dcb23d5fcceb21cabf86d789
  Author: Fabian Aggeler <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/arm/vexpress.c

  Log Message:
  -----------
  hw/arm/vexpress.c: Wire FIQ between CPU <> GIC

Connect FIQ output of the GIC CPU interfaces to the CPUs.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
[PMM: minor format tweak]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5ae79fe825bedc89db8b6bde9d0ed0bb5d59558c
      
https://github.com/qemu/qemu/commit/5ae79fe825bedc89db8b6bde9d0ed0bb5d59558c
  Author: Peter Maydell <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/arm/highbank.c

  Log Message:
  -----------
  hw/arm/highbank.c: Wire FIQ between CPU <> GIC

Connect FIQ output of the GIC CPU interfaces to the CPUs.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 968bb75c348a401b85e08d5eb1887a3e6c3185f5
      
https://github.com/qemu/qemu/commit/968bb75c348a401b85e08d5eb1887a3e6c3185f5
  Author: Peter Maydell <address@hidden>
  Date:   2015-05-12 (Tue, 12 May 2015)

  Changed paths:
    M hw/arm/highbank.c
    M hw/arm/vexpress.c
    M hw/arm/virt.c
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_common.c
    M hw/intc/arm_gic_kvm.c
    M hw/intc/armv7m_nvic.c
    M hw/intc/gic_internal.h
    M hw/sd/sd.c
    M include/hw/intc/arm_gic_common.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150512' 
into staging

target-arm queue:
 * Support TZ and grouping in the GIC
 * hw/sd: sd_reset cleanup
 * armv7m_nvic: fix bug in systick device

# gpg: Signature made Tue May 12 12:02:26 2015 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20150512:
  hw/arm/highbank.c: Wire FIQ between CPU <> GIC
  hw/arm/vexpress.c: Wire FIQ between CPU <> GIC
  hw/arm/virt.c: Wire FIQ between CPU <> GIC
  hw/intc/arm_gic: Add grouping support to gic_update()
  hw/intc/arm_gic: Change behavior of IAR writes
  hw/intc/arm_gic: Change behavior of EOIR writes
  hw/intc/arm_gic: Handle grouping for GICC_HPPIR
  hw/intc/arm_gic: Restrict priority view
  hw/intc/arm_gic: Implement Non-secure view of RPR
  hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked
  hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked
  hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked
  hw/intc/arm_gic_kvm.c: Save and restore GICD_IGROUPRn state
  hw/intc/arm_gic: Add Interrupt Group Registers
  hw/intc/arm_gic: Switch to read/write callbacks with tx attributes
  hw/intc/arm_gic: Add Security Extensions property
  hw/intc/arm_gic: Create outbound FIQ lines
  hw/sd: Don't pass BlockBackend to sd_reset()
  armv7m_nvic: systick: Reload the RELOAD value and count down only if ENABLE 
bit is set

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/19fbe5084c1d...968bb75c348a