[Qemu-commits] [qemu/qemu] cc05c4: memory: Define API for MemoryRegionOps to take att...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: cc05c43ad942165ecc6ffd39e41991bee43af044
      
https://github.com/qemu/qemu/commit/cc05c43ad942165ecc6ffd39e41991bee43af044
  Author: Peter Maydell <address@hidden>
  Date:   2015-04-26 (Sun, 26 Apr 2015)

  Changed paths:
    A include/exec/memattrs.h
    M include/exec/memory.h
    M memory.c

  Log Message:
  -----------
  memory: Define API for MemoryRegionOps to take attrs and return status

Define an API so that devices can register MemoryRegionOps whose read
and write callback functions are passed an arbitrary pointer to some
transaction attributes and can return a success-or-failure status code.
This will allow us to model devices which:
 * behave differently for ARM Secure/NonSecure memory accesses
 * behave differently for privileged/unprivileged accesses
 * may return a transaction failure (causing a guest exception)
   for erroneous accesses

This patch defines the new API and plumbs the attributes parameter through
to the memory.c public level functions io_mem_read() and io_mem_write(),
where it is currently dummied out.

The success/failure response indication is also propagated out to
io_mem_read() and io_mem_write(), which retain the old-style
boolean true-for-error return.

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Paolo Bonzini <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>


  Commit: 3b6434953934e6d4a776ed426d8c6d6badee176f
      
https://github.com/qemu/qemu/commit/3b6434953934e6d4a776ed426d8c6d6badee176f
  Author: Peter Maydell <address@hidden>
  Date:   2015-04-26 (Sun, 26 Apr 2015)

  Changed paths:
    M exec.c
    M hw/s390x/s390-pci-inst.c
    M hw/vfio/pci.c
    M include/exec/exec-all.h
    M include/exec/memory.h
    M memory.c
    M softmmu_template.h

  Log Message:
  -----------
  memory: Replace io_mem_read/write with memory_region_dispatch_read/write

Rather than retaining io_mem_read/write as simple wrappers around
the memory_region_dispatch_read/write functions, make the latter
public and change all the callers to use them, since we need to
touch all the callsites anyway to add MemTxAttrs and MemTxResult
support. Delete io_mem_read and io_mem_write entirely.

(All the callers currently pass MEMTXATTRS_UNSPECIFIED
and convert the return value back to bool or ignore it.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>


  Commit: e469b22ffda40188954fafaf6e3308f58d50f8f8
      
https://github.com/qemu/qemu/commit/e469b22ffda40188954fafaf6e3308f58d50f8f8
  Author: Peter Maydell <address@hidden>
  Date:   2015-04-26 (Sun, 26 Apr 2015)

  Changed paths:
    M cputlb.c
    M include/exec/cpu-defs.h
    M softmmu_template.h

  Log Message:
  -----------
  Make CPU iotlb a structure rather than a plain hwaddr

Make the CPU iotlb a structure rather than a plain hwaddr;
this will allow us to add transaction attributes to it.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>


  Commit: fadc1cbe85c6b032d5842ec0d19d209f50fcb375
      
https://github.com/qemu/qemu/commit/fadc1cbe85c6b032d5842ec0d19d209f50fcb375
  Author: Peter Maydell <address@hidden>
  Date:   2015-04-26 (Sun, 26 Apr 2015)

  Changed paths:
    M cputlb.c
    M include/exec/cpu-defs.h
    M include/exec/exec-all.h
    M softmmu_template.h

  Log Message:
  -----------
  Add MemTxAttrs to the IOTLB

Add a MemTxAttrs field to the IOTLB, and allow target-specific
code to set it via a new tlb_set_page_with_attrs() function;
pass the attributes through to the device when making IO accesses.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>


  Commit: f25a49e0057bbfcc2b1111f60785d919b6ddaeea
      
https://github.com/qemu/qemu/commit/f25a49e0057bbfcc2b1111f60785d919b6ddaeea
  Author: Peter Maydell <address@hidden>
  Date:   2015-04-26 (Sun, 26 Apr 2015)

  Changed paths:
    M exec.c

  Log Message:
  -----------
  exec.c: Convert subpage memory ops to _with_attrs

Convert the subpage memory ops to _with_attrs; this will allow
us to pass the attributes through to the underlying access
functions. (Nothing uses the attributes yet.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 5c9eb0286c819c1836220a32f2e1a7b5004ac79a
      
https://github.com/qemu/qemu/commit/5c9eb0286c819c1836220a32f2e1a7b5004ac79a
  Author: Peter Maydell <address@hidden>
  Date:   2015-04-26 (Sun, 26 Apr 2015)

  Changed paths:
    M dma-helpers.c
    M exec.c
    M hw/mips/mips_jazz.c
    M hw/pci-host/prep.c
    M include/exec/memory.h
    M include/sysemu/dma.h
    M ioport.c
    M kvm-all.c
    M scripts/coverity-model.c

  Log Message:
  -----------
  exec.c: Make address_space_rw take transaction attributes

Make address_space_rw take transaction attributes, rather
than always using the 'unspecified' attributes.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>


  Commit: 500131154d677930fce35ec3a6f0b5a26bcd2973
      
https://github.com/qemu/qemu/commit/500131154d677930fce35ec3a6f0b5a26bcd2973
  Author: Peter Maydell <address@hidden>
  Date:   2015-04-26 (Sun, 26 Apr 2015)

  Changed paths:
    M exec.c
    M include/exec/memory.h

  Log Message:
  -----------
  exec.c: Add new address_space_ld*/st* functions

Add new address_space_ld*/st* functions which allow transaction
attributes and error reporting for basic load and stores. These
are named to be in line with the address_space_read/write/rw
buffer operations.

The existing ld/st*_phys functions are now wrappers around
the new functions.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>


  Commit: 66b9b43c42049bcae37668e890fedde9a72c8167
      
https://github.com/qemu/qemu/commit/66b9b43c42049bcae37668e890fedde9a72c8167
  Author: Peter Maydell <address@hidden>
  Date:   2015-04-26 (Sun, 26 Apr 2015)

  Changed paths:
    M exec.c
    M include/qom/cpu.h

  Log Message:
  -----------
  exec.c: Capture the memory attributes for a watchpoint hit

Capture the memory attributes for the transaction which triggered
a watchpoint; this allows CPU specific code to implement features
like ARM's "user-mode only WPs also hit for LDRT/STRT accesses
made from privileged code". This change also correctly passes
through the memory attributes to the underlying device when
a watchpoint access doesn't hit.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>


  Commit: 42874d3a8c6267ff7789a0396843c884b1d0933a
      
https://github.com/qemu/qemu/commit/42874d3a8c6267ff7789a0396843c884b1d0933a
  Author: Peter Maydell <address@hidden>
  Date:   2015-04-26 (Sun, 26 Apr 2015)

  Changed paths:
    M hw/alpha/dp264.c
    M hw/alpha/typhoon.c
    M hw/arm/boot.c
    M hw/arm/highbank.c
    M hw/dma/pl080.c
    M hw/dma/sun4m_iommu.c
    M hw/i386/intel_iommu.c
    M hw/pci-host/apb.c
    M hw/pci/msi.c
    M hw/pci/msix.c
    M hw/s390x/css.c
    M hw/s390x/s390-pci-bus.c
    M hw/s390x/s390-virtio-bus.c
    M hw/s390x/s390-virtio.c
    M hw/s390x/virtio-ccw.c
    M hw/sh4/r2d.c
    M hw/timer/hpet.c
    M monitor.c
    M target-i386/arch_memory_mapping.c

  Log Message:
  -----------
  Switch non-CPU callers from ld/st*_phys to address_space_ld/st*

Switch all the uses of ld/st*_phys to address_space_ld/st*,
except for those cases where the address space is the CPU's
(ie cs->as). This was done with the following script which
generates a Coccinelle patch.

A few over-80-columns lines in the result were rewrapped by
hand where Coccinelle failed to do the wrapping automatically,
as well as one location where it didn't put a line-continuation
'\' when wrapping lines on a change made to a match inside
a macro definition.

===begin===
#!/bin/sh -e
# Usage:
# ./ldst-phys.spatch.sh > ldst-phys.spatch
# spatch -sp_file ldst-phys.spatch -dir . | sed -e '/^+/s/\t/        /g' > 
out.patch
# patch -p1 < out.patch

for FN in ub uw_le uw_be l_le l_be q_le q_be uw l q; do
cat <<EOF
@ cpu_matches_ld_${FN} @
expression E1,E2;
identifier as;
@@

ld${FN}_phys(E1->as,E2)

@ other_matches_ld_${FN} depends on !cpu_matches_ld_${FN} @
expression E1,E2;
@@

-ld${FN}_phys(E1,E2)
+address_space_ld${FN}(E1,E2, MEMTXATTRS_UNSPECIFIED, NULL)

EOF

done

for FN in b w_le w_be l_le l_be q_le q_be w l q; do
cat <<EOF
@ cpu_matches_st_${FN} @
expression E1,E2,E3;
identifier as;
@@

st${FN}_phys(E1->as,E2,E3)

@ other_matches_st_${FN} depends on !cpu_matches_st_${FN} @
expression E1,E2,E3;
@@

-st${FN}_phys(E1,E2,E3)
+address_space_st${FN}(E1,E2,E3, MEMTXATTRS_UNSPECIFIED, NULL)

EOF

done
===endit===

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>


  Commit: 8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc
      
https://github.com/qemu/qemu/commit/8bf5b6a9c1911d2c8473385fc0cebfaaeef42dbc
  Author: Peter Maydell <address@hidden>
  Date:   2015-04-26 (Sun, 26 Apr 2015)

  Changed paths:
    M include/exec/memattrs.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Honour NS bits in page tables

Honour the NS bit in ARM page tables:
 * when adding entries to the TLB, include the Secure/NonSecure
   transaction attribute
 * set the NS bit in the PAR when doing ATS operations

Note that we don't yet correctly use the NSTable bit to
cause the page table walk itself to use the right attributes.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>


  Commit: ebca90e4c3aaaae5ed1ee7c569dea00d5d6ed476
      
https://github.com/qemu/qemu/commit/ebca90e4c3aaaae5ed1ee7c569dea00d5d6ed476
  Author: Peter Maydell <address@hidden>
  Date:   2015-04-26 (Sun, 26 Apr 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Use correct memory attributes for page table walks

Factor out the page table walk memory accesses into their own function,
so that we can specify the correct S/NS memory attributes for them.
This will also provide a place to use the correct endianness and
handle the need for a stage-2 translation when virtualization is
supported.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>


  Commit: 0995bf8cd91b81ec9c1078e37b808794080dc5c0
      
https://github.com/qemu/qemu/commit/0995bf8cd91b81ec9c1078e37b808794080dc5c0
  Author: Peter Maydell <address@hidden>
  Date:   2015-04-26 (Sun, 26 Apr 2015)

  Changed paths:
    M include/exec/memattrs.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add user-mode transaction attribute

Add a transaction attribute indicating that a memory access is being
done from user-mode (unprivileged). This corresponds to an equivalent
signal in ARM AMBA buses.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>


  Commit: 9e1fc5bdfdf94564abf7621c0ef644599196360f
      
https://github.com/qemu/qemu/commit/9e1fc5bdfdf94564abf7621c0ef644599196360f
  Author: Peter Maydell <address@hidden>
  Date:   2015-04-26 (Sun, 26 Apr 2015)

  Changed paths:
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Use attribute info to handle user-only watchpoints

Now that we have memory access attribute information in the watchpoint
checking code, we can correctly implement handling of watchpoints
which should match only on userspace accesses, where LDRT/STRT/LDT/STT
from EL1 are treated as userspace accesses.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>


  Commit: ef7bab8d73580b48bda83b8d16b5eea8a3ac43fe
      
https://github.com/qemu/qemu/commit/ef7bab8d73580b48bda83b8d16b5eea8a3ac43fe
  Author: Peter Maydell <address@hidden>
  Date:   2015-04-26 (Sun, 26 Apr 2015)

  Changed paths:
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Check watchpoints against CPU security state

Fix a TODO in bp_wp_matches() now that we have a function for
testing whether the CPU is currently in Secure mode or not.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>


  Commit: 7ebd5f2e03a00889619bb97e83062d27066d4a26
      
https://github.com/qemu/qemu/commit/7ebd5f2e03a00889619bb97e83062d27066d4a26
  Author: Sergey Fedorov <address@hidden>
  Date:   2015-04-26 (Sun, 26 Apr 2015)

  Changed paths:
    M hw/arm/pxa2xx.c
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: rename c1_coproc to cpacr_el1

Rename the field holding CPACR_EL1 system register state in AArch64
naming style.

Signed-off-by: Sergey Fedorov <address@hidden>
[PMM: also fixed a couple of missed occurrences in cpu.c]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3d5c84ff21a8a7a3bfb3a75154be8905e62f51db
      
https://github.com/qemu/qemu/commit/3d5c84ff21a8a7a3bfb3a75154be8905e62f51db
  Author: Sergey Fedorov <address@hidden>
  Date:   2015-04-26 (Sun, 26 Apr 2015)

  Changed paths:
    M target-arm/cpu.c

  Log Message:
  -----------
  target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled

Signed-off-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
Reviewed-by: Greg Bellows <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4eb276408363aef5435a72a8e818f24220b5edd0
      
https://github.com/qemu/qemu/commit/4eb276408363aef5435a72a8e818f24220b5edd0
  Author: Greg Bellows <address@hidden>
  Date:   2015-04-26 (Sun, 26 Apr 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  Allow ARMv8 SCR.SMD updates

Updated scr_write to always allow updates to the SCR.SMD bit on ARMv8
regardless of whether virtualization (EL2) is enabled or not.

Signed-off-by: Greg Bellows <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: da378d014d27fe3a243bd8e7e060e9eb8c1a272b
      
https://github.com/qemu/qemu/commit/da378d014d27fe3a243bd8e7e060e9eb8c1a272b
  Author: Peter Maydell <address@hidden>
  Date:   2015-04-28 (Tue, 28 Apr 2015)

  Changed paths:
    M cputlb.c
    M dma-helpers.c
    M exec.c
    M hw/alpha/dp264.c
    M hw/alpha/typhoon.c
    M hw/arm/boot.c
    M hw/arm/highbank.c
    M hw/arm/pxa2xx.c
    M hw/dma/pl080.c
    M hw/dma/sun4m_iommu.c
    M hw/i386/intel_iommu.c
    M hw/mips/mips_jazz.c
    M hw/pci-host/apb.c
    M hw/pci-host/prep.c
    M hw/pci/msi.c
    M hw/pci/msix.c
    M hw/s390x/css.c
    M hw/s390x/s390-pci-bus.c
    M hw/s390x/s390-pci-inst.c
    M hw/s390x/s390-virtio-bus.c
    M hw/s390x/s390-virtio.c
    M hw/s390x/virtio-ccw.c
    M hw/sh4/r2d.c
    M hw/timer/hpet.c
    M hw/vfio/pci.c
    M include/exec/cpu-defs.h
    M include/exec/exec-all.h
    A include/exec/memattrs.h
    M include/exec/memory.h
    M include/qom/cpu.h
    M include/sysemu/dma.h
    M ioport.c
    M kvm-all.c
    M memory.c
    M monitor.c
    M scripts/coverity-model.c
    M softmmu_template.h
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/op_helper.c
    M target-i386/arch_memory_mapping.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150427' 
into staging

target-arm queue:
 * memory system updates to support transaction attributes
 * set user-mode and secure attributes for accesses made by ARM CPUs
 * rename c1_coproc to cpacr_el1
 * adjust id_aa64pfr0 when has_el3 CPU property disabled
 * allow ARMv8 SCR.SMD updates

# gpg: Signature made Mon Apr 27 16:14:30 2015 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20150427:
  Allow ARMv8 SCR.SMD updates
  target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled
  target-arm: rename c1_coproc to cpacr_el1
  target-arm: Check watchpoints against CPU security state
  target-arm: Use attribute info to handle user-only watchpoints
  target-arm: Add user-mode transaction attribute
  target-arm: Use correct memory attributes for page table walks
  target-arm: Honour NS bits in page tables
  Switch non-CPU callers from ld/st*_phys to address_space_ld/st*
  exec.c: Capture the memory attributes for a watchpoint hit
  exec.c: Add new address_space_ld*/st* functions
  exec.c: Make address_space_rw take transaction attributes
  exec.c: Convert subpage memory ops to _with_attrs
  Add MemTxAttrs to the IOTLB
  Make CPU iotlb a structure rather than a plain hwaddr
  memory: Replace io_mem_read/write with memory_region_dispatch_read/write
  memory: Define API for MemoryRegionOps to take attrs and return status

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/3d27b09cf6f6...da378d014d27