[Qemu-commits] [qemu/qemu] 0fbf52: target-arm: convert check_ap to ap_to_rw_prot

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 0fbf5238203041f734c51b49778223686f14366b
      
https://github.com/qemu/qemu/commit/0fbf5238203041f734c51b49778223686f14366b
  Author: Andrew Jones <address@hidden>
  Date:   2015-03-16 (Mon, 16 Mar 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: convert check_ap to ap_to_rw_prot

Instead of mixing access permission checking with access permissions
to page protection flags translation, just do the translation, and
leave it to the caller to check the protection flags against the access
type. Also rename to ap_to_rw_prot to better describe the new behavior.

Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d76951b65dfb1be4e41cfae6abebf8db7a1243a3
      
https://github.com/qemu/qemu/commit/d76951b65dfb1be4e41cfae6abebf8db7a1243a3
  Author: Andrew Jones <address@hidden>
  Date:   2015-03-16 (Mon, 16 Mar 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: fix get_phys_addr_v6/SCTLR_AFE access check

Introduce simple_ap_to_rw_prot(), which has the same behavior as
ap_to_rw_prot(), but takes the 2-bit simple AP[2:1] instead of
the 3-bit AP[2:0]. Use this in get_phys_addr_v6 when SCTLR_AFE
is set, as that bit indicates we should be using the simple AP
format.

It's unlikely this path is getting used. I don't see CR_AFE
getting used by Linux, so possibly not. If it had been, then
the check would have been wrong for all but AP[2:1] = 0b11.
Anyway, this should fix it up, in case it ever does get used.

Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d8e052b387635639a6ba4a09a7874fd2f113b218
      
https://github.com/qemu/qemu/commit/d8e052b387635639a6ba4a09a7874fd2f113b218
  Author: Andrew Jones <address@hidden>
  Date:   2015-03-16 (Mon, 16 Mar 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: get_phys_addr_lpae: more xn control

This patch makes the following changes to the determination of
whether an address is executable, when translating addresses
using LPAE.

1. No longer assumes that PL0 can't execute when it can't read.
   It can in AArch64, a difference from AArch32.
2. Use va_size == 64 to determine we're in AArch64, rather than
   arm_feature(env, ARM_FEATURE_V8), which is insufficient.
3. Add additional XN determinants
   - NS && is_secure && (SCR & SCR_SIF)
   - WXN && (prot & PAGE_WRITE)
   - AArch64: (prot_PL0 & PAGE_WRITE)
   - AArch32: UWXN && (prot_PL0 & PAGE_WRITE)
   - XN determination should also work in secure mode (untested)
   - XN may even work in EL2 (currently impossible to test)
4. Cleans up the bloated PAGE_EXEC condition - by removing it.

The helper get_S1prot is introduced. It may even work in EL2,
when support for that comes, but, as the function name implies,
it only works for stage 1 translations.

Signed-off-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f0bb55890a173cb1e9e87d608647cac70f8f9dd4
      
https://github.com/qemu/qemu/commit/f0bb55890a173cb1e9e87d608647cac70f8f9dd4
  Author: Eric Auger <address@hidden>
  Date:   2015-03-16 (Mon, 16 Mar 2015)

  Changed paths:
    M hw/intc/arm_gic_kvm.c

  Log Message:
  -----------
  hw/intc/arm_gic: Initialize the vgic in the realize function

This patch forces vgic initialization in the vgic realize function.
It uses a new group/attribute that allows such operation:
KVM_DEV_ARM_VGIC_GRP_CTRL/KVM_DEV_ARM_VGIC_CTRL_INIT

This earlier initialization allows, for example, to setup VFIO
signaling and irqfd after vgic initialization, on a reset notifier.

Signed-off-by: Eric Auger <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: da3e53ddcb0ca924da97ca5a35605fc554aa3e05
      
https://github.com/qemu/qemu/commit/da3e53ddcb0ca924da97ca5a35605fc554aa3e05
  Author: Peter Maydell <address@hidden>
  Date:   2015-03-16 (Mon, 16 Mar 2015)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Fix handling of STM (user) with r15 in register list

The A32 encoding of LDM distinguishes LDM (user) from LDM (exception
return) based on whether r15 is in the register list. However for
STM (user) there is no equivalent distinction. We were incorrectly
treating "r15 in list" as indicating exception return for both LDM
and STM, with the result that an STM (user) involving r15 went into
an infinite loop. Fix this; note that the value stored for r15
in this case is the current PC regardless of our current mode.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: fcf83ab103dce6d2951f24f48e30820e7dbb3622
      
https://github.com/qemu/qemu/commit/fcf83ab103dce6d2951f24f48e30820e7dbb3622
  Author: Peter Maydell <address@hidden>
  Date:   2015-03-16 (Mon, 16 Mar 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Ignore low bit of PC in M-profile exception return

For the ARM M-profile cores, exception return pops various registers
including the PC from the stack. The architecture defines that if the
lowest bit in the new PC value is set (ie the PC is not halfword
aligned) then behaviour is UNPREDICTABLE. In practice hardware
implementations seem to simply ignore the low bit, and some buggy
RTOSes incorrectly rely on this. QEMU's behaviour was architecturally
permitted, but bringing QEMU into line with the hardware behaviour
allows more guest code to run. We log the situation as a guest error.

This was reported as LP:1428657.

Reported-by: Anders Esbensen <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b8d43285a4db12156c40ba6fdbd8002c383fcbca
      
https://github.com/qemu/qemu/commit/b8d43285a4db12156c40ba6fdbd8002c383fcbca
  Author: Mikhail Ilyin <address@hidden>
  Date:   2015-03-16 (Mon, 16 Mar 2015)

  Changed paths:
    M linux-user/arm/target_cpu.h
    M linux-user/main.c

  Log Message:
  -----------
  linux-user: Access correct register for get/set_tls syscalls on ARM TZ CPUs

When support was added for TrustZone to ARM CPU emulation, we failed
to correctly update the support for the linux-user implementation of
the get/set_tls syscalls. This meant that accesses to the TPIDRURO
register via the syscalls were always using the non-secure copy of
the register even if native MRC/MCR accesses were using the secure
register. This inconsistency caused most binaries to segfault on startup
if the CPU type was explicitly set to one of the TZ-enabled ones like
cortex-a15. (The default "any" CPU doesn't have TZ enabled and so is
not affected.)

Use access_secure_reg() to determine whether we should be using
the secure or the nonsecure copy of TPIDRURO when emulating these
syscalls.

Signed-off-by: Mikhail Ilyin <address@hidden>
Message-id: address@hidden
[PMM: rewrote commit message to more clearly explain the issue
 and its consequences.]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dcf848c478dd8765bd4f746fc4e80eaad44cf87d
      
https://github.com/qemu/qemu/commit/dcf848c478dd8765bd4f746fc4e80eaad44cf87d
  Author: Peter Maydell <address@hidden>
  Date:   2015-03-16 (Mon, 16 Mar 2015)

  Changed paths:
    M hw/intc/arm_gic_kvm.c
    M linux-user/arm/target_cpu.h
    M linux-user/main.c
    M target-arm/helper.c
    M target-arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150316' 
into staging

target-arm queue:
 * fix handling of execute-never bits in page table walks
 * tell kernel to initialize KVM GIC in realize function
 * fix handling of STM (user) with r15 in register list
 * ignore low bit of PC in M-profile exception return
 * fix linux-user get/set_tls syscalls on CPUs with TZ

# gpg: Signature made Mon Mar 16 12:39:04 2015 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20150316:
  linux-user: Access correct register for get/set_tls syscalls on ARM TZ CPUs
  target-arm: Ignore low bit of PC in M-profile exception return
  target-arm: Fix handling of STM (user) with r15 in register list
  hw/intc/arm_gic: Initialize the vgic in the realize function
  target-arm: get_phys_addr_lpae: more xn control
  target-arm: fix get_phys_addr_v6/SCTLR_AFE access check
  target-arm: convert check_ap to ap_to_rw_prot

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/307146cb9359...dcf848c478dd