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[Qemu-commits] [qemu/qemu] fe6ac4: target_arm: Remove memory region init
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[Qemu-commits] [qemu/qemu] fe6ac4: target_arm: Remove memory region init from armv7m_... |
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Date: |
Thu, 05 Feb 2015 07:30:10 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: fe6ac447add80978c1bf988c3ef4a7ce8aab2fa0
https://github.com/qemu/qemu/commit/fe6ac447add80978c1bf988c3ef4a7ce8aab2fa0
Author: Alistair Francis <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M hw/arm/armv7m.c
M hw/arm/stellaris.c
M include/hw/arm/arm.h
Log Message:
-----------
target_arm: Remove memory region init from armv7m_init
This patch moves the memory region init code from the
armv7m_init function to the stellaris_init function
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 8b47b7da29121ecddb173dd4afb82d6fb0eece37
https://github.com/qemu/qemu/commit/8b47b7da29121ecddb173dd4afb82d6fb0eece37
Author: Alistair Francis <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M hw/arm/armv7m.c
M hw/arm/stellaris.c
M include/hw/arm/arm.h
Log Message:
-----------
target_arm: Parameterise the irq lines for armv7m_init
This patch allows the board to specifiy the number of NVIC interrupt
lines when using armv7m_init.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
[PMM: removed stale FIXME comment]
Signed-off-by: Peter Maydell <address@hidden>
Commit: 569b49f864e7593a14182acae5a7f5981f6ec24f
https://github.com/qemu/qemu/commit/569b49f864e7593a14182acae5a7f5981f6ec24f
Author: Greg Bellows <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/helper.c
Log Message:
-----------
target-arm: Fix RVBAR_EL1 register encoding
Fix the RVBAR_EL1 CP register opc2 encoding from 2 to 1
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: be8e8128595b41b9f609c1507e67d121e65e7173
https://github.com/qemu/qemu/commit/be8e8128595b41b9f609c1507e67d121e65e7173
Author: Greg Bellows <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/helper.c
Log Message:
-----------
target-arm: Add extended RVBAR support
Added RVBAR_EL2 and RVBAR_EL3 CP register support. All RVBAR_EL# registers
point to the same location and only the highest EL version exists at any one
time.
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 5097227c15aa89baec1123aac25dd9500a62684d
https://github.com/qemu/qemu/commit/5097227c15aa89baec1123aac25dd9500a62684d
Author: Greg Bellows <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M hw/arm/boot.c
M target-arm/cpu.c
Log Message:
-----------
target-arm: Change reset to highest available EL
Update to arm_cpu_reset() to reset into the highest available exception level
based on the set ARM features.
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 884b4deeeb8b158ed3db5792161902bc8b41b62d
https://github.com/qemu/qemu/commit/884b4deeeb8b158ed3db5792161902bc8b41b62d
Author: Greg Bellows <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/helper.c
Log Message:
-----------
target-arm: Add missing SP_ELx register definition
Added CP register definitions for SP_EL1 and SP_EL2.
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7a0e58fa648736a75f2a6943afd2ab08ea15b8e0
https://github.com/qemu/qemu/commit/7a0e58fa648736a75f2a6943afd2ab08ea15b8e0
Author: Peter Maydell <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/cpu.h
M target-arm/helper.c
Log Message:
-----------
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW
We currently mark ARM coprocessor/system register definitions with
the flag ARM_CP_NO_MIGRATE for two different reasons:
1) register is an alias on to state that's also visible via
some other register, and that other register is the one
responsible for migrating the state
2) register is not actually state at all (for instance the TLB
or cache maintenance operation "registers") and it makes no
sense to attempt to migrate it or otherwise access the raw state
This works fine for identifying which registers should be ignored
when performing migration, but we also use the same functions for
synchronizing system register state between QEMU and the kernel
when using KVM. In this case we don't want to try to sync state
into registers in category 2, but we do want to sync into registers
in category 1, because the kernel might have picked a different
one of the aliases as its choice for which one to expose for
migration. (In particular, on 32 bit hosts the kernel will
expose the state in the AArch32 version of the register, but
TCG's convention is to mark the AArch64 version as the version
to migrate, even if the CPU being emulated happens to be 32 bit,
so almost all system registers will hit this issue now that we've
added AArch64 system emulation.)
Fix this by splitting the NO_MIGRATE flag in two (ALIAS and NO_RAW)
corresponding to the two different reasons we might not want to
migrate a register. When setting up the TCG list of registers to
migrate we honour both flags; when populating the list from KVM,
only ignore registers which are NO_RAW.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Message-id: address@hidden
[PMM: changed ARM_CP_NO_MIGRATE to ARM_CP_ALIAS on new SP_EL1 and
SP_EL2 reginfo stanzas since there was a (semantic) merge conflict
with the patchset that added those]
Commit: 375421ccaeebae8212eb8f9a36835ad4d9dc60a8
https://github.com/qemu/qemu/commit/375421ccaeebae8212eb8f9a36835ad4d9dc60a8
Author: Peter Maydell <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/helper.c
Log Message:
-----------
target-arm: Add checks that cpreg raw accesses are handled
Add assertion checking when cpreg structures are registered that they
either forbid raw-access attempts or at least make an attempt at
handling them. Also add an assert in the raw-accessor-of-last-resort,
to avoid silently doing a read or write from offset zero, which is
actually AArch32 CPU register r0.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Greg Bellows <address@hidden>
Commit: dabf005808f0830313f313c76a492294ef3bce6a
https://github.com/qemu/qemu/commit/dabf005808f0830313f313c76a492294ef3bce6a
Author: Xiangyu Hu <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/helper-a64.c
Log Message:
-----------
Fix FMULX not squashing denormalized inputs when FZ is set.
While FMULX returns a 2.0f float when two operators are infinity and
zero, those operators should be unpacked from raw inputs first. Inconsistent
cases would occur when operators are denormalized floats in flush-to-zero
mode. A wrong codepath will be entered and 2.0f will not be returned
without this patch.
Fix by checking whether inputs need to be flushed before running into
different codepaths.
Signed-off-by: Xiangyu Hu <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: a8eb6e19991d1a7a6a7b04ac447548d30d75eb4a
https://github.com/qemu/qemu/commit/a8eb6e19991d1a7a6a7b04ac447548d30d75eb4a
Author: Peter Maydell <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/helper-a64.c
Log Message:
-----------
target-arm: Squash input denormals in FRECPS and FRSQRTS
The helper functions for FRECPS and FRSQRTS have special case
handling that includes checks for zero inputs, so squash input
denormals if necessary before those checks. This fixes incorrect
output when the FPCR DZ bit is set to enable squashing of input
denormals.
Signed-off-by: Peter Maydell <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Commit: 45140a57675ecb4b0daee71bf145c24dbdf9429c
https://github.com/qemu/qemu/commit/45140a57675ecb4b0daee71bf145c24dbdf9429c
Author: Kirill Batuzov <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/translate.c
Log Message:
-----------
target-arm: check that LSB <= MSB in BFI instruction
The documentation states that if LSB > MSB in BFI instruction behaviour
is unpredictable. Currently QEMU crashes because of assertion failure in
this case:
tcg/tcg-op.h:2061: tcg_gen_deposit_i32: Assertion `len <= 32' failed.
While assertion failure may meet the "unpredictable" definition this
behaviour is undesirable because it allows an unprivileged guest program
to crash the emulator with the OS and other programs.
This patch addresses the issue by throwing illegal instruction exception
if LSB > MSB. Only ARM decoder is affected because Thumb decoder already
has this check in place.
To reproduce issue run the following program
int main(void) {
asm volatile (".long 0x07c00c12" :: );
return 0;
}
compiled with
gcc -marm -static badop_arm.c -o badop_arm
Signed-off-by: Kirill Batuzov <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 587078f0ed6371f83a54228faed70867d3137954
https://github.com/qemu/qemu/commit/587078f0ed6371f83a54228faed70867d3137954
Author: Laszlo Ersek <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: explain device-to-transport mapping in create_virtio_devices()
Signed-off-by: Laszlo Ersek <address@hidden>
Message-id: address@hidden
[PMM: added note recommending UUIDs]
Signed-off-by: Peter Maydell <address@hidden>
Commit: 8f3ae2ae2d02727f6d56610c09d7535e43650dd4
https://github.com/qemu/qemu/commit/8f3ae2ae2d02727f6d56610c09d7535e43650dd4
Author: Peter Maydell <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M include/exec/cpu_ldst.h
Log Message:
-----------
cpu_ldst.h: Allow NB_MMU_MODES to be 7
Support guest CPUs which need 7 MMU index values.
Add a comment about what would be required to raise the limit
further (trivial for 8, TCG backend rework for 9 or more).
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 6d54ed3c93f1e05a483201b087142998381c9be8
https://github.com/qemu/qemu/commit/6d54ed3c93f1e05a483201b087142998381c9be8
Author: Peter Maydell <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/cpu.h
Log Message:
-----------
target-arm: Make arm_current_el() return sensible values for M profile
Although M profile doesn't have the same concept of exception level
as A profile, it does have a notion of privileged versus not, which
we currently track in the privmode TB flag. Support returning this
information if arm_current_el() is called on an M profile core, so
that we can identify the correct MMU index to use (and put the MMU
index in the TB flags) without having to special-case M profile.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Commit: 949013ce111eb64f8bc81cf9a9f1cefd6a1678c3
https://github.com/qemu/qemu/commit/949013ce111eb64f8bc81cf9a9f1cefd6a1678c3
Author: Peter Maydell <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STT
The LDT/STT (load/store unprivileged) instruction decode was using
the wrong MMU index value. This meant that instead of these insns
being "always access as if user-mode regardless of current privilege"
they were "always access as if kernel-mode regardless of current
privilege". This went unnoticed because AArch64 Linux doesn't use
these instructions.
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
---
I'm not counting this as a security issue because I'm assuming
nobody treats TCG guests as a security boundary (certainly I
would not recommend doing so...)
Commit: c1e3781090b9d36c60e1a254ba297cb34011d3d4
https://github.com/qemu/qemu/commit/c1e3781090b9d36c60e1a254ba297cb34011d3d4
Author: Peter Maydell <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/cpu.h
M target-arm/helper.c
M target-arm/translate-a64.c
M target-arm/translate.c
M target-arm/translate.h
Log Message:
-----------
target-arm: Define correct mmu_idx values and pass them in TB flags
We currently claim that for ARM the mmu_idx should simply be the current
exception level. However this isn't actually correct -- secure EL0 and EL1
should have separate indexes from non-secure EL0 and EL1 since their
VA->PA mappings may differ. We also will want an index for stage 2
translations when we properly support EL2.
Define and document all seven mmu index values that we require, and
pass the mmu index in the TB flags rather than exception level or
priv/user bit.
This change doesn't update the get_phys_addr() code, so our page
table walking still assumes a simplistic "user or priv?" model for
the moment.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
---
This leaves some odd gaps in the TB flags usage. I will circle
back and clean this up later (including moving the other common
flags like the singlestep ones to the top of the flags word),
but I didn't want to bloat this patchseries further.
Commit: 579d21cce63f3dd2f6ee49c0b02a14e92cb4a836
https://github.com/qemu/qemu/commit/579d21cce63f3dd2f6ee49c0b02a14e92cb4a836
Author: Peter Maydell <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/translate-a64.c
M target-arm/translate.c
Log Message:
-----------
target-arm: Use correct mmu_idx for unprivileged loads and stores
The MMU index to use for unprivileged loads and stores is more
complicated than we currently implement:
* for A64, it should be "if at EL1, access as if EL0; otherwise
access at current EL"
* for A32/T32, it should be "if EL2, UNPREDICTABLE; otherwise
access as if at EL0".
In both cases, if we want to make the access for Secure EL0
this is not the same mmu_idx as for Non-Secure EL0.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Commit: 0dfef7b58f0c24b463e36630f08a45e93012b33a
https://github.com/qemu/qemu/commit/0dfef7b58f0c24b463e36630f08a45e93012b33a
Author: Peter Maydell <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/cpu.h
Log Message:
-----------
target-arm: Don't define any MMU_MODE*_SUFFIXes
target-arm doesn't use any of the MMU-mode specific cpu ldst
accessor functions. Suppress their generation by not defining
any of the MMU_MODE*_SUFFIX macros. ("user" and "kernel" are
too simplistic as descriptions of indexes 0 and 1 anyway.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Commit: 060e8a48cb84d41d4ac36e4bb29d9c14ed7168b6
https://github.com/qemu/qemu/commit/060e8a48cb84d41d4ac36e4bb29d9c14ed7168b6
Author: Peter Maydell <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/helper.c
Log Message:
-----------
target-arm: Split AArch64 cases out of ats_write()
Instead of simply reusing ats_write() as the handler for both AArch32
and AArch64 address translation operations, use a different function
for each with the common code in a third function. This is necessary
because the semantics for selecting the right translation regime are
different; we are only getting away with sharing currently because
we don't support EL2 and only support EL3 in AArch32.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Commit: d364970287c0ba68979711928c15e5d37414f87f
https://github.com/qemu/qemu/commit/d364970287c0ba68979711928c15e5d37414f87f
Author: Peter Maydell <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/helper.c
Log Message:
-----------
target-arm: Pass mmu_idx to get_phys_addr()
Make all the callers of get_phys_addr() pass it the correct
mmu_idx rather than just a simple "is_user" flag. This includes
properly decoding the AT/ATS system instructions; we include the
logic for handling all the opc1/opc2 cases because we'll need
them later for supporting EL2/EL3, even if we don't have the
regdef stanzas yet.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Commit: 0480f69abf849ca0d48928cc6c669c1c7264239b
https://github.com/qemu/qemu/commit/0480f69abf849ca0d48928cc6c669c1c7264239b
Author: Peter Maydell <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/helper.c
Log Message:
-----------
target-arm: Use mmu_idx in get_phys_addr()
Now we have the mmu_idx in get_phys_addr(), use it correctly to
determine the behaviour of virtual to physical address translations,
rather than using just an is_user flag and the current CPU state.
Some TODO comments have been added to indicate where changes will
need to be made to add EL2 and 64-bit EL3 support.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Commit: 554b0b09aec4579c8164f363b18a263150e91a2c
https://github.com/qemu/qemu/commit/554b0b09aec4579c8164f363b18a263150e91a2c
Author: Peter Maydell <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/helper.c
Log Message:
-----------
target-arm: Reindent ancient page-table-walk code
A few of the oldest parts of the page-table-walk code have broken indent
(either hardcoded tabs or two-spaces). Reindent these sections.
For ease of review, this patch does not touch the brace style and
so is a whitespace-only change.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Commit: 87c3d486150917c8e286d29166c98a2035377b52
https://github.com/qemu/qemu/commit/87c3d486150917c8e286d29166c98a2035377b52
Author: Peter Maydell <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/helper.c
Log Message:
-----------
target-arm: Fix brace style in reindented code
This patch fixes the brace style in the code reindented in the
previous commit.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Commit: d4eba98df4cca016c3cc88f519164b5c0e434e69
https://github.com/qemu/qemu/commit/d4eba98df4cca016c3cc88f519164b5c0e434e69
Author: Peter Maydell <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M disas/libvixl/README
M disas/libvixl/a64/assembler-a64.h
M disas/libvixl/a64/constants-a64.h
M disas/libvixl/a64/decoder-a64.h
M disas/libvixl/a64/disasm-a64.cc
M disas/libvixl/a64/disasm-a64.h
M disas/libvixl/a64/instructions-a64.cc
M disas/libvixl/a64/instructions-a64.h
M disas/libvixl/globals.h
M disas/libvixl/utils.cc
M disas/libvixl/utils.h
Log Message:
-----------
disas/libvixl: Update to upstream VIXL 1.7
Update our copy of libvixl to upstream's 1.7 release.
This includes upstream's fix for the issue we had a local
patch for in commit 94cc44a9e.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 8d298bee09f0cb8997c87006c0ff3a49a419837b
https://github.com/qemu/qemu/commit/8d298bee09f0cb8997c87006c0ff3a49a419837b
Author: Peter Maydell <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M disas/arm-a64.cc
Log Message:
-----------
disas/arm-a64.cc: Tell libvixl correct code addresses
disassembling relative branches in code which doesn't reside at
what the guest CPU would think its execution address is. Use
the new MapCodeAddress() API to tell libvixl where the code is
from the guest CPU's point of view so it can get the target
addresses right.
Previous disassembly:
0x0000000040000000: 580000c0 ldr x0, pc+24 (addr 0x7f6cb7020434)
0x0000000040000004: aa1f03e1 mov x1, xzr
0x0000000040000008: aa1f03e2 mov x2, xzr
0x000000004000000c: aa1f03e3 mov x3, xzr
0x0000000040000010: 58000084 ldr x4, pc+16 (addr 0x7f6cb702042c)
0x0000000040000014: d61f0080 br x4
Fixed disassembly:
0x0000000040000000: 580000c0 ldr x0, pc+24 (addr 0x40000018)
0x0000000040000004: aa1f03e1 mov x1, xzr
0x0000000040000008: aa1f03e2 mov x2, xzr
0x000000004000000c: aa1f03e3 mov x3, xzr
0x0000000040000010: 58000084 ldr x4, pc+16 (addr 0x40000020)
0x0000000040000014: d61f0080 br x4
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 568bab1fb8cb2237f0134c4c5ffbc2a8ea26df69
https://github.com/qemu/qemu/commit/568bab1fb8cb2237f0134c4c5ffbc2a8ea26df69
Author: Pranavkumar Sawargaonkar <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/kvm64.c
Log Message:
-----------
target-arm: KVM64: Get and Sync up guest register state like kvm32.
This patch adds:
1. Call write_kvmstate_to_list() and write_list_to_cpustate()
in kvm_arch_get_registers() to sync guest register state.
2. Call write_list_to_kvmstate() in kvm_arch_put_registers()
to sync guest register state.
These changes are already there for kvm32 in target-arm/kvm32.c.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Pranavkumar Sawargaonkar <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 84f2bed3cf505f90b7918e2de32e11da27160563
https://github.com/qemu/qemu/commit/84f2bed3cf505f90b7918e2de32e11da27160563
Author: Pranavkumar Sawargaonkar <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/cpu.c
M target-arm/cpu.h
Log Message:
-----------
target-arm: Guest cpu endianness determination for virtio KVM ARM/ARM64
This patch implements a fucntion pointer "virtio_is_big_endian"
from "CPUClass" structure for arm/arm64.
Function arm_cpu_is_big_endian() is added to determine and
return the guest cpu endianness to virtio.
This is required for running cross endian guests with virtio on ARM/ARM64.
Signed-off-by: Pranavkumar Sawargaonkar <address@hidden>
Message-id: address@hidden
[PMM: check CPSR_E in env->cpsr_uncached, not env->pstate.]
Signed-off-by: Peter Maydell <address@hidden>
Commit: fc1792e9aa36227ee9994757974f9397684e1a48
https://github.com/qemu/qemu/commit/fc1792e9aa36227ee9994757974f9397684e1a48
Author: Ildar Isaev <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M target-arm/helper.c
Log Message:
-----------
target-arm: fix for exponent comparison in recpe_f64
f64 exponent in HELPER(recpe_f64) should be compared to 2045 rather than 1023
(FPRecipEstimate in ARMV8 spec). This fixes incorrect underflow handling when
flushing denormals to zero in the FRECPE instructions operating on 64-bit
values.
Signed-off-by: Ildar Isaev <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: cd07b19307bd185dccfd39052ac66d2730b32857
https://github.com/qemu/qemu/commit/cd07b19307bd185dccfd39052ac66d2730b32857
Author: Peter Maydell <address@hidden>
Date: 2015-02-05 (Thu, 05 Feb 2015)
Changed paths:
M disas/arm-a64.cc
M disas/libvixl/README
M disas/libvixl/a64/assembler-a64.h
M disas/libvixl/a64/constants-a64.h
M disas/libvixl/a64/decoder-a64.h
M disas/libvixl/a64/disasm-a64.cc
M disas/libvixl/a64/disasm-a64.h
M disas/libvixl/a64/instructions-a64.cc
M disas/libvixl/a64/instructions-a64.h
M disas/libvixl/globals.h
M disas/libvixl/utils.cc
M disas/libvixl/utils.h
M hw/arm/armv7m.c
M hw/arm/boot.c
M hw/arm/stellaris.c
M hw/arm/virt.c
M include/exec/cpu_ldst.h
M include/hw/arm/arm.h
M target-arm/cpu.c
M target-arm/cpu.h
M target-arm/helper-a64.c
M target-arm/helper.c
M target-arm/kvm64.c
M target-arm/translate-a64.c
M target-arm/translate.c
M target-arm/translate.h
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150205'
into staging
target-arm queue:
* refactor/clean up armv7m_init()
* some initial cleanup in the direction of supporting 64-bit EL3
* fix broken synchronization of registers between QEMU and KVM
for 32-bit ARM hosts (which among other things broke memory
access via gdbstub)
* fix flush-to-zero handling in FMULX, FRECPS, FRSQRTS and FRECPE
* don't crash QEMU for UNPREDICTABLE BFI insns in A32 encoding
* explain why virt board's device-to-transport mapping code is
the way it is
* implement mmu_idx values which match the architectural
distinctions, and introduce the concept of a translation
regime to get_phys_addr() rather than incorrectly looking
at the current CPU state
* update to upstream VIXL 1.7 (gives us correct code addresses
when dissassembling pc-relative references)
* sync system register state between KVM and QEMU for 64-bit ARM
* support virtio on big-endian guests by implementing the
"which endian is the guest now?" CPU method
# gpg: Signature made Thu 05 Feb 2015 14:02:16 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
* remotes/pmaydell/tags/pull-target-arm-20150205: (28 commits)
target-arm: fix for exponent comparison in recpe_f64
target-arm: Guest cpu endianness determination for virtio KVM ARM/ARM64
target-arm: KVM64: Get and Sync up guest register state like kvm32.
disas/arm-a64.cc: Tell libvixl correct code addresses
disas/libvixl: Update to upstream VIXL 1.7
target-arm: Fix brace style in reindented code
target-arm: Reindent ancient page-table-walk code
target-arm: Use mmu_idx in get_phys_addr()
target-arm: Pass mmu_idx to get_phys_addr()
target-arm: Split AArch64 cases out of ats_write()
target-arm: Don't define any MMU_MODE*_SUFFIXes
target-arm: Use correct mmu_idx for unprivileged loads and stores
target-arm: Define correct mmu_idx values and pass them in TB flags
target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STT
target-arm: Make arm_current_el() return sensible values for M profile
cpu_ldst.h: Allow NB_MMU_MODES to be 7
hw/arm/virt: explain device-to-transport mapping in create_virtio_devices()
target-arm: check that LSB <= MSB in BFI instruction
target-arm: Squash input denormals in FRECPS and FRSQRTS
Fix FMULX not squashing denormalized inputs when FZ is set.
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/2c918a245ca2...cd07b19307bd
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